JPS6415861A - Load distribution system for parallel logical simulator - Google Patents

Load distribution system for parallel logical simulator

Info

Publication number
JPS6415861A
JPS6415861A JP62171555A JP17155587A JPS6415861A JP S6415861 A JPS6415861 A JP S6415861A JP 62171555 A JP62171555 A JP 62171555A JP 17155587 A JP17155587 A JP 17155587A JP S6415861 A JPS6415861 A JP S6415861A
Authority
JP
Japan
Prior art keywords
time
processing
gate
processors
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62171555A
Other languages
Japanese (ja)
Inventor
Shintaro Shimogoori
Tetsuo Kage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62171555A priority Critical patent/JPS6415861A/en
Publication of JPS6415861A publication Critical patent/JPS6415861A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To reduce the idle time and to shorten the processing time of each processor by performing the synchronization of each processor at an optional time within a period during which the gate evaluation of the present time point ends and that of the next time point starts. CONSTITUTION:A pre-processing means 1 stores an event received from another processor and at the same time extracts another event at that time to update the gate output value. A gate evaluating means 2 calculates successively the output value of each gate from the event of each relevant time to store these values and at the same time informs them to other processors. An end report means 3 delivers a report when the means ends the processing of the present time. An end report means 4 monitors the ends of all processors are reported or not. Each processor performs immediately the pre-processing of each time after the end report and ends this processing when the end reports received from all processors are confirmed. Then all processors starts their processes at one time and each processor performs the gate evaluation after the pre- processing of each time point.
JP62171555A 1987-07-09 1987-07-09 Load distribution system for parallel logical simulator Pending JPS6415861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62171555A JPS6415861A (en) 1987-07-09 1987-07-09 Load distribution system for parallel logical simulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62171555A JPS6415861A (en) 1987-07-09 1987-07-09 Load distribution system for parallel logical simulator

Publications (1)

Publication Number Publication Date
JPS6415861A true JPS6415861A (en) 1989-01-19

Family

ID=15925302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62171555A Pending JPS6415861A (en) 1987-07-09 1987-07-09 Load distribution system for parallel logical simulator

Country Status (1)

Country Link
JP (1) JPS6415861A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8036761B2 (en) 2006-09-27 2011-10-11 Fujitsu Ten Limited Simulation hardware apparatus comprising vehicle model

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8036761B2 (en) 2006-09-27 2011-10-11 Fujitsu Ten Limited Simulation hardware apparatus comprising vehicle model

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