JPS6412624A - Adaptive impedance matching system - Google Patents

Adaptive impedance matching system

Info

Publication number
JPS6412624A
JPS6412624A JP16841887A JP16841887A JPS6412624A JP S6412624 A JPS6412624 A JP S6412624A JP 16841887 A JP16841887 A JP 16841887A JP 16841887 A JP16841887 A JP 16841887A JP S6412624 A JPS6412624 A JP S6412624A
Authority
JP
Japan
Prior art keywords
matching circuit
echo peak
circuit
sub
matching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16841887A
Other languages
Japanese (ja)
Inventor
Akira Sasama
Setsu Fukuda
Toshitaka Tsuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16841887A priority Critical patent/JPS6412624A/en
Publication of JPS6412624A publication Critical patent/JPS6412624A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress as echo peak in a prescribed reference level by changing over circuits so as to connect a sub-matching circuit in parallel with a major matching circuit in adding a bridged tap to a communication line. CONSTITUTION:When the bridged tape 11 is added in the vicinity of a hybrid transfer 12, the echo peak value exceeds largely the highest level of a reference circuit 16 and the matching circuit of a main matching circuit group 19 cannot decrease the echo peak value. In detecting the state, an adaptive control circuit 17 sends a control signal to a sub selection circuit 40, which is driven to connect a sub matching circuit BNN 41 being a parallel impedance with lines l1, l2 thereby decreasing the echo peak. In this case, while the sub matching circuit BNN 41 is connected, the matching is started again from the lowest reference level to change over matching circuits BN1-BNn of the main matching circuit group 19. Thus, the echo peak is suppressed to a prescribed reference levle or below.
JP16841887A 1987-07-06 1987-07-06 Adaptive impedance matching system Pending JPS6412624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16841887A JPS6412624A (en) 1987-07-06 1987-07-06 Adaptive impedance matching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16841887A JPS6412624A (en) 1987-07-06 1987-07-06 Adaptive impedance matching system

Publications (1)

Publication Number Publication Date
JPS6412624A true JPS6412624A (en) 1989-01-17

Family

ID=15867759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16841887A Pending JPS6412624A (en) 1987-07-06 1987-07-06 Adaptive impedance matching system

Country Status (1)

Country Link
JP (1) JPS6412624A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999066683A1 (en) * 1998-06-16 1999-12-23 Rc Networks Impedance matching interface for transmission loop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999066683A1 (en) * 1998-06-16 1999-12-23 Rc Networks Impedance matching interface for transmission loop

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