JPS6399483U - - Google Patents

Info

Publication number
JPS6399483U
JPS6399483U JP19629386U JP19629386U JPS6399483U JP S6399483 U JPS6399483 U JP S6399483U JP 19629386 U JP19629386 U JP 19629386U JP 19629386 U JP19629386 U JP 19629386U JP S6399483 U JPS6399483 U JP S6399483U
Authority
JP
Japan
Prior art keywords
signal
circuit
video signal
processing circuit
recording medium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19629386U
Other languages
Japanese (ja)
Other versions
JPH0741264Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986196293U priority Critical patent/JPH0741264Y2/en
Publication of JPS6399483U publication Critical patent/JPS6399483U/ja
Application granted granted Critical
Publication of JPH0741264Y2 publication Critical patent/JPH0741264Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る映像信号処理回路のブロ
ツク図、第2図は再生回路のブロツク図、第3図
は第1図に示す回路の動作を示すタイミングチヤ
ート、第4図は磁気デイスクの信号記録状態を説
明する図である。 1…磁気デイスク、2…磁気ヘツド、3…PG
コイル、8…マスキング回路、9…メモリ回路、
12…PGヨーク。
Fig. 1 is a block diagram of a video signal processing circuit according to the present invention, Fig. 2 is a block diagram of a reproducing circuit, Fig. 3 is a timing chart showing the operation of the circuit shown in Fig. 1, and Fig. 4 is a block diagram of a magnetic disk. It is a figure explaining a signal recording state. 1...Magnetic disk, 2...Magnetic head, 3...PG
Coil, 8...masking circuit, 9...memory circuit,
12...PG York.

Claims (1)

【実用新案登録請求の範囲】 同心円状信号トラツクの信号記録開始点を規
定すべき基準信号発生器が配備された信号記録媒
体から、一対の信号トラツクに記録されている一
連のフイールド信号を連続して再生し、後段の回
路へ送出する映像信号処理回路に於いて、信号記
録媒体から再生された合成映像信号は、該信号に
含まれる垂直同期信号を分離する同期分離回路6
,7を経て、前記基準信号発生器から得られる基
準信号がトリガー信号として接続されたマスキン
グ回路8へ連結し、該マスキング回路8は、トリ
ガー信号の入力時点を基準とする所定期間だけ前
記同期分離回路6,7の出力信号を遮断して真の
垂直同期信号を作成し、後段回路へ送出すること
を特徴とする映像信号処理回路。 マスキング回路8は、トリガー信号の入力に
より所定期間だけローレベルとなるパルス信号を
作成するパルス整形回路17と、該パルス整形回
路17及び垂直同期回路6,7の出力信号が各入
力端に接続されたアンド回路18とから構成され
る実用新案登録請求の範囲第1項に記載の映像信
号処理回路。 基準信号発生器は信号記録媒体となる磁気デ
イスク1に配備したPGヨーク12によつて構成
される実用新案登録請求の範囲第1項又は第2項
に記載の映像信号処理回路。
[Claims for Utility Model Registration] A series of field signals recorded on a pair of signal tracks are continuously recorded from a signal recording medium equipped with a reference signal generator for defining the signal recording start point of concentric signal tracks. In the video signal processing circuit that reproduces the composite video signal and sends it to the subsequent circuit, the composite video signal reproduced from the signal recording medium is passed through a synchronization separation circuit 6 that separates the vertical synchronization signal included in the signal.
, 7, the reference signal obtained from the reference signal generator is connected as a trigger signal to a connected masking circuit 8, and the masking circuit 8 performs the synchronization separation for a predetermined period based on the input time of the trigger signal. A video signal processing circuit characterized in that output signals of circuits 6 and 7 are cut off to create a true vertical synchronization signal and sent to a subsequent circuit. The masking circuit 8 includes a pulse shaping circuit 17 that creates a pulse signal that becomes low level for a predetermined period when a trigger signal is input, and the output signals of the pulse shaping circuit 17 and the vertical synchronization circuits 6 and 7 are connected to each input terminal. The video signal processing circuit according to claim 1, which comprises an AND circuit 18. The video signal processing circuit according to claim 1 or 2, wherein the reference signal generator is constituted by a PG yoke 12 disposed on a magnetic disk 1 serving as a signal recording medium.
JP1986196293U 1986-12-19 1986-12-19 Video signal processing circuit Expired - Lifetime JPH0741264Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986196293U JPH0741264Y2 (en) 1986-12-19 1986-12-19 Video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986196293U JPH0741264Y2 (en) 1986-12-19 1986-12-19 Video signal processing circuit

Publications (2)

Publication Number Publication Date
JPS6399483U true JPS6399483U (en) 1988-06-28
JPH0741264Y2 JPH0741264Y2 (en) 1995-09-20

Family

ID=31154981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986196293U Expired - Lifetime JPH0741264Y2 (en) 1986-12-19 1986-12-19 Video signal processing circuit

Country Status (1)

Country Link
JP (1) JPH0741264Y2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55144623U (en) * 1979-03-31 1980-10-17
JPS55174725U (en) * 1979-05-30 1980-12-15
JPS6183389U (en) * 1984-11-02 1986-06-02
JPS61277283A (en) * 1985-05-31 1986-12-08 Tokyo Electric Co Ltd Reproducing method for television composite video signal to magnetic disc

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55144623U (en) * 1979-03-31 1980-10-17
JPS55174725U (en) * 1979-05-30 1980-12-15
JPS6183389U (en) * 1984-11-02 1986-06-02
JPS61277283A (en) * 1985-05-31 1986-12-08 Tokyo Electric Co Ltd Reproducing method for television composite video signal to magnetic disc

Also Published As

Publication number Publication date
JPH0741264Y2 (en) 1995-09-20

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