JPS6397007A - Timing generation circuit - Google Patents

Abstract

PURPOSE:To generate optional timing signals only by changing the positions of through holes by connecting a first wiring with a second wiring with the through holes which are formed one hole per one wiring of the second wirings. CONSTITUTION:The first wirings 52-57 are connected to the respective delay nodes 12-17 of a delay line 1 through buffer invertors 22-27 and moreover the second wirings 31-34 are provided in the direction of orthogonally crossing the wirings 52-57, then the inputs of logic circuits 41 and 42 are connected to them. The through holes 61-64 are provided by forming one hole per one wiring of the second wirings and the second wirings and the first wirings are connected at the through holes 61-64. With constitution like this, the connection between the delay line 1 and the logic circuits 41 and 42 for generating pulses can be changed only by altering the positions of the through holes 61-64, so that optional timing signals can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a timing generation circuit for generating necessary timing pulses within a semiconductor integrated circuit.

2. Description of the Related Art An example of a conventional timing generation circuit is shown in FIG. In the conventional timing generation circuit, a desired timing pulse is obtained by changing the transistor size of the capacitor 1 and the driver inverter 2.3 shown in FIG. It is not easy to design, change, or optimize timing in such a conventional timing generation circuit. This is because when changing the size of the transistor in the inverter, it is necessary to change the shape of the diffusion layer, which means restarting the process from the beginning. In that case, it is still necessary to perform the simulation again and check the timing.

As described above, the conventional technology has a problem in that it is not easy to design, change, or optimize timing.

Problems to be Solved by the Invention As mentioned above, in the conventional technology, there is a problem in that it is not easy to design timing, change it, or optimize it.
The present invention seeks to solve this problem.

Means for Solving the Problems The present invention provides a delay line formed in a first direction consisting of an inverter chain, and a first delay line connected to each delay node of the delay line and further wired in a second direction. a plurality of first wirings made of a wiring layer; a plurality of second wirings made of a second wiring layer formed in a direction intersecting the second direction;
It consists of a multi-input logic circuit with an input gate connected to the second wiring, and a through hole formed for each second wiring for connecting the first wiring and the second wiring. ,
This invention attempts to solve the above problems by configuring a timing generation circuit that can generate any timing signal by changing the position of the through hole.

By simply changing the position of the working through hole, the connection between the delay line and the logic circuit for pulse generation can be changed, thereby making it possible to generate any timing signal.

Embodiment An embodiment of the present invention is shown in FIG. The configuration of the embodiment shown in FIG. 1 will be explained.

First wiring lines 62 to 67 are connected to each delay node 12 to 17 of a delay line 1 consisting of an inverter chain via buffer inverters 22 to 27, and a second wiring line 31 is connected in a direction perpendicular thereto. There are ~34. (MuND game) 41 whose input is connected to these second wirings
, and a HAND gate 42. Also, the second wiring 31 to 3
4. There is one through hole 61 to 64 per hole,
Here, the second wirings 31 to 34 are connected to the first wirings.

The operation of this embodiment will be explained using FIG. 2.

Assuming that the delay time per stage of inverter used as a delay line is 1Δt, the time axis is taken as a unit. If you draw a time chart for the operation shown in Figure 1, it will look like Figure 2. Note that the delay time of m141 and NAND42 is ignored here.

In FIG. 2, V (nn) indicates the time change of the signal at the node nn, and out(A1) and out(42) mean the output signals of the ND41 and the NAND42.

As shown in FIG. 2, the embodiment of FIG. 1 requires timing signals 0ut (41) and out (42).
) is obtained.

Incidentally, the four timing patterns shown in FIG. 3 and their inverted signals are generally sufficient as the timing signals required within the memory chip.

Here, the timing pattern 1nner means that, with respect to the reference timing signal RAS, starting from the falling edge of RAS, 1nnet starts for a certain period of time, 1nnet falls, and from the rising edge of RAS, starts for a certain period of time, then 1nner rises, and , &0tiV6 hours Δtinner <ha.

Also, the timing pattern y outer is 1nne
Unlike t, Δtoutc, r>Δt.

In addition, the timing pattern head is from the falling edge of RAS, starts for a certain period of time, then falls, and then starts for a certain period of 1t.
It rises after haad and is the falling edge timing pattern of RAS. timing pattern t&workl
is the rising edge timing pattern of RAS, as opposed to head.

In the memory chip, 1nner, outer, h
ead.

tail and its reversal pattern, inf'l 6r,
outer, h6mA.

The eight tail timing patterns can cover all the necessary timing signals.

Consider AND and HAND as logic circuits that receive signals from delay lines.

Now active hi (h's input pattern is p, a
Cave -1ow's input cover turn is N1 person cover turn yi, j (i, j = P, N) AND, ) TAN
The output pattern when inputting to D is ND (ij),
Write it as HAND(ij). (Here, input cover turn 1
Suppose that changes faster than j. ) At this time, eight timing patterns are obtained from FIGS. 4 and 5.

In the embodiment shown in FIG. 1, out(41) is
PP)=inner, out(42) is NAND(N
P) = i, ail is used.

In this embodiment, the timing patterns out (41) and out (42) shown in FIG. 2 are obtained by coding the positions of the through holes as shown in FIG. By coding, any timing pattern with any delay time can be easily obtained.

Effects of the Invention According to the present invention, an arbitrary timing pattern with an arbitrary delay time can be obtained only by coding the positions of through holes. Therefore, timing can be easily designed.

In addition, changes and optimization of the timing are easy because it is only necessary to change the mask for forming through-holes. The period required for re-introducing this waste process and re-evaluating it can be shortened, and as a result, the development period for the entire integrated circuit can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a timing generation circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the circuit of this embodiment, and FIG. 3 is an explanatory diagram of the timing pattern.
Figure 4 is an explanatory diagram of a timing pattern when using a NAND logic circuit, Figure 5 is an explanatory diagram of a timing pattern when a NAND logic circuit is used, and Figure 6 is a circuit diagram of a conventional timing generation circuit. be. 1...Delay line using inverter chain,
12-17...Delay nodes of delay line, 22-2
7... Buffer inverter, 61-64.
Mountain: Through hole, 41.42...AND and NARD logic circuit. /-11 late Tamedamaei/Z-f'/-1-ji! ” Nodes 22-27--
- Batsufua no Innoku 4/, 47--Issho Shiomasa Haya 4 61-64--Through hose, Figure 1! Figure 2 Figure 3 - ΔC--m-- One hour Figure 4 σtLte Y - One hour Figure 5 One hour Figure 6

Claims (2)

[Claims] (1) A timing generation circuit comprising a delay line formed by an inverter chain and a multi-input logic circuit whose inputs are connected to delay nodes of the delay line. (2) A delay line formed in a first direction consisting of an inverter chain, and a plurality of delay lines formed in a first wiring layer connected to each delay node of the delay line and further formed in a second direction. 1 wiring, a plurality of second wirings made up of a second wiring layer formed in a direction intersecting the second direction, and a multi-input logic circuit in which an input gate is connected to the second wiring. , a timing generation circuit comprising through holes for connecting the first wiring and the second wiring, one of which is formed for each of the second wirings.