JPS6395812A - Method of detecting abnormality of load of rectifier - Google Patents
Method of detecting abnormality of load of rectifierInfo
- Publication number
- JPS6395812A JPS6395812A JP23949586A JP23949586A JPS6395812A JP S6395812 A JPS6395812 A JP S6395812A JP 23949586 A JP23949586 A JP 23949586A JP 23949586 A JP23949586 A JP 23949586A JP S6395812 A JPS6395812 A JP S6395812A
- Authority
- JP
- Japan
- Prior art keywords
- load
- rectifier
- current
- voltage
- abnormality detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005856 abnormality Effects 0.000 title claims description 62
- 238000000034 method Methods 0.000 title claims description 15
- 230000002159 abnormal effect Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 description 41
- 238000010586 diagram Methods 0.000 description 5
- 238000009713 electroplating Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 208000026817 47,XYY syndrome Diseases 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007600 charging Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000909 electrodialysis Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Protection Of Static Devices (AREA)
- Rectifiers (AREA)
- Control Of Voltage And Current In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、整流器の負荷異常検出方法に関し、特に負
荷短絡と負荷開放の両異常を検知して負荷の事故を防止
できるものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for detecting a load abnormality in a rectifier, and in particular is capable of detecting both load short-circuit and load open abnormalities to prevent load accidents.
例えば、電気分解或いは銅帯の電気めっきその他、直流
電力を利用する多くの分野で、直流電源装置として交流
電力を直流電力に変換するための整流器が、−ｉ的に広
く使われている。For example, in many fields that utilize DC power, such as electrolysis or electroplating of copper strips, rectifiers for converting AC power into DC power are widely used as DC power supplies.
第４図は、その代表例としての六相半波整流式半導体形
整流器の基本的な構成を示すものであり、過電流遮断器
１を介し入力された三相交流が、サイリスタ２を有する
開閉器Ｓ、三相交流を六相交流に変換する例えば２重Ｙ
結線された整流器用変圧器３．半波整流用ダイオード４
を経て半波整流され、例えば電気メッキであれば１００
００アンペア（Ａ）程度の直流大電流としてメッキ装置
に供給される。また、この整流器には、直流電力を供給
すべき負荷に短絡事故が発生したとき、これをいち早く
検知して事故拡大を防ぐために、負荷異常検出回路が設
けられている。すなわち、前記整流器用変圧器３の一次
側には電流検出器５が、二次側には電圧検出器６がそれ
ぞれ介挿されていて、前者で検知された電流検出信号ｓ
ｒと後者で検知された電圧検出信号ＳＶとが、演算器７
に入力される。そして、この演算器７には、更に図示し
ない負荷短絡異常検出レート設定装置で予め設定された
負荷異常検出の上限電圧Ｖａと下限電流Ｉａとが入力さ
れている。FIG. 4 shows the basic configuration of a six-phase half-wave rectifier semiconductor rectifier as a typical example. For example, a double Y that converts three-phase AC into six-phase AC
Wired rectifier transformer 3. Half-wave rectifier diode 4
For example, in the case of electroplating, 100
The plating device is supplied with a large DC current of about 0.00 amperes (A). Further, this rectifier is provided with a load abnormality detection circuit in order to promptly detect a short-circuit accident in a load to which DC power is to be supplied and prevent the accident from spreading. That is, a current detector 5 is inserted on the primary side of the rectifier transformer 3, and a voltage detector 6 is inserted on the secondary side, and the current detection signal s detected by the former is inserted.
r and the voltage detection signal SV detected by the latter, the arithmetic unit 7
is input. Further, an upper limit voltage Va and a lower limit current Ia for load abnormality detection, which are set in advance by a load short-circuit abnormality detection rate setting device (not shown), are inputted to this calculator 7.
第５図は上記整流器における負荷異常検出回路の動作特
性を示すものであり、図中、ｉｎ、Ｖｎばそれぞれ定格
電流値と定格電圧値を表し、鎖線り、は整流器運転にお
ける最低電圧−電流特性を表している。Figure 5 shows the operating characteristics of the load abnormality detection circuit in the rectifier. In the figure, in and Vn represent the rated current value and rated voltage value, respectively, and the chain line and dotted line represent the minimum voltage-current characteristics during rectifier operation. represents.
いまメッキ装置等の負荷側に短絡事故（夕（部短絡）が
発生すると、電流が急激に増大する。その結果、整流器
から出力される電圧ＳＶ、電流Ｓ１は前記の最低電圧−
電流特性の範囲をはずれて、例えばＶａボルトと言う低
い電圧でＩａアンペア以上の大電流が出力されることと
なる。そこで、負荷異常の判定条件として、負荷異常検
知の」二限電圧Ｖａと負荷異常検出の下限電流Ｉａとを
前取って設定しておき、演算器７でそれらの判定条件値
と実測された検出電圧値ＳＶおよび検出電流値Ｓ１とを
絶えず比較し、ＳＩ＞ｉａで、かつＳＶ＜Ｖａのとき負
荷異常有りど判断して、サイリスタ２に対して消弧信号
Ｇ。ＦＦを出力する。If a short circuit accident occurs on the load side of the plating equipment, etc., the current will suddenly increase.As a result, the voltage SV and current S1 output from the rectifier will be lower than the minimum voltage -
Out of the range of current characteristics, for example, a large current of Ia ampere or more is output at a low voltage of Va volts. Therefore, as load abnormality judgment conditions, the second limit voltage Va for load abnormality detection and the lower limit current Ia for load abnormality detection are set in advance, and the calculator 7 uses these judgment condition values and the actually measured detection. The voltage value SV and the detected current value S1 are constantly compared, and when SI>ia and SV<Va, it is determined that there is a load abnormality, and an extinguishing signal G is sent to the thyristor 2. Output FF.
しかしながら、どのような従来の整流器の負荷異常検出
方法にあっては、上記短絡異常時の出力電圧Ｖａの」−
限は整流器の内部短絡電圧で規制されてしまう。すると
、負荷異常検出下限電流Ｉａも、整流器運転における最
低電圧−−電流特性に従い必然的に規定される（第５図
参照）。However, in any conventional rectifier load abnormality detection method, the output voltage Va at the time of the short circuit abnormality is
The limit is regulated by the internal short-circuit voltage of the rectifier. Then, the load abnormality detection lower limit current Ia is also necessarily defined according to the minimum voltage-current characteristics in the rectifier operation (see FIG. 5).
そのため、（１）負荷電流ＳＩが、整流器内部短絡電圧
で規定される負荷異常検出下限電流Ｉａより小さい範囲
では異常が検出できない。しかも、（２）負荷電流ＳＮ
が負荷異常検出下限電流１ａより大きくなるにつれて、
異常検出の感度が鈍くなり、結局第５図に斜線で示す極
めて限られた範囲の負荷短絡しか対応できないという問
題点があった。Therefore, (1) an abnormality cannot be detected in a range where the load current SI is smaller than the load abnormality detection lower limit current Ia defined by the rectifier internal short-circuit voltage. Moreover, (2) load current SN
As becomes larger than the load abnormality detection lower limit current 1a,
There was a problem in that the sensitivity of abnormality detection became low, and in the end, it was possible to deal with load short circuits only in an extremely limited range shown by diagonal lines in FIG.
この発明は、負荷異常の検出可能範囲を従来より大幅に
拡大させるとともに、短絡異常のみならず開放異常につ
いても対応できる負荷異常検出方法を提供することをそ
の目的としている。It is an object of the present invention to provide a load abnormality detection method that greatly expands the detectable range of load abnormalities compared to the conventional method and can handle not only short-circuit abnormalities but also open abnormalities.
上記の目的を達成するこの発明は、整流器の入力電流と
出力電圧とから負荷抵抗を演算手段で演算し、その演算
結果が、予め設定された短絡上限抵抗より小さいたき、
または開放下限抵抗より大きいときに、負荷異常と判断
して前記整流器出力を零にすることを特徴とする。To achieve the above object, the present invention calculates the load resistance from the input current and output voltage of the rectifier using a calculation means, and if the calculation result is smaller than a preset short circuit upper limit resistance,
Alternatively, when the open resistance is greater than the lower limit resistance, it is determined that the load is abnormal and the output of the rectifier is set to zero.
整流器の入力電流と出力電圧とから演算手段で負荷抵抗
Ｒを演算する。一方、負荷短絡異常検出の上限電圧と定
格電流とから負荷短絡上限抵抗ＲＵを設定すると共に、
負荷開放異常検出の上限電流と定格電圧とから負荷開放
下限抵抗１１を設定する。しかして、上記各抵抗を整流
器運転中常時比較し、負荷抵抗Ｒが短絡上限抵抗Ｒｕ以
下のときは負荷短絡で所定以上の大電流が流れたと判断
し、一方、負荷抵抗Ｒが開放下限抵抗Ｒ１以上のときは
負荷開放で所定以下の電流しか流れないものと判断し、
いずれも直ちに整流器出力を零にして事故の拡大を未然
に防止する。A calculation means calculates the load resistance R from the input current and output voltage of the rectifier. On the other hand, while setting the load short circuit upper limit resistance RU from the upper limit voltage and rated current for load short circuit abnormality detection,
The load release lower limit resistance 11 is set from the upper limit current and rated voltage for load release abnormality detection. Therefore, the above-mentioned respective resistances are constantly compared during operation of the rectifier, and when the load resistance R is equal to or less than the short circuit upper limit resistance Ru, it is determined that a large current of more than a predetermined value has flowed due to a load short circuit. If the above is the case, it is determined that the load is open and only the current below the specified value flows.
In both cases, the rectifier output is immediately reduced to zero to prevent the accident from expanding.
以下、この発明の実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図は、この発明を適用する整流器の負荷異常検出回
路の一例を示すブロック図である。なお、図中、従来と
同一または相当部分には同一符号を付しである。FIG. 1 is a block diagram showing an example of a load abnormality detection circuit for a rectifier to which the present invention is applied. In addition, in the drawings, the same reference numerals are given to the same or corresponding parts as in the conventional art.
コントローラ１０は、入出力ボート、演算処理装置（Ｃ
ＰＵ） 、ＲＡＭ、ＲＯＭ等の記憶装置を具えるマイク
ロコンピュータを有し、その入力側ボートに、電流検出
器５により得られた電流検出信号Ｓｌと電圧検出器６に
より得られた電圧検出信号ＶＩとが、サイリスタ２が点
弧している間中、常時入力される。また、負荷の特性と
整流器の仕様に合わせて、図外の負荷異常検出レート設
定装置で予め設定された負荷短絡異常検出の」−限電圧
信号Ｖ、と、負荷開放異常検出の上限電流Ｔ、とが入力
される。更に、定格電圧Ｖｎと、定格電流Ｉｎと、電流
検出器５および電圧検出器６の各検出器誤差並びに演算
誤差による誤動作を防止するため設定された負荷短絡異
常検出の下限電圧ｖ０と、負荷開放異常検出の下限電流
■。とが、負荷異常検知情報として入力される。The controller 10 includes an input/output board, an arithmetic processing unit (C
It has a microcomputer equipped with a storage device such as RAM, ROM, etc., and the input side board receives the current detection signal Sl obtained by the current detector 5 and the voltage detection signal VI obtained by the voltage detector 6. is constantly input while the thyristor 2 is firing. In addition, according to the characteristics of the load and the specifications of the rectifier, the limit voltage signal V for load short-circuit abnormality detection and the upper limit current T for load open abnormality detection are set in advance by a load abnormality detection rate setting device (not shown). is input. Furthermore, the rated voltage Vn, the rated current In, the lower limit voltage v0 for load short-circuit abnormality detection set to prevent malfunctions due to each detector error and calculation error of the current detector 5 and voltage detector 6, and the load open Lower limit current for abnormality detection■. is input as load abnormality detection information.
これらの負荷異常検知情報に基づき、コントロ−ラ１０
は、負荷異常の有無を判断し、出力側ポートから論理値
“１″又は論理値“０“の制御信号を、サイリスタ２の
点弧、消弧指令信号として出力する。すなわち例えば、
異常有りと判断すればサイリスタ２に論理値“１”の消
弧信号を出力し、これにより例えばサイリスクをそのカ
ソード及びアノード間を短絡することによって消弧し、
負荷への電力の供給が遮断される。Based on this load abnormality detection information, the controller 10
determines the presence or absence of a load abnormality, and outputs a control signal with a logic value of "1" or logic value "0" from the output side port as a command signal for firing and extinguishing the thyristor 2. For example,
If it is determined that there is an abnormality, it outputs an extinguishing signal with a logic value of "1" to the thyristor 2, thereby extinguishing the thyristor by short-circuiting its cathode and anode, for example,
Power supply to the load is cut off.
以下、第１図に示す負荷異常検出装置の構成に従って行
われるこの発明の負荷異常検出方法の手順を、上記マイ
クロコンピュータの記憶装置のＲＯＭに予め記憶された
、第２図に示すプログラムに基づいて説明する。Hereinafter, the procedure of the load abnormality detection method of the present invention performed according to the configuration of the load abnormality detection device shown in FIG. 1 will be explained based on the program shown in FIG. explain.
今、コントローラ１０から論理値“０°゛の制御信号が
出力されており、従ってサイリスタ２のゲートにゲート
信号が供給されて点弧状態にあり、図外の負荷（例えば
電気メツキ装置）には、整流器を介して所定の直流電力
が供給されつつあるものとする。Now, a control signal with a logical value of "0°" is being output from the controller 10, and therefore a gate signal is supplied to the gate of the thyristor 2, which is in the ignition state, and a load (for example, an electroplating device) not shown is connected to the thyristor 2. , it is assumed that a predetermined DC power is being supplied through a rectifier.
まずステップ■で初期設定を実行し、次いでステップ■
に移行して、電流検出器５で検出された電流信号ＳＩと
、電圧検出器６で検出された電圧信号ＳＶのアナログ信
号をＡ／Ｄ変換器でデジタル信号に変換して読み込み、
ステップ■に移行する。ステップ■では、これらの検出
値に基づいて抵抗Ｒ＝ＳＶ／ＳＩを算出し、それを負荷
抵抗値として記憶装置の所定の領域に一時記憶する。First perform the initial settings in step ■, then step ■
The current signal SI detected by the current detector 5 and the analog signal of the voltage signal SV detected by the voltage detector 6 are converted into digital signals by an A/D converter and read.
Move to step ■. In step (2), resistance R=SV/SI is calculated based on these detected values, and it is temporarily stored in a predetermined area of the storage device as a load resistance value.
次にステップ■に移行して、負荷の特性と整流器仕様に
応じて定められた定格電流値Ｉｎと、この定格電流Ｉｎ
を流したときの許容最低電圧で表される負荷短絡異常検
出上限電圧■１とを読み込み（第３図参照）、これに基
づいてステップ■で抵抗Ｒｕ ＝Ｖ Ｈ／ Ｉ ｎを算
出し、その結果を負荷短絡上限抵抗値Ｒｕとして所定の
記ｔ！領域に一時記憶する。Next, move to step
Read the load short circuit abnormality detection upper limit voltage ■1, which is expressed as the minimum allowable voltage when The result is set as the load short-circuit upper limit resistance value Ru, and the predetermined notation t! Temporarily stored in the area.
次にステップ■に移行し、上記ステップ■で算出した現
負荷抵抗値Ｒとステップ■で算出した負荷短絡上限抵抗
値Ｒｕとを比較することにより、負荷の短絡異常の有無
を判断する。すなわち、負荷に短絡があれば、正常な状
態におけるより低電圧で大電流が流れる故、負荷短絡上
限抵抗値Ｒｕは小さい値を示す筈である。よって現負荷
抵抗値Ｒ＞Ｒｕならば負荷短絡無しと判断してステップ
■に移行する。一方Ｒ＜Ｒｕであれば短絡事故発生の可
能性が大きいと考えられるが、電流、電圧の検出誤差の
可能性もあり得る。そこでステップ■に移行し、検出電
流値ＳＩが負荷短絡異常検出下限電流設定値１０を上回
るか否かを判断する。Next, the process proceeds to step (2), and by comparing the current load resistance value R calculated in step (2) and the load short-circuit upper limit resistance value Ru calculated in step (2), it is determined whether or not there is a short-circuit abnormality in the load. That is, if there is a short circuit in the load, a large current flows at a lower voltage than in a normal state, so the load short circuit upper limit resistance value Ru should exhibit a small value. Therefore, if the current load resistance value R>Ru, it is determined that there is no load short circuit, and the process moves to step (2). On the other hand, if R<Ru, it is considered that there is a high possibility that a short circuit accident will occur, but there is also a possibility of a current or voltage detection error. Therefore, the process moves to step (3), and it is determined whether or not the detected current value SI exceeds the load short circuit abnormality detection lower limit current setting value 10.
その結果がＳＩ＞Ｉ。であれば上記誤差の範囲外故１、
負荷短絡異常有りと判定され、ステップ＠へ移行して、
コントローラ１０の出力ボートからサイリスタ２へ、サ
イリスク消弧信号Ｇ ＯＦＦが出力されて、その結果負
荷への電流が零になり、事故拡大が防止される。The result is SI>I. If so, the above error is outside the range 1,
It is determined that there is a load short circuit abnormality, and the process moves to step @.
The thyristor arc extinguishing signal G OFF is output from the output port of the controller 10 to the thyristor 2, and as a result, the current to the load becomes zero, preventing the accident from spreading.
すなわち、この実施例によれば、第３図の電圧−電流特
性が台形Ｉ ａ、 Ｉ ｎ、 Ｖｌ、 Ｖｏの範囲内
にあるとき短絡異常有りと判断できる。That is, according to this embodiment, when the voltage-current characteristic shown in FIG. 3 is within the range of trapezoids Ia, In, Vl, and Vo, it can be determined that there is a short circuit abnormality.
一方、ステップ■で反対にｓｒ＜ｉｏであれば、先に述
べた誤差の範囲内であるから負荷短絡異常は無いものと
判定して、ステップ■以降の負荷開放異常判定に移る。On the other hand, if sr<io in step (2), it is determined that there is no load short-circuit abnormality since it is within the error range described above, and the process moves to the load open abnormality determination in step (2) and subsequent steps.
ステップ■では、負荷の特性と整流器仕様に応じて定め
られた定格電圧値Ｖｎを読み込むと共に、負荷開放と判
断すべき限度状態でこの定格電圧Ｖｎを加えたとき流れ
得る最大電流値を、負荷開放異常検出の上限電流■１と
して読み込み（第３図参照）、これに基づいてステップ
■で抵抗Ｒ１＝Ｖ ｎ ／ Ｉ １を算出し、その結果
を負荷開放下限抵抗値Ｒ１として所定の記憶領域に一時
記憶する。In step ■, the rated voltage value Vn determined according to the characteristics of the load and the rectifier specifications is read, and the maximum current value that can flow when this rated voltage Vn is applied in the limit state that should be considered as load open is calculated. The upper limit current for abnormality detection is read as 1 (see Figure 3), and based on this, the resistance R1 = V n / I 1 is calculated in step 2, and the result is stored in a predetermined storage area as the load release lower limit resistance value R1. Memorize temporarily.
次にステップ［相］に移行し、上記ステップ■で算出し
た現負荷抵抗値Ｒとステップ■で算出した負荷開放下限
抵抗値ＲＮとを比較することにより、負荷の開放異常の
有無を判断する。すなわち、負荷に開放があれば、抵抗
値は上記負荷開放下限抵抗値ＲＩ！より大きい値を示す
筈である。よって現負荷抵抗値Ｒ＜Ｒｆならば負荷開放
無しと判断してステップ■に戻る。一方Ｒ＞Ｒｆであれ
ば負荷開放の可能性が大きいと考えられるが、検出誤差
の可能性もあり得る。そこでステップ■に移行し、検出
電圧値ＳＶが負荷開放異常検出下限電流設定値Ｖ。を上
回るか否かを判断する。その結果がＳＶ＞Ｖ、であれば
、負荷開放異常有りと判定され、ステップ＠へ移行して
、コントローラ１ｏの出力ボートからサイリスク２へ、
サイリスタ消弧信号ＧＯＦＦが出力されて、負荷への電
流が遮断される。Next, the process moves to step [phase], and the presence or absence of a load release abnormality is determined by comparing the current load resistance value R calculated in step (2) with the load release lower limit resistance value RN calculated in step (2). That is, if the load is open, the resistance value is the load open lower limit resistance value RI! It should show a larger value. Therefore, if the current load resistance value R<Rf, it is determined that the load is not released and the process returns to step (2). On the other hand, if R>Rf, it is considered that there is a high possibility of load release, but there is also a possibility of a detection error. Therefore, the process moves to step (3), where the detected voltage value SV becomes the load open abnormality detection lower limit current set value V. Determine whether or not it exceeds. If the result is SV>V, it is determined that there is a load release abnormality, and the process moves to step @, from the output port of the controller 1o to the Cyrisk 2.
The thyristor arc extinguishing signal GOFF is output, and the current to the load is cut off.
その結果、負荷開放時の電流不足によるメツキネ足など
の事故を未然に防止することができる。As a result, it is possible to prevent accidents such as a tripping due to insufficient current when the load is released.
すなわち、この実施例によれば、第３図に示す電圧−電
流特性が台形Ｖ。、Ｖｎ、Ｉ＋、ｊｏの範囲内にあると
き開放異常有りと判断できる。That is, according to this embodiment, the voltage-current characteristic shown in FIG. 3 has a trapezoidal V shape. , Vn, I+, and jo, it can be determined that there is an open abnormality.
これに対してＳ Ｖ ＜ Ｖ。ならば、上記範囲外であ
り、開放異常無しと判断されてステップ■に戻る。かく
して」二足ステップ■〜ステップ［相］を整流器の運転
中繰り返し実行することにより、負荷の短絡異常と開放
異常に起因する事故を防止する。On the other hand, S V < V. If so, it is outside the above range, and it is determined that there is no opening abnormality, and the process returns to step (2). Thus, by repeating the two-legged step (■) to step [phase] during operation of the rectifier, accidents caused by short-circuit abnormalities and open-circuit abnormalities of the load can be prevented.
この実施例によれば、電気メツキ時の負荷短絡によるト
ランス焼損等の事故のみならず、負荷開放によるメツキ
ネ足などのトラブルをも未然に防止できて、しかもそれ
らの負荷異常の検知範囲を拡げ且つ検出感度も良好に保
つことができる。According to this embodiment, it is possible to prevent not only accidents such as transformer burnout due to load short circuit during electroplating, but also troubles such as disconnection due to load release, and furthermore, the detection range of these load abnormalities can be expanded and Detection sensitivity can also be kept good.
なお、上記実施例では、負荷として電気メツキ装置に適
用する場合につき述べたが、これに限らずその他例えば
電気分解、電気透析、充電等、整流器を使用する各種の
装置に適用可能である。In the above embodiment, the case where the present invention is applied to an electroplating device as a load has been described, but the present invention is not limited to this and can be applied to various other devices using a rectifier, such as electrolysis, electrodialysis, charging, etc.
また、六相半波整流に限定されるものではなく、単相、
三相交流や全波整流等の整流器にも通用できる。In addition, it is not limited to six-phase half-wave rectification, but single-phase,
It can also be used in rectifiers such as three-phase AC and full-wave rectification.
更乙、二また、電流検出器５の設定位置については。Regarding the setting position of the current detector 5.
整流器用変圧器３の二次側であっても良い。It may be the secondary side of the rectifier transformer 3.
以−に説明したように、この発明によれば、整流器の入
力電流、出力電圧から負荷抵抗を演算手段で演算し、そ
の結果に応じて負荷異常の有無を判断して整流器出力を
制御するものとしたため、負荷異常の検出可能範囲を従
来より大幅に拡大させると共に、短絡異常のみならず開
放異常をも容易かつ確実に検出することが可能となり、
整流器における負荷異常対策の内容と範囲を著しく拡張
するという効果が得られる。As explained above, according to the present invention, the load resistance is calculated by the calculation means from the input current and output voltage of the rectifier, and the presence or absence of load abnormality is determined according to the result to control the rectifier output. As a result, the detectable range of load abnormalities has been greatly expanded compared to conventional methods, and it has become possible to easily and reliably detect not only short-circuit abnormalities but also open abnormalities.
This has the effect of significantly expanding the content and scope of countermeasures against load abnormalities in rectifiers.
第１図はこの発明を適用する装置の一例を示すブロック
図、第２図はこの発明の負荷異常検出手順を説明するフ
ローチャート、第３図はこの発明を適用する負荷異常検
出回路の動作特性図、第４図は従来の整流器の負荷異常
検出装置のブロック図、第５図は従来の負荷異常検出回
路の動作特性図である。
２はサイリスク、３は整流器用変圧器、４はダイオード
、５は電流検出器、６は電圧検出器、１０は演算手段（
マイクロコンピュータ）である。Fig. 1 is a block diagram showing an example of a device to which the present invention is applied, Fig. 2 is a flowchart explaining the load abnormality detection procedure of the invention, and Fig. 3 is an operational characteristic diagram of a load abnormality detection circuit to which the invention is applied. , FIG. 4 is a block diagram of a conventional load abnormality detection device for a rectifier, and FIG. 5 is an operational characteristic diagram of a conventional load abnormality detection circuit. 2 is a Sirisk, 3 is a rectifier transformer, 4 is a diode, 5 is a current detector, 6 is a voltage detector, 10 is a calculation means (
microcomputer).
Claims (1)
で演算し、その演算結果が、予め設定された短絡上限抵
抗より小さいとき、または開放下限抵抗より大きいとき
に、負荷異常と判断して前記整流器出力を零にすること
を特徴とする整流器の負荷異常検出方法。A calculation means calculates the load resistance from the input current and output voltage of the rectifier, and when the calculation result is smaller than the preset short circuit upper limit resistance or larger than the open lower limit resistance, it is determined that the load is abnormal and the above-mentioned A method for detecting a load abnormality in a rectifier, characterized by reducing the rectifier output to zero.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61239495A JPH0732534B2 (en) | 1986-10-08 | 1986-10-08 | Rectifier load abnormality detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61239495A JPH0732534B2 (en) | 1986-10-08 | 1986-10-08 | Rectifier load abnormality detection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6395812A true JPS6395812A (en) | 1988-04-26 |
| JPH0732534B2 JPH0732534B2 (en) | 1995-04-10 |
Family
ID=17045629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61239495A Expired - Lifetime JPH0732534B2 (en) | 1986-10-08 | 1986-10-08 | Rectifier load abnormality detection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732534B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0237532U (en) * | 1988-08-30 | 1990-03-13 | ||
| JP2012130210A (en) * | 2010-12-17 | 2012-07-05 | Toshiba Mitsubishi-Electric Industrial System Corp | Electric power conversion apparatus |
| KR20220105584A (en) | 2021-01-20 | 2022-07-27 | 가부시키가이샤 에바라 세이사꾸쇼 | Short circuit detection method in plating apparatus, control method of plating apparatus, and plating apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58154322A (en) * | 1982-03-08 | 1983-09-13 | 三菱電機株式会社 | Shortcircuit detector |
-
1986
- 1986-10-08 JP JP61239495A patent/JPH0732534B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58154322A (en) * | 1982-03-08 | 1983-09-13 | 三菱電機株式会社 | Shortcircuit detector |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0237532U (en) * | 1988-08-30 | 1990-03-13 | ||
| JP2012130210A (en) * | 2010-12-17 | 2012-07-05 | Toshiba Mitsubishi-Electric Industrial System Corp | Electric power conversion apparatus |
| KR20220105584A (en) | 2021-01-20 | 2022-07-27 | 가부시키가이샤 에바라 세이사꾸쇼 | Short circuit detection method in plating apparatus, control method of plating apparatus, and plating apparatus |
| US11866842B2 (en) | 2021-01-20 | 2024-01-09 | Ebara Corporation | Short circuit detection method in plating apparatus, control method of plating apparatus, and plating apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0732534B2 (en) | 1995-04-10 |
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