JPS6395788A - Video signal reproducing device - Google Patents

Abstract

PURPOSE:To obtain a still picture reproduction without fluctuation by operating a reference value and a correcting value, obtaining first and second arithmetic results and outputting a variable delaying signal to delay a head changing-over signal by the first or second arithmetic result. CONSTITUTION:In a variable delaying circuit 5 to delay a head changing-over signal (a) for a prescribed time and output a variable delaying signal (c), the device has a reference value generating circuit 51 to output 6.5-fold time (f) of a horizontal scanning period as a reference value in a VHS system, a correcting value generating circuit 52 to output, as the correcting value, a time (i) equivalent between a head X2 for a standard mode and a head Y1 for a long time mode and between a head Y2 for a long time mode and a head X1 for a standard mode and a delaying time control device 53 to control the correcting value in the correcting value generating circuit 52 by adjustment. The reference value and the correcting value are operated, the first and second arithmetic results are obtained, and a variable delaying signal to delay a head changing-over signal is outputted by the first or second arithmetic result. Thus, the delaying quantity of the variable delaying signal can be easily set and the still picture vertical synchronizing adjustment can be executed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a video signal reproducing device that adjusts the phase of an image signal and a vertical synchronization signal, especially when reproducing still images, to achieve good quality without vertical blur. The present invention relates to a video tape recorder that can obtain still images.

[Conventional technology]

2. Description of the Related Art Conventionally, as a video tape recorder for reproducing still images, the one shown in Fig. 3 is known.

Figure 3 is a diagram showing a conventional still picture vertical synchronization adjustment device in a video tape recorder.
A head drum m is provided to be rotatable about the distance u through which the magnetic tape (1a) runs, and rotates in the direction R shown in the figure during recording or reproduction;
° Mounted opposite to each other, video signals are transferred to magnetic tape (LA).
) For example, in the VH8 system, one head X1 is set at +6 degrees. , the other head X2 has an azimuth angle of 16 degrees. Y, ,
Y2 is attached to the head (1) facing 1800 degrees, and records video signals on the magnetic tape (1a) or reproduces them when the speed of the magnetic tape (1a) is 1/2 or 1/3 of the target speed. For example, in the VH8 system, one head Y1 is tilted so that it has an azimuth angle of +6 degrees, and the other head Y has an azimuth angle of 16 degrees. When still images and playback are performed, the azimuth angles are made to be the same, and in the standard mode, one of the standard mode heads X and the long time mode head Y1 are used. , long time mode
Here, this is carried out using the other standard mode head and long time mode head Y2. αQ is the primary winding unit (10a) on the head drum (11 side) into which the video signals reproduced by the heads x, , y, , y2 are input, and the secondary winding m (
10b), a rotary transformer consisting of a]), aa,
(to) and α slope are the secondary winding IA of the rotary transformer, respectively.
A video signal amplifier that is connected to the LC and amplifies the video signal (
g) is a head switching device into which the amplified video signals from these video signal amplifiers are input.

(2) is a drum motor that rotationally controls the above-mentioned drum head +1), (3) is a head switching signal generating element directly connected to this tram motor (2), and z, , ' z2 is a drum motor that controls the rotation of the above-mentioned drum motor (2). (180 degrees in the case shown) of each head switching signal detection head, (4
) are used to detect these head switching signals 2. , 22, the head switching signal generating circuit outputs the head switching signal a shown in FIG. Video signal amplifier C11)-
Selectively output the video signal from 〇4. σ6 amplifies the reproduced video signal υ output from the head switcher (a) above.

A reproduction signal processing circuit that performs signal processing such as detection and frequency conversion, qη is a pseudo vertical synchronization signal addition circuit that outputs the processed video signal from the processing circuit aG as a reproduction video signal at the output end, The above head switching signal generation times vf
A fixed delay circuit that delays the head switching signal a of i4>no) by a predetermined time and outputs the fixed delay signal shown in @4 Figure fbl, (9) is the head switching signal from the head switching signal generation circuit (4). By delaying the signal a for a predetermined period of time (Fig. 4 fc)
A variable delay circuit that outputs a variable delay signal C shown in FIG. (93) A first delay circuit (
91), a second delay time control device (94) for controlling the variable delay signal in the long time mode, and a second delay time control device (94) for the forward switching signal a%C. ul control signal (delayed by a predetermined time from this to generate a second variable delay signal c)
2 and a second delay circuit (92), which receives the first and second variable delay signals from these fXl and the second delay circuits (91) and (92), and a mode discriminator ([ 81y) and a selector switch (90) which selects and outputs the first and second 0T variable delay signals in response to the standard/long-time mode discrimination signal to form the variable delay signal C. It is. (1) is the above fixed delay circuit (
6), the variable delay signal from the variable delay circuit (9), and the head switching signal a from the head switching signal generating circuit (4) shown in FIG. This is a changeover switch that outputs a pseudo signal d shown in FIG.
A switch is used to output a fixed delay signal when the signal C is 'L level. (8) is obtained by differentiating and inverting the pseudo No. 13 d from this changeover switch (7).
e) The pseudo vertical synchronization signal e5 shown in 1 is generated, and upon receiving the still image mode signal from the still image playback command switch nii, 2 this pseudo vertical synchronization signal e is sent to the above four pseudo vertical rules 4
This is a pseudo-vertical signal addition circuit qηi for adding a video signal to the signal addition circuit qηi.

The playback operation of the video chip recorder constructed in this manner will be explained below. First, in the standard mode iC, the video No. 15 played back by the rotor 'J) Lance α1. amplifier uD,
03 and the playback signal processing circuit 0 via the head switch aυ
61 inputs, signal processing 8 and 21. The reproduced video signal is outputted to the output terminal (I) 11 via the pseudo vertical equal amount signal addition circuit Oη. 'f, ta. In the long-time mode, the head Y, Y2) regenerated rLr, - video signal is input to the regenerated 4J processing circuit QO via the rotor 1J) lance signal, amplifier 0, α4 and head 9J converter α0. , the signal is processed and a reproduced video signal is outputted to the output 4 via the pseudo hand 16 dosuke 13 additional circuit αη.

In these target i11 mode and long time mode +C.

Since the 011-image mode signal of the still image playback command switch tllJ is not output, the pseudo vertical 1 signal addition circuit αη has the pseudo vertical 1+'f4 light signal generation 4 signal (8
) and) etc. are given to the pseudo silkworms 11 and 1 e, and the output end (181j moss pseudo 6 +u) outputs a reproduced image signal to which the assistance signal e is not added.

91. Still image playback mode 1 will be explained below. First, if the magnetic tape (1aH) is recorded in standard mode,
Then, the video signals reproduced by the heads x, , y are transferred to the rotary transformer α1. Video signal amplifier 0υ.

(141 and the head switching device ([9) is input to the reproduction No. 14 processing circuit a0, subjected to signal processing, and inputted to the pseudo-synchronization signal addition circuit αη. The head switching signal fat from !8+4> is sent to the fixed delay circuit (6) and the first and second delay circuits (91).
. (92) Each G iron is delayed. Since the standard mode discrimination signal is output from the mode discrimination device, the selector switch (90) is set to the first delay 1! ,! J Road (91)
The first iq variable delay signal from the output terminal is outputted from the selector switch (1) as the ljj variable delay signal C. Changeover switch (7) that receives fixed delay signal S and town change delay signal C
The analogous signal d is simulated by the analogous image 1a, the same 1υ1, the signal generator circuit (8)
Added to the still image Paleozoic Command Sinch f111p> etc. i (
? The pseudo vertical IK same gate signal generation circuit (8) which receives the stop mode signal gives the pseudo vertical 1υ1 signal e to the pseudo vertical IK 101 signal additional times (1'8σ).The reproduced signal processing circuit u
A pseudo vertical synchronization signal e is added to the video signal by a pseudo vertical synchronization signal e. hand.

Output terminal q (outputs C as a 4E video signal, also.

Magnetic tape (LA) Recorded at jc time t-de
When there is a message saying, ``Hey, play it on head X2, Y217m.''
The video signal is rotated by the rotary receiver QO, and the video signal amplifier is connected to the rotary receiver QO.

The signals are input to the reproduced signal processing circuit (1! 1c) by turning on the θ1 and -.Sept.

On the other hand, \ Sodo switching G, F original generation circuit (4) small Ghent off (4 signal a is fixed slow Q + E circuit 113), and second delay circuit (Sl), (Q2) ζ Each trowel is delayed. The mode discrimination device 0E17')) outputs a long-time mode discrimination signal.
0) is ・■2υ) from the lπ2 delay circuit (92) 6
The changeover delay A1 is outputted to the changeover switch (7) as the changeover delay (+) E signal c, and the changeover switch (7) receives the constant exposure signal and the variable delay signal c5. gives the pseudo signal d to the pseudo vertical synchronization signal generation circuit (8), and outputs the iil stop ryosenryo mode signal from the static ulj l'f raw command switch to the main circuit (8).
) is the pseudo interval (υJ1.
n> et σ, the pseudo vertical synchronization signal size addition circuit Qη receives the video signal processed by No. 1 and the pseudo vertical synchronization signal e, and the video signal In addition, four output signals are output as playback video signals.

By the way, one long time 1117-mode head Y1 is one standard mode head X, 18077: opposite t~
The position γ is 1, which is slightly ahead of the other standard mode head X2 in the direction of travel E.
180 degrees opposite to each other, that is, one long-time mode head Y is located behind the position 1 in the direction of travel.

In other words, in the still image playback mode, in order to play back the video signal recorded in the standard mode (when using the head The interval between the standard mode head and the long-time mode head η is less than the image signal reproduced by the head for the standard mode and the long-time mode head η. If Y2 is used to reproduce the signal, the image signal reproduced by the standard mode head There is a large amount of delay in head switching by a time corresponding to the interval of the semi-mode head The delay time of the 1α and 1υJ signals from the head switching signal a needs to be smaller than the delay time of the standard mode head X by the time corresponding to the interval between the standard mode head X2 and the long time mode head Y. Yes. For still image playback in long mode, the standard mode hand
2. When there is a delay from switching the screen synchronization signal to the image signal reproduced by 2, the delay time between the long-time mode head Y1 and the standard mode head X2 is longer than the delay time caused by the long-time mode head Y2. It is necessary to reduce the interval E by a corresponding amount of time.

In the video tape recorder shown above.

This adjustment is made by adjusting the first delay time control device (93) for still image playback in standard mode, and by adjusting the second delay time control device (') 4) for still image playback in long time mode. The above-mentioned necessary differences are provided for each mode switch, and the switching switch (
9Q) to select the optimal delay time adjusted for each mode. Specifically, when a video tape recorder user connects a television receiver to play still images, a delay time control device ('13) is used to prevent the played still images from vibrating in the vertical direction of the screen. 9
This is done by adjusting 4).

[Problem that the invention seeks to solve]

However, in the video tape recorder constructed in this way, the first and second
The delay amounts of the delay circuits (91) and (92) must be set separately according to the receiving television, and two delay time control devices (93) and (94) are required.
The problem is that the device is complicated and difficult to handle.

This invention has been made in view of the above-mentioned points, and includes still image playback and a2
It is an object of the present invention to provide a video tape recorder that can perform still picture vertical synchronization adjustment using a single delay time control device regardless of the still picture playback mode, for example, a long time mode.

[Means for solving problems]

This invention - this video signal reproducing device has a pair of heads for a first mode and a pair of heads for a second mode, and the video signals from these heads for the first and second modes are reproduced by a head switching signal. When output as a signal, ζ
This method generates a pseudo vertical synchronization signal based on the fixed delay signal and variable delay signal of the identification delay means, adds this pseudo vertical synchronization signal to the video signal during still image playback mode, and outputs it as a playback video signal. 2, using the variable delay means to obtain first and second calculation results using the reference value and the correction value;
The first or second selected based on the mode discrimination signal.
A variable delay signal obtained by delaying the head switching signal is output based on the calculation result.

[Effect]

The 6 variable delay means in this invention calculates the reference value and the correction value, obtains @l and the second calculation result, and delays the head switching signal according to the first or second calculation result. Since the signal is output, the delay amount of the variable delay signal can be easily set.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on FIG. 1. The device of this embodiment delays the head switching signal a by a predetermined time compared to the conventional device shown in Fig. @3, and the DI conversion delay f
It is characterized by a variable delay circuit (5) that outputs J No. C. In Figure 1, (51) ij
The time from the head switching force (normal head switching force) to the vertical synchronization signal at the time of re-maining, that is, 6 of the C horizontal scanning period in the VH8 system.
．． Reference value generation circuit that outputs 5 times the time f8 reference value, (!') 2) is between the standard mode head X2 and the time mode head η, and the long time mode head Y and C□1
A correction value generating circuit which outputs the time i corresponding to the interval between the quasi-mode heads X1 as a correction value f.

(53) is a zero delay time control device that controls the correction value in this correction value generation circuit according to the adjustment; (54) is the reference value f of the reference value generation circuit (51)) and the correction value generation circuit ( 52) Input the correction value i from the above, subtract the correction value i from the reference value f, and output the subtraction result t'0j2.4
The circuit (55) inputs the reference value f from the reference value generation circuit (51) and the correction value i from the correction generation circuit (52), and adds the correction value 1 to the base value f#. The addition circuit (56) outputs the result, and the subtraction circuit (54)
) J1 result t and the addition result t from the adder circuit (55) are input, and 1 from the mode discriminator f181 is input.
This is a selector switch that selects and outputs the separate signal l, Koyotero, Bojun Seika, and the addition result.When the discrimination signal indicates the standard mode, the subtraction result? , outputs the addition result when indicating the long-term mode. (57) is the changeover switch (
56) minus 1′! $result t, itching result ri memorized,
This (preset memory that outputs L et al. results, (Fi8
) receives the head switching signal a from the head switching signal generation circuit (4) and the output from the preset memory (57), and presets the delay amount of the head switching signal a. J
(57) 1) A delay counter that is set by the output of z and outputs a variable delay signal C.
Is the output from (57) the castle 4 result? Then, the first variable delay signal shown in Fig. 2 (cl) l is output as the = J variable delay signal C, and the variable delay signal of river 2 shown in Fig. 2 (C2) is the addition result. This outputs the following.

This variable delay circuit C1+5) takes advantage of the following features in 1). In other words, three pairs of heads in the same mode during normal operation on the drum each weigh 180g at position i'
4- The lengths between the standard mode head X1 and the long-time+ifl mode head Y2 and the long-time mode head Y2 are the same.

On the other hand, when s r'iP and Ll-i surface +1 are born, it is in i1 semi-mode and for standard mode -\nodoXI tok 1l-i li
'Since the first seventh-order head Y is used, the video signal reproduced from the long-time mode head Y is higher than the video signal reproduced from the standard-mode head Xl. The delay from head switching is less by 1 - 1 time in the henode Yl(1) interval for long time mode, while in long time mode, the delay from head switching is 4% + iJj mode head Y2 scant 1 vote for semi-mode Since the hand X2 is used, the video signal played by the standard mode hand X2 is
jThe delay from the switching of the head to the time f corresponding to the interval between the head Y for the 4-hour mode and the head Y for the standard mode than the video signal reproduced from the head Y2 for the Q mode.
There are many. Therefore, the time 1111 corresponding to the distance between the head and the hen in both modes is not the same."IQ
-1'jt-tei mode, 3rd still image playback, No. 13 is played from tijl mode henodo Y, +: A'A mode henodo Since the amount of extension from head switching is smaller, the signal is reproduced from the standard mode head X2, so that the long time mode head Y
This means that the amount of delay caused by the head switching force is greater than the signal to be reproduced.

Next, the playback operation of the video tape recorder configured as described above will be explained. Since still picture mode signals such as f3 mode and long time mode (still picture playback command switch 09 in this case) are not output, a pseudo vertical opening signal is generated in the pseudo vertical synchronization signal addition circuit qη. circuit(
Similarly to the conventional device shown in FIG. A dog-like signal is output.

Reproducing still images in standard mode 8 In 'L mode, one video signal reproduced by head The signal is input to the signal processing circuit QO.

The signal is processed and input to the pseudo vertical synchronization addition circuit aηl. On the other hand, the head switching signal a from the head switching signal generation circuit (4) is sent to the fixed delay circuit (6) and the delay counter (
58) respectively. mode discriminator (four powers)
This is because they output a standard mode discrimination signal.

The cut-back switch (56) outputs the subtraction result t from the subtraction circuit (54) and provides it to the preset memory (57). The subtraction result t from the preset memory (57) is given to the delay counter (58), and the fourth delay counter (58) delays the head switching signal a by the delay amount based on the subtraction result t. The town variable delay Kaya signal C shown in FIG. 2 (cl) is output. The changeover switch (7) which receives the fixed delay signal S and the variable delay signal C outputs the pseudo signal shown in FIG. The pseudo vertical direction rV) signal generation circuit (8) which receives the still image mode signals from fJ> and others is shown in FIG.
), the pseudo picture 1B signal e shown in f is applied to the pseudo vertical synchronizing signal adding circuit aη. The pseudo first synchronization signal addition circuit αη receives the signal-processed video signal of the reproduction signal processing circuit Q, 7n, etc. and the pseudo vertical first synchronization signal e, and outputs the pseudo first synchronization signal adding circuit αη adds the pseudo first synchronization signal e8 to the video signal. End port (This is output as a video signal. Also, in the still image playback mode in the long time mode, the video signal played back by the head
The reproduced signal processing circuit Q is input through the head switch αG and the head switch αG, and the signal is processed and sent to the pseudo vertical synchronization addition circuit a7.
) i is input. On the other hand, the head switching signal generation circuit (4
) is delayed by a fixed delay circuit (6) and a delay counter (58) f, respectively. Since the mode discriminating device ω has not yet outputted the mode discriminating signal for a long time, the changeover switch (56) outputs the addition result from the adding circuit (55) and supplies it to the preset memory (57). From the preset memo IJ (57), the addition result is given to the delay counter (58) fC, and the delay color/re (
58), a variable delay signal C shown in FIG. The received changeover switch (7) supplies the pseudo signal d shown in FIG. 2(d) to the pseudo vertical synchronization signal generation circuit (8),
The pseudo vertical synchronization signal generation circuit (8) that receives the still image mode signal from the still image reproduction command switch concave is shown in Figure 2 (e2).
A pseudo vertical synchronizing signal e shown in FIG. 1 is applied to a pseudo vertical synchronizing signal adding circuit α. The pseudo vertical synchronization signal adding circuit α7) which receives the 1g processed video signal from the reproduction signal processing circuit αO and the pseudo vertical synchronization signal addition circuit α7) which receives the 1g processed video signal and the pseudo vertical synchronization signal addition circuit α7) adds a pseudo vertical 1d signal to the video signal.
The same signal e8 is added to the output terminal U# and outputted as a reproduced video signal.

2 to the video tape recorder that has been set up as described above.
In this case, a variable delay signal for the still image playback mode in the standard mode and a variable delay signal for the still image playback mode in the long time mode are generated based on the reference value and one correction value. All you have to do is set the value and it becomes very easy to use.

In addition, in the embodiment L, the variable delay circuit [5] is
Reference value generation port path (51), correction value generation surface u4 (52)
.

Delay opening control device (53), ) II11 arithmetic circuit (5
4), H-1 circuit (55), selector switch (5fi)
, preset memory (57) and delay counter (58)
), but in this, 1;
γ of a number from base $1 direct, correction value and fC
It may be any means that outputs a variable delay signal according to the calculation result selected based on the result of the stolen data, and may be configured by a microcomputer, etc., for example. be.

〔Effect of the invention〕

As described above, this invention includes the delay means,
The reference value and the correction value are calculated to obtain the first and second calculation results, and a variable delay signal in which the hennode switching signal is delayed by Wt or the second calculation result is output.
This has the advantage that the delay amount of the variable delay signal can be easily set, and still image playback without jerkiness can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a schematic configuration diagram showing a video tape recorder which is an embodiment of the present invention, Fig. 2 is an output waveform diagram for each part of Fig. 1, and Fig. 3 is a schematic configuration diagram showing a conventional video tape recorder. Figure @4 is an output waveform diagram at each part in Figure 2. 3 in the figure, x,, X2. Y, , Y2 head, (1) Head drum, +51 is variable delay circuit,
(51) is a base value generator circuit, (52) is an f correction 4rt generation circuit, and (54) is a σ kumi calculation circuit. (55) is the addition path, (!'i6) is the switching switch, (57) is the pre-seven node memory, (58)≦;J:
NN delay counter, (6) is a fixed delay circuit, (7) if
OFF 1:8 switch, (8) is a pseudo vertical synchronization signal generation circuit, (17+ is a pseudo vertical synchronization signal addition circuit. show.

Claims (2)

[Claims] (1) A pair of first mode heads disposed opposite to the head drum, a pair of second mode heads disposed opposite to the head drum, and video signals from these first and second mode heads. , head switching means for outputting based on a head switching signal; playback signal processing means for performing predetermined signal processing on the video signal from the head switching means; and fixed means for delaying the head switching signal by a predetermined time and outputting a fixed delay signal. The first and second calculation results are obtained by the delay means, the reference value and the correction value, and the first calculation result is selected based on the mode discrimination signal.
Alternatively, according to the second calculation result, a variable delay means for delaying the head switching signal and outputting a variable delay signal, receiving a fixed delay signal from the identification delay means and a variable delay signal from the variable delay means, generate a synchronization signal,
Pseudo vertical synchronizing signal generating means outputs a pseudo vertical synchronizing signal upon receiving a still picture mode signal, and adding a pseudo vertical synchronizing signal from the pseudo vertical synchronizing signal generating means to the video signal from the reproduction signal processing means and outputting the resultant signal. A video signal reproducing device equipped with pseudo vertical synchronization signal adding means. (2) The variable delay means includes a reference value generation means for outputting a reference value, a correction value generation means for outputting a correction value, and a correction value from the correction value generation means is subtracted from the reference value from the reference value generation means. subtracting means for outputting a first operation result using the reference value generating means; addition means for adding the correction value from the correction value generation means to the reference value from the reference value generation means and outputting a second operation result; switching means for selectively outputting the first calculation result and the second calculation result from the addition means based on a mode discrimination signal;
A preset memory into which the calculation result selected and output from the switching means is input, and a variable delay signal that receives the head switching signal and the calculation result input to the preset memory, and delays the head switching signal based on the calculation result. 2. The video signal reproducing apparatus according to claim 1, further comprising a delay counter that outputs a delay counter.