JPS639424B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing method for improving the recording reproducibility of facsimile image signals.

In a facsimile, a photoelectric conversion operation is performed on the original to be transmitted in the main scanning direction on the transmitter side, and the original is decomposed into pixel signals on each scanning line and then transmitted as serial image signals according to the scanning order. On the receiver side, recording scanning is performed to record dot-shaped pixels that correspond to the scanning on the transmitter side based on the received image signal, thereby obtaining a received image that corresponds to the transmitted original. ing.

However, when scanning is mainly performed on the transmitter side, it may be difficult to distinguish between black and white due to the photoelectric conversion process for objects with high spatial frequency components, such as thin lines on the original, and when this is used as a received image, black thin lines may be difficult to distinguish. It has the drawback that what is supposed to be there is often missing, resulting in the so-called "missing reading" phenomenon.

The present invention has an object of fundamentally solving such drawbacks of the conventional art, and provides first and second discrimination levels for facsimile image signals, and white signals exceeding the first discrimination level and black signals below the second discrimination level. image signal extraction means for sequentially extracting from the image signal signals corresponding to three gradations of a signal and a halftone signal between a first discrimination level and a second discrimination level; and three signals extracted from the image signal extraction means. storage means for temporarily storing a signal corresponding to a gradation as the immediately preceding image signal, whether it is a black signal, a white signal and a halftone signal; When the halftone signal is taken out, it is determined whether the image signal immediately before the taken out halftone signal is a black signal or a white signal according to the storage contents of the storage means, and the halftone signal is continuous. a discriminating means for maintaining this discriminating state for a period of time; a means for generating a repetitive signal of a black signal and a white signal for each pixel; and a repetitive signal of a white signal and a black signal for each pixel; Based on this, when the immediately preceding image signal is a black signal, a repetitive signal of the white signal and black signal is sent instead while the halftone signal from the image signal extraction means continues, and the immediately preceding image signal is means for transmitting a repetitive signal of the black signal and the white signal while the halftone signal from the picture signal extracting means is continuous when the white signal is received; An image signal that extremely effectively prevents thin line omissions on a received image, comprising means for combining and transmitting a repetitive signal and a white signal and a black signal from the image signal extraction means at the same timing. It provides a processing method.

Below, Figures 1 and 1 show circuit diagrams of the embodiment.
Figures 2 and 3 show waveforms at each part of the figure.
The details of the present invention will be explained with reference to the time chart shown in the figure.

In Figure 1, the clock pulse for reset
CPr and _the clock pulse CPs for sampling are given as those _shown in FIG.
The other D-type flip-flop circuits FF ₃ to FF ₅ and FF ₇ are controlled in output generation by the clock pulse CPs.

The image signal in FIG. 2 and 3 applied to the input IN is synchronized with the clock pulse CPr, and as shown in the figure, the upper reference line is the black level B, and the lower reference line is the white level W. The highest value of the image signal 3 applied to the input IN is held in the white level direction in the peak value hold circuit PH, and is applied to the inverting inputs of the comparators CM ₁ and CM ₂ . Peak value hold circuit PH
The output of is given to the potentiometers RV ₁ and RV ₂ , the voltage of the second discrimination level L ₁ for the image signal 3 is taken out from the potentiometer RV 1, and the voltage of the second discrimination level L ₁ for the image signal 3 is taken out from the potentiometer RV ₂ . level
The voltage of L ₂ is taken out and the comparator CM ₁ , respectively
Applied to the non-inverting input as the reference voltage for CM ₂ .

Therefore, output 4 of comparator CM ₁ is image signal 3
This occurs only when the level of CM exceeds the first discrimination level L ₁ , and the output 5 of the comparator CM ₂ similarly occurs only when the level exceeds the second discrimination level L ₂ .
A signal that produces output 4 is judged as a white signal, a signal that produces only output 5 but does not produce output 4 is judged as a halftone signal, and a signal that does not produce output 5 is judged as a black signal because it is below the second discrimination level. become. Note that although no particular output is generated as a black signal, it can be considered a black signal when neither output 4 nor 5 is generated, and by the above method and the operation of AND gate _G1 described later, white, black, and intermediate signals are generated. Signals corresponding to the three gradations are sequentially extracted from the image signal 3.

Since outputs 4 and 5 have narrow pulse widths, in order to make them predetermined, flip-flop circuits FF ₁ and FF ₂ are set respectively using both outputs 4 and 5, and outputs 6 and 7 are generated. 6 and 7 are reset by the falling edge of the first clock pulse CPr after the output occurs.

Outputs 6 and 7 are D-type flip-flop circuits FF ₃ ,
These outputs 8, 9, and 15 occur only when _the rising edge of clock pulse CPs coincides with inputs 6 and 7;
7 and the rising edge of the clock pulse CPs coincide with each other. Therefore, the flip-flop circuit FF ₁ ,
From outputs 6 and 7 of FF ₂ , the clock pulse CPr and
The outputs 8, 9, and 15 of the D-type flip-flop circuits FF ₃ and FF ₄ are generated with a delay of the rise time difference t ₁ from CPs, and while the outputs 6 and 7 are continuously generated, the outputs 8, 9 are continuously generated. , 15 are generated, and as well as sampling and holding signals corresponding to three gradations, the image signal immediately before the halftone signal is used for temporary storage for the purpose of determining whether it is white or black. Preparations are being made.

The above-mentioned components constitute an image signal extraction means that sequentially extracts signals corresponding to three gradations from an image signal. That is, D type flip-flop FF3
The non-inverted output 15 of the AND gate G1 is a white signal, the output 10 of the AND gate G1 is a halftone signal, and when both signals are present, it is a black signal.

Inverted output 8 of D-type flip-flop circuit _FF3
The non-inverted output 9 of the D-type full-flop circuit FF ₄ is applied to an AND gate G ₁ , and a halftone signal is taken out as its output 10 . That is, the second
Extraction of the conditions that caused only 5 in the figure is performed.

On the other hand, the non-inverted output 9 of the D-type flip-flop circuit _FF4 is also given to the input of the D-type flip-flop circuit _FF5 , and an inverted clock pulse 11 is obtained by inverting the clock pulse CPs by the inverter IV.
The non-inverted output 12 is produced when the rising edge of the clock pulse 11 coincides with the rising edge of the inverted clock pulse 11, and this state is maintained until the reset state of the output 9 coincides with the rising edge of the inverted clock pulse 11. Therefore, this output 12 is further delayed with respect to the output 5 of the comparator _CM2 , so that the output 5 is temporarily stored as the immediately previous image signal.

The output 12 of the D-type flip-flop circuit FF ₅ described above is given as an input to the D-type flip-flop circuit FF ₆ , and the output 10 of the AND gate G ₁ is given as an input.
is given as a clock pulse, and input 1
The coincidence of the rising edges of output 10 and output 10 as a clock pulse produces a non-inverted output 13 and an inverted output 14, and the reset state of input 12 and the coincidence of the rising edges of output 10 reset both outputs 13 and 14.
In other words, the input 12 temporarily stores the output 5 taken out as a signal of halftone or higher in the comparator CM ₂ , and both outputs 1 based on this are stored.
3 and 14 have a time relationship in which the output 5 is further delayed, and when the theoretical value of the non-inverted output 13 changes from "0" to "1" at the same time, it represents a white signal, and the inverted output 1
4 changes from “0” to “1” represents a black signal, and these are the image signals immediately before the halftone signal indicated by the output 10 of AND gate _G1 , and the image signal immediately before is the white signal. In this case, instead of the subsequent halftone signal, a black and white repetition signal is sent for each pixel, so
AND gate G ₄ performs a logical product with the output from the repetitive signal generating means described later, or when the previous image signal is black, sends out a black and white repetitive signal for each pixel instead of the subsequent halftone signal. For,
By ANDing the signal with the output from a similar repetitive signal generating means using the AND gate _G5 , a repetitive signal can be obtained in place of the halftone signal.

As described above, the D-type flip-flop circuit FF6
constitutes a determining means, and this means determines whether the image signal immediately before the halftone signal is a white signal or a black signal, according to the contents stored in the flip-flop circuit _FF5 .
At the same time, a black-and-white or black-and-white repetitive signal corresponding to the image signal immediately before the halftone signal extracted based on this judgment is sent out from the AND gate _G4 or _G5 .

On the other hand, the non-inverted output 15 of the D-type flip-flop circuit FF ₃ is the delayed output 4 of the comparator CM ₁ which is determined to be a white signal and taken out, and is sent in place of this and the aforementioned halftone signal. Since the repetition signal is the same as the order of the image signal 3 applied to the input IN, if the output 15 is sent to the output OT via the OR gate G7 together with the output ₂₁ of the OR gate _G6 , which will be described later, the intermediate tone will be An image signal is obtained by combining a signal instead of a signal and a white signal at the same timing.
Note that the output 15 is a white signal when it is "1" and a black signal or a halftone signal when it is "0", and the output 15 becomes a signal that is synthesized with the output 21 by the synthesis of the OR gate _G7 .

Next, a description will be given of means for generating a repetitive signal instead of a halftone signal. Due to space constraints, the time chart is based on the D-type flip-flop circuit _FF3.
Output 15 of , outputs 13, 14 of similar flip-flop circuit FF ₆ , input 1 of AND gates G ₂ , G ₃
0, 9, and the clock pulse input points of the D-type flip-flop circuit _FF7 are separated in FIG. The time axis has been compressed. However, important waveforms based on the image signal of FIG. 3 are shown overlappingly with FIG. 2.

As mentioned above, the halftone signal 10 taken out from the AND gate _G1 is applied to the input of the D-type flip-flop circuit _FF7 via one input of the AND gate _G2 , and is applied to the other input of the AND gate _G2 . The inverted output of the D-type flip-flop circuit _FF7 is fed back. Therefore, as shown in FIG. 3, the halftone signal corresponds to one pixel, that is, the clock pulse CPs.
When one period ts of , the output 16 of AND gate _G2
As a result, the same waveform as the output 10 of AND gate _G1 is obtained. However, when the halftone signal spans several pixels, that is, several periods of the clock pulse CPs, the inverted output of the D-type flip-flop circuit _FF7 changes every time the clock pulse CPs rises.
Output 16 of AND gate _G2 is clock pulse CPs
From “1” to “0” or “0” every cycle of
is inverted to "1", and this becomes a black and white repetitive signal instead of a halftone signal. Also, at this time, the non-inverted output 17 of the D-type flip-flop circuit _FF7 is 1 of the clock pulse CPs with respect to the output 16 of the AND gate _G2 .
It is delayed by the period ts, and at the same time has an inverse relationship with the output 16 of the AND gate _G2 , and this output 1
6 and the output 9 of the D-type flip-flop circuit FF ₄ , that is, the signal representing the non-black signal state.
When extracted at AND gate G ₃ , its output 1
As shown in FIG. 8, a black-and-white repetitive signal is obtained which is inverted every cycle of the clock pulse CPs and is replaced by a continuous halftone signal.

Therefore, D representing the white signal immediately before the halftone signal
Non-inverting output 13 of flip-flop circuit _FF6
and the output 18 of AND gate _G3 .
When applied to the input of gate G ₄ and ANDing the two, a black and white repetition signal is obtained at the output 19 of gate G ₃ which is sent out following the white signal immediately before the halftone signal. Furthermore, if the inverted output 14 of the D-type flip-flop circuit FF ₆ , which represents the black signal immediately before the halftone signal, and the output 16 of the AND gate G ₂ are applied to the input of the AND gate G ₅ , and the logical product of the two is taken, As the output 20 of ₅ , a black and white repetitive signal is obtained which is sent out following the black signal immediately before the halftone signal.

By the means described above, a repetitive signal is generated and a repetitive signal is sent out in place of a continuous halftone signal, and these repetitive signals 1
9, 20 are synthesized by OR gate G ₆ , and further
As mentioned above, the OR gate _G7 synthesizes the non-inverted output 15 of the D-type flip-flop circuit _FF3 , that is, the white signal and the black signal, at the same timing.
It is sent to the output OT as processed output 22.

When this output 22 is compared with the image signal 3 in FIG. 3, it has a delay of only a time difference t ₁ with respect to the image signal 3, but the white signal exceeds the first discrimination level L ₁ of the image signal 3. It is “1” for the second
“0” for black signal less than discrimination level L ₂
In addition, when the halftone signal between both discrimination levels L ₁ - _{L 2} is one pixel, that is, one period ts of the clock pulse CPs, when the immediately preceding image signal is a white signal, it is "0", and the same black signal is "0". When the halftone signal is continuous over several pixels, that is, several cycles of the clock pulse CPs, if the immediately preceding image signal is a white signal, it is "0" for each pixel. "1" repeating signal, similar black signal is "1""0" repeating signal for each pixel, and if "0" is used as black level and "1" as white level, continuous A received image is obtained in which the first pixel of the halftone is set to be the opposite of the previous grayscale, and the grayscale continues to be inverted pixel by pixel thereafter. Furthermore, in the halftone of only one pixel, the opposite gradation to the immediately previous gradation is reproduced on the received image.

Therefore, even if photoelectric conversion is performed on white and black areas during photoelectric conversion processing of thin lines and the like during scanning of documents on the transmitter side, the accuracy will still slightly exceed the conventional sole discrimination level. Since the image signal is processed as a signal of the opposite gradation based on the immediately preceding pixel information, instead of being made into a white signal or a black signal depending on whether the pixel is In addition to completely blocking the image, the resolution of the received image is significantly improved, and by repeatedly reproducing the opposite gradation for each pixel for continuous halftones, faithful reception is possible even for multi-gradation originals such as photographs. Image reproducibility is achieved.

It goes without saying that each of the above means can be modified or selected in various ways other than those shown in Fig. 1.A given image signal is once stored in a memory circuit, etc., and while being read out, it is compared with the image signal before storage. The same effect can be obtained even if a signal is determined in place of the halftone signal. Further, it goes without saying that the present invention can be applied not only to the transmitter side but also to the input side of the receiver to obtain similar results.

As is clear from the above description, according to the present invention, in images received by a facsimile apparatus, omission of thin lines in the sub-scanning direction is prevented, and thin lines in the main scanning direction are also reproduced, thereby improving resolution. In addition, since continuous halftones are also reproduced, it is suitable for transmitting two-tone drawings, documents, etc. (white and black), and multi-tone photographs as documents without changing the received image reproduction characteristics. However, it can be used to electronically transmit various types of originals, and extremely effective results can be obtained.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 are time charts showing waveforms at various parts in FIG. 1. IN...Input, PH...Peak value hold circuit,
RV ₁ , RV ₂ ... Potentiometer, CM ₁ , CM ₂
... Comparator, FF ₁ , FF ₂ ... Flip-flop circuit, FF ₃ to FF ₇ ... D-type flip-flop circuit,
_G1 to _G5 ...AND gate, _G6 , _G7 ...OR gate, IV...Inverter, OT...Output, CPr,
CPs...Clock pulses.

Claims (1)

[Claims] 1. A first and a second discrimination level are provided for a facsimile image signal, and a white signal exceeding the first discrimination level, a black signal below the second discrimination level, and a first discrimination level are provided for the facsimile image signal.
an image signal extraction means for sequentially extracting signals corresponding to three gradations of a halftone signal between a discrimination level and a second discrimination level from the image signal; and a signal corresponding to the three gradations extracted from the image signal extraction means. a storage means for temporarily storing whether the signal obtained is a black signal, a white signal and a halftone signal as the immediately preceding picture signal; and a halftone signal is output from the picture signal extracting means following the white signal or black signal. When the image signal is retrieved, it is determined whether the image signal immediately before the retrieved halftone signal is a black signal or a white signal according to the storage contents of the storage means, and this determination state is maintained while the halftone signal continues. a discriminating means for holding a signal, a means for generating a repetitive signal of a black signal and a white signal for each pixel, and a repetitive signal of a white signal and a black signal for each pixel, based on the judgment of the discriminating means, When the image signal is a black signal, a repetitive signal of the white signal and the black signal is sent instead while the halftone signal from the image signal extraction means continues, and when the immediately preceding image signal is a white signal, means for transmitting a repetitive signal of the black signal and white signal instead of the halftone signal while the halftone signal from the picture signal extracting means continues; a repeating signal instead of the halftone signal from the picture signal extracting means; An image signal processing system comprising means for combining and transmitting a white signal and a black signal from an image signal extraction means at the same timing.