JPS639408B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer that automatically eliminates intersymbol interference occurring in a communication transmission path, and in particular to an improvement in an automatic equalizer suitable for high-speed data transmission.

When high-speed data transmission is performed within a limited band, received data is strongly affected by various deterioration factors of the line, and it is impossible for the receiving unit to identify the data in its original state. Therefore, an equalizer is used in the receiving device to compensate for this distortion. Furthermore, in order to keep up with fluctuations in line characteristics and always maintain optimal reception conditions, equalizers in recent years have the ability to perform real-time arithmetic processing on received signals at fixed time slots to change their characteristics to the optimal state. Automatic equalizers with .

By the way, since automatic equalizers find degradation from data components and adaptively perform equalization operations to optimize internal values, it is difficult to identify stationary data points from the beginning of data transmission. This is nearly impossible for polyphase/multilevel data points. Therefore, before data transmission, a signal (hereinafter referred to as a synchronization signal) is required to bring the equalizer into an operable state, and after that, normal multiphase/multilevel data is received. A method of equalization is used. Therefore, if initial synchronization (making it operational) fails, or if synchronization suddenly goes out due to line abnormality during data transmission (in the case of automatic equalizers, this is called divergence). , has the disadvantage that it cannot resynchronize itself without a synchronization signal.

The drawbacks of the conventional automatic equalizer will be explained in more detail. After synchronization with a synchronization signal, if the quality of the received signal deteriorates extremely due to line disturbances, the automatic equalizer will lose the equalization state due to excessive degraded components in the data components. and the synchronization will be lost. When it diverges, polyphase
In the case of multi-level data points, even if the disturbance is recovered, it is impossible to equalize them by themselves for the reasons mentioned above. Therefore, once a divergence state occurs, this state will continue unless the synchronization signal from the transmitting section is received again. In order to re-equalize, it is necessary to convey the divergence state to the transmitter using some kind of signal and receive the synchronization signal again, but in a polling mode system that is branched into several parts as shown in Figure 1, If request signals are sent from each terminal modem at the same time, the signals will collide with each other and will not be transmitted properly to the center station. Furthermore, even if the data is transmitted normally to the center station without collision, the center station temporarily interrupts the sending data and issues a synchronization signal, resulting in a reduction in data transmission efficiency. In FIG. 1, 1 is a center station, 2, 3, and 4 are respective terminal stations, and 5 is a request signal from the terminal station. In this way, high-speed data transmission with multi-phase/multi-level data points has a drawback in that it is not possible to re-equalize the divergence of the receiving section by itself.

The object of the invention is to provide an automatic equalizer that eliminates the above-mentioned drawbacks.

The present invention has two discriminating parts of an automatic equalizer, and the discriminating parts are switched between the normal state (equalization state) and the abnormal state (divergence state). This automatic equalizer is characterized in that it does not identify data, but identifies multi-level data by treating it as if it were binary.

In multiphase/multilevel modulation, one transmission data is divided into amplitude components according to orthogonal X and Y coordinates, each modulated by a sine carrier wave and a cosine carrier wave, and then summed. In the receiving section, two demodulating sections are provided and demodulated using sine and cosine carrier waves, respectively, to obtain two pieces of data that are orthogonal to each other. This represents the respective amplitudes in the X and Y coordinates, and is represented as shown in FIG. 2. In FIG. 2, the circles are points located at the same location as the transmitted data, and if there is no line deterioration, these will be the received data points. Point a is a degraded received data point of point A.

FIG. 3 shows the configuration of a conventional automatic equalizer. Here, the received data can be expressed as a complex number if its real part component is X and its imaginary part component is Y. Therefore, the two demodulated data X and Y are RD=(X, Y)=
Let it be (X+jY). Furthermore, the values of elements such as C _o in this equalizer are considered in the same way, and calculations are performed using complex numbers. 6 is a receive data register, 7 is a tap gain register, 8 is a multiplier, 9 and 11 are adders,
10 represents a discriminator.

The received data RD is given to the received data register 6, and for each time slot of the received data, each element X _-2 , X _-1 , X ₀ , X ₁ , Shift X ₂ in order.
In register 7, tap gain (equivalent correction amount) is stored in each element C _-2 to _C2 , and the contents of each element of register 6 and each element of register 7 are calculated by multiplier 8 and added. Vessel 11
It is configured to be given to Adder 11
The output is equivalently compensated received data RD' and is used as an output. The equalization result for the received data X ₀ at the center of the received data register 6 is ₂ 〓 ^n=-2 C _o X _o . This value is compared with the ideal value in the discriminator 10 to obtain an error amount, which is sent to the adder 9 and added to the tap gain, and the tap gain _Co stored in the register 7 is further corrected to the optimum value. By repeating this operation, the error amount of the output data of the automatic equalizer is minimized for each time slot, and equalization with the minimum error amount can be constantly performed. For example, when point a shown in FIG. 2 is received, it is compared with an ideal value in the discriminator 10 (because it is closest to point A), and the distance between a and A is obtained as the error amount.

FIG. 4 shows the configuration of an embodiment of the present invention. This equalizer is the same as the equalizer shown in FIG. It is characterized by having a selector 20 for selecting. The discriminator 18 is characterized by having two judgment circles as shown in FIG. The ○ points in FIG. 5 are the same as the ○ points in FIG. 2. Detector 19
When detecting that the automatic equalizer is in a divergent state, it switches the operation of the selector 20 to select and output the output of the discriminator 18.

It is easy to detect that the automatic equalizer is in a divergent state, and an example of the circuit of the detector 19 is shown in FIG. 21 represents a detector, which forms a window by providing a certain range in the X and Y directions for each data point to be received, and when the actual received data is outside this window, it is set to "1". Output. Furthermore, since the received data is output from the adder for each time slot, the output of the detector 21 is similarly output for each time slot. Next, in the AND circuit 22, the clock (which has the same period as the time slot) and
The AND logic is used as the clock for the counter 23. In this way, the output of the detector 21 will be “1”
In this state, the count of the counter 23 advances. 24 represents a timer circuit, which provides a clear pulse to the counter 23 at regular intervals. In other words,
If there is data that falls outside a window with a certain range (that is, data that is extremely degraded or in a divergent state), the counter ₂₃ counts up. (This is similar to counting the number of data) Q _o = "1" and it is determined that the automatic equalizer is in a divergent state. Q _o becomes the output of the detector 19.

Next, an automatic equalizer using the discriminator 18 as a path will be explained based on FIG. In the discriminator 18, the reference value is not the 16 points but the great circle shown in FIG. 5 as the reference circle. That is, when 16 points of received data are projected onto both the X and Y axes, there are 7 values on the X axis, but this is considered as if it were binary data, and other values are considered to be superimposed with noise. Also, considering the Y axis in the same way, the reference value becomes a circle when viewed in two dimensions, X and Y. For example, received data b is the value closest to point B, but B
This means that instead of taking the point and the error amount, draw a perpendicular line from point b to the great circle and use the distance l as the error amount. In other words, if we consider that the data is binary, even if we calculate the amount of error from the reference value and correct the automatic equalizer, the probability that it will be corrected is greater than the probability that it will be incorrectly corrected. If the values are averaged sufficiently, the automatic equalizer will be able to perform equalization.

By the way, if this method is used for the degraded point C in the small circle, the distance to the large circle will be used as the error amount, which will result in a larger value than the actual error amount, which will have a negative effect on the overall degree of deterioration. I end up giving. Therefore, conversely, better results can be obtained with respect to the overall degree of deterioration by ignoring the data within the small circle (not taking the amount of error). In other words, in the discriminator 18, the X-axis (in-phase) and Y-axis (orthogonal) of the output signal of the adder 11
The sum of the squares of is calculated and compared with the radius value of the small circle.Only when the radius value is exceeded, the distance l from the large circle is calculated and used as the error amount. Correcting the tap gain value using the error amount obtained in this way is
The purpose is to adjust the tap gain of the equalizer so that the output of the adder 11 becomes closest to the reference value of the great circle as an average value. After the detector 19 detects the divergence state in this way, the discriminator 18 calculates the amount of error using the two large and small circles, corrects each C _o by the value, and after a certain time, the equalized state is reached. If you return to
Since the detector 19 outputs a normal state, the discriminator 1
Instruct the selector to select 7. In this way, by adding the second discriminator 18, detector 19, and selector 20 to the conventional example shown in FIG. By using the threshold value of the discriminator 18, it becomes possible to return to the equalization state by itself without a synchronization signal.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of a polling mode system in which the line is branched into three, Figure 2 is a layout diagram showing one configuration of multiphase/multilevel data points, and Figure 3 is a diagram of a conventional automatic equalizer. Block diagram: FIG. 4 is a block diagram showing an embodiment of the automatic equalizer of the present invention;
FIG. 5 is a layout diagram illustrating a multiphase/multilevel data point configuration of the discriminator shown in FIG. 4, and FIG. 6 is a block diagram showing an example of the detector shown in FIG. 4. 6... Received data register, 7... Tap gain register, 8... Multiplier, 9, 11... Adder, 10... Discriminator, 18... Discriminator, 19...
...Detector, 20...Selector.

Claims (1)

[Claims] 1. In an automatic equalizer used in a multiphase/multilevel modulation method that transmits information by amplitude modulating each of a sine carrier wave and a cosine carrier wave, the divergence state of the automatic equalizer is detected and the in-phase output signal and quadrature output signal are When the sum of squares of the signal exceeds a first predetermined threshold, the tap gain is adjusted so that the average value of the sum of squares becomes closest to a second predetermined threshold that is substantially larger than the first threshold. An automatic equalizer characterized by adjusting.