JPS6393219A - Voltage converting circuit - Google Patents

Abstract

PURPOSE:To obtain an output voltage higher than the gate withstanding voltage value of main transistors TRs without consuming an unnecessary power by providing a gate driving voltage generating circuit and a gate driving voltage switch and allowing these switches to alternately perform the switching operation in accordance with the logical state of a bit signal to alternately switch a pair of main TRs. CONSTITUTION:Gate driving voltage generating circuits 20 and 30 for main TRs 11 and 12 consist of Zener diodes 21 and 31 and resistances 22 and 32, and Zener voltages of diodes 21 and 31 are gate driving voltages as they are. Gate driving voltage switch means 40 and 50 consist of MOS TRs 41 and 51. When the logical value of a bit signal BS is set to '1', the TR 41 is opened and the TR 51 is closed, and the gate driving voltage generated by the diode 21 is opened and that generated by the diode 31 is short-circuited, and therefore, the main TR 11 is closed and the main TR 12 is opened, and a supply voltage is outputted from an output V0. When the logical value of the bit signal BS is changed to '0', open/close states Of respective TRs are switched to opposite states.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a voltage conversion circuit that inputs each digital bit signal and converts the bit signal into an on/off output having a predetermined voltage value.

[Prior art and its problems]

The voltage conversion circuit as described above is used, for example, to drive a display panel, and depending on the type, the voltage conversion circuit is 100 to 2
A driving voltage of 00V is required, and it is necessary to convert a TTL level digital data signal specifying the pattern to be displayed into a signal of such high voltage. In addition, it is necessary to provide a voltage conversion circuit for each bit of display pattern data, and since a large amount of pattern data is displayed simultaneously on one display panel, a very large number of voltage conversion circuits must be housed in an integrated circuit. There is a need. Therefore, each voltage conversion circuit must be as simple in construction as possible and can be manufactured at low cost.Also, since high-speed display is always required, the circuit operation must be as fast as possible. As an example of a conventional circuit suitable for such an application, the one shown in FIG. 3 is known. The circuit shown in FIG.
1B It obtains an on/off output Vo having a power supply voltage value supplied between points P and N, and is made by connecting four P-channel MOS transistors 2 to 5 in a bridge shape, and the two transistors on the upper side of the figure The gates 4.5 receive the potential at the midpoint of each opposite side in a crossed manner as shown in the figure. On the other hand, the gates of transistors 2 and 3 on the lower side of the figure each receive a bit signal BS or its complementary signal BS via an inverter 6, and are alternately opened and closed depending on the logic value of the bit signal BS. As can be easily seen, when the bit signal BS takes the value "0", the transistor pair 2, 5
is closed, transistor pair 3 and 4 are opened, and the power supply voltage is output from output Vo. When the bit signal BS takes the value "1", the opening and closing operations of both transistor pairs are reversed, and the output value from the output Vo becomes zero. This voltage conversion circuit has a very simple configuration, but since an overvoltage is applied between the gate and source of all transistors, it is suitable only when the output voltage value is about 20V or less.For example, considering transistor 5, When transistor pair 2.5 is closed and transistor pair 3.4 is open, the potential at the mutual common point of transistors 2 and 4 is
Since it is closed, it is almost at the ground potential, so the gate potential of the transistor 5 is also at the ground potential, while its source and drain are at the power supply potential. In other words, in this case, approximately ? between the gate and source of transistor 5? [A voltage equal to the voltage will be applied, and the same applies to other transistors. Therefore, this conventional circuit can only handle an output voltage within the range of 1 volume of alcohol between the gate and the source. However, as is well known, the operating threshold of a MOS transistor is sufficiently low to respond to TTL level signals, and the thickness of the gate oxide film must be increased to increase the allowable withstand voltage between the gate and source. If it is strengthened, the operating threshold will become high. In order to solve this problem, the applicant proposed the circuit shown in Fig. 4 (Japanese Patent Application No. 112495/1982). In this circuit, the output transistor is a P-channel MO3I-transistor 11 that is alternately opened and closed. There are two N-channel MOS transistors 12 and 12, and drive transistors 13 and 14, both of which are N-channel MOS transistors, are provided for gate control. A drive transistor 1 is used for gate control of the upper main transistor 11.
A voltage divider circuit consisting of a resistor 15, 16 connected in series with 3 is provided, and when the drive transistor 13 is closed, the resistor 15 is connected between the gate 1 and the source of the main transistor 11.
．． A divided voltage of the power supply voltage set at a ratio of 16 is applied, and the main transistor 11 is thereby closed. Of course, when the drive transistor 13 is open, the gate potential of the main transistor is the same as the a potential, i.e. its source potential, and thus the main transistor. is operated to open. Therefore, the gate and source of the main transistor 11 have at most an amount a! determined by the ratio of the two resistors 15.16! Since only one voltage is applied, a high power supply voltage, that is, an output voltage can be handled by the main transistor having a relatively low gate-to-source breakdown voltage. A power supply voltage dividing circuit consisting of a resistor 17 and a Zener diode 18 is provided for operating the lower main transistor 12, and the Zener voltage of the Zener diode 8 is applied between the gate and source of the main transistor 12. ,
The main transistor 12 is opened and closed by opening or short-circuiting this Zener voltage by the drive transistor 14 which is opened and closed by the bit signal BS. Therefore, the voltage applied between the gate and source of this main transistor does not exceed the Zener voltage.
As can be easily seen, when the bit signal BS is "1", the redrive transistors 13 and 14 are closed, but the main transistor 11 is closed and the main transistor 12 is open, and when the bit signal BS is "0", the redrive transistors 13 and 14 are closed. Since the opening and closing operations of each transistor are reversed, both main transistors are alternately opened and closed. The voltage conversion circuit according to this prior application has the advantage of being able to handle a high output voltage with a main transistor having a relatively low gate withstand voltage, but a weakness was discovered in the process of putting it into practical use. This will be explained with reference to FIG. Figure 5 shows the operation when the bit signal BS disappears at time to and the voltage conversion circuit turns off its output Vo in response to this, as shown at +al. , the gate potentials Vl and V2 of the main transistors 11 and 12 are respectively shown. Before time 10, the gate potential v1 of the main transistor 11 is lower than the potential of the power supply point P by the voltage drop Vr set by the resistor 15. It rises over time as shown in the figure from time to, and the main transistor 1 rises from the power point potential P.
It intersects with a line of potential lower by the operating threshold value vth of 1 at time tl. After this time, the gate drive voltage to the main transistor is below the operating threshold, so the main transistor 11 is activated at time t.
1 for closing operation. On the other hand, the gate potential v2 of the main transistor 12 is at the potential at point tB before time to, rises over time from time 10, and finally reaches the Zener voltage Vz of the Zener diode 18; Since the operating threshold (fiVth) of the main transistor 12 is reached at time t2, which is relatively early in the rise, the main transistor 12 is closed at that time t2.As a result, the output voltage vO becomes as shown in the figure (d+) Between time t2 and tl, the upper power point potential P drops to the lower power point potential N, and both times t2.
Since the main transistors 11 and 12 are both closed in the middle of tl, the power supply is short-circuited via the on-resistance of both main transistors, so that a short-circuit current Is as shown in FIG. 5(e) is generated. This short-circuit current naturally increases the power consumption associated with the operation of the voltage conversion circuit, and the faster the circuit operation and the higher its operating frequency, the more power consumption will occur, and if this increase is excessive, then the power consumption will increase. This may also damage the output transistor. This drawback can be overcome by reversing the order of times tt and tz, but the operating threshold value vt of the main transistor
The voltage drop Vr and Zener voltage Vz for h must be several times the threshold value vth to ensure the opening/closing operation of the main transistor, so the gate potentials Vl, V
Time t2 cannot be set before tl unless a very large difference is made in the time constants of the rising edge of 2, and it is actually difficult to change the circuit constants so drastically. Another weakness of this circuit is that it takes a relatively long time from time to to time t1 when the main transistor 11 opens, and if we try to speed up the circuit operation in response to the above-mentioned demand for higher speeds, This time inevitably becomes a bottleneck.

[Purpose of the invention]

In view of the above circumstances, it is an object of the present invention to provide a voltage conversion circuit that can obtain an output voltage higher than the gate breakdown voltage of the main transistor without wasting power.

[Key points of the invention]

The above object is to supply a DC voltage of a predetermined value to the voltage conversion circuit mentioned at the beginning according to the present invention. A pair of main transistors each configured as a Mos transistor are connected in series between a pair of power points of the source, and a 1! a pair of gate drive voltage generation circuits each generating a gate a dynamic voltage of the main transistor by dividing the im pressure;
Each of the gate drive voltage generation circuits is provided with a pair of gate drive voltage switch means connected to each other so that the gate drive voltages generated can be short-circuited, and the gate drive voltage switch means is configured to operate according to the logic state of the bit signal. This is achieved by alternately opening and closing the main transistors and taking out on/off outputs from the mutual contact points of both main transistors. In the above configuration, the pair of main transistors are two MOS transistors that are alternately opened and closed as in the case of the previous application, but each main transistor is Gate drive voltage generation circuits that divide the power supply voltage for each transistor are provided in a phased manner. As a means for voltage division, a division using two resistors or a combination of a resistor and a Zener diode can be used. The gate drive voltage switch means is a gate drive voltage switch (IS) which opens and closes the main transistor by shorting or opening the gate drive voltage generated by the dynamic voltage generation circuit, and is most simply a single MOS transistor. By means of this gate drive voltage switch means, when the gate dynamic voltage is short-circuited, the main transistor is operated to open, and conversely, when it is opened, the main transistor is operated to be closed. Now, in the above-mentioned conventional technology, the problem of short-circuit current occurred because the opening operation time of one main transistor was longer than the closing operation time of the other main transistor, but in the above-mentioned configuration of the present invention, Since the opening operation of the main transistor is performed by short-circuiting the gate drive voltage generated by the gate drive voltage generation circuit by the gate drive voltage switch means, the opening operation time of the main transistor can be made essentially shorter than before. can. That is,
This opening operation time is determined by the gate capacitance of the main transistor and the short circuit resistance of the gate drive voltage switch means.
When a transistor is used, by selecting a low on-resistance, the opening time of the main transistor can be made much shorter than in the past. In order to eliminate the problem of short circuit current, it is necessary to make the closing operation time of the other main transistor the same or slightly longer than the opening operation time of one main transistor, but this time, the gate drive voltage According to the prior art, if the closing operation time is kept at the same level, this requirement is usually satisfied, and if necessary, this requirement can be easily satisfied by just slightly changing the circuit constants. In this way, according to the present invention, the short circuit current in the prior art is eliminated, and as can be seen from the above description, the operating speed of the voltage conversion circuit can be increased. In other words, the time required to switch the open/close state of the main transistor of the circuit of the present invention is long (although it takes only about the time required for the closing operation of the main transistor in the prior art; Since the turn-on time is usually longer than the turn-on time during the closing operation, the opening operation time of one main transistor is actually made shorter than the closing operation time of the other main transistor by the difference between them. is desirable to eliminate the risk of short-circuit current, but if this difference is made too large, there will be a time when both main transistors are open at the same time when switching operations. In the case of the above-mentioned display panel, the load is generally capacitive, so there is no particular problem if both main transistors are connected for the same amount of time, but if the load is inductive. Since overvoltage may be generated from the load circuit, even if there is a risk of short-circuit current occurring for a short time, the opening/closing operation time should be selected to be approximately the same, and the closing operation periods of both main transistors should be slightly overlapped to prevent simultaneous open conditions from occurring. It is safer to do so.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 shows a voltage conversion circuit according to the present invention together with an electronic circuit that generates a bit signal BS, such as a flip-flop 1 as a latch circuit.The flip-flop shown in FIG. The pattern data PD to be displayed on the panel is received at the D input, and the latch command LS is sent to the clock C.
When received, it is edge triggered and latches the pattern data PO, and outputs the bit signal 85 and its complementary signal BS from its Q output and Q output. The pair of main transistors is a P-channel MOS transistor as a first main transistor 11 and a P-channel MOS transistor as a second main transistor 12 connected in series between a pair of power points P and N from a DC power source that generates a voltage of 150V, for example. An output Vo is derived from a mutual connection point of both MOS transistors, and the load of the voltage conversion circuit is connected, for example, between this output Vo and a negative power supply point N. The first and second gate drive vJ voltage generation circuits 20.30, which respectively generate the gate drive voltages for the first and second main transistors 11.12, are composed of a Zener diode 21.31 and a resistor 22.32, respectively, in this example. is a kind of voltage divider circuit connected in series between power points P and N, and in both cases, the potential of the mutual contact point between the Zener diode and the resistor is set so that the Zener voltage of the Zener diode 21 and 31 becomes the gate drive voltage as it is. is applied to the gates of the first and second main transistors 11.12. The main bodies of the first and second gate drive voltage switch means 40.50 provided to short-circuit and open these two gate drive voltages are respectively constituted by MOS transistors 41.51 in this example, The second of them. The gate drive voltage switch means 50 receives the bit signal BS.
It is constituted by one N-channel MOS transistor 51 which receives at its gate. The other first gate drive voltage switch means 40 can also be composed of one MoS transistor in principle, but in this example, it is customary for a MOS transistor provided on the positive power supply point P side. Accordingly, a P-channel MOS transistor 41 for short-circuiting and opening the gate drive voltage is combined with another N-channel MOS transistor 42 for driving the gate. As shown in the figure, the other MOS transistor 42 is connected in series with a pair of resistors 43 and 44 for setting the gate of the MOS transistor 41 or for generating a gate KW dynamic voltage between the positive and negative power points P and N. When the bit signal BS is received, the logical value of the bit signal BS becomes "
When it is "1", the closing operation is performed, and when it is "0", the closing operation is performed. Both resistors 43 and 44 are of course also load resistors of this other MOS transistor 42, and their mutual common point potential is MO.
Since it is applied to the gate of the S transistor 41, P
The 8-channel MOS transistor 41 is connected to another MO
It performs the same opening/closing operation as the S transistor 42. In the illustrated voltage conversion circuit according to the present invention configured as described above, when the logical value "1" is specified in the bit signal BS, the MOS transistor 41 is opened and the MOS transistor 5 is opened.
1 is closed, the gate drive voltage generated by the Zener diode 21 is opened, and the gate drive voltage generated by the Zener diode 31 is short-circuited, so the first main transistor is closed and the second main transistor is closed. When the transistor is closed and the logic value of the zero-order bit signal BS, which outputs the t conductive voltage from the output Vo, changes to rOJ, each MO shown in the figure. The open/close state of the S transistor shifts to an operation opposite to that described above, and the transient state at this time is shown in FIG. However, this diagram is drawn assuming that the operating threshold values vth of the MO3I transistors are all the same. First, the bit signal BS starts at time t as shown in fa) in the figure. changes from "1" to "0", another MOS transistor 42 in the first gate drive voltage switch means 40 is immediately closed by the complementary bit signal BS, and the until then positive power supply point of the MOS transistor 41 is closed. The gate potential Vll, which was at the potential P, falls as shown in the figure (bl), and the difference from the positive 1a source point potential P is the operating threshold value Vt.
At time tll when h is reached, the MOS transistor 41 is also closed. The time constant of the fall of the gate of the MOS transistor 41 during this time is determined by the product of the gate capacitance of the MOS transistor 41 and the resistance value of the resistor 43, and the value of the resistor 43 generates the gate drive voltage of the MOS transistor 41. Since the value is low enough to
The time from o to time tll is short, and when the MOS transistor 41 closes, the Zener diode 21 of the first gate SIN dynamic voltage generation circuit 20, which had previously closed the first main transistor 11, The Zener voltage Vzl indicated by the peak) is short-circuited, and the gate potential V of the main transistor rises toward the positive power point potential P as shown in the figure. It is determined by the capacitance and the on-resistance of the MOS transistor 41. Since this on-resistance is sufficiently low, the gate potential vl rises with a fast time constant, and the difference between the gate potential v1 and the positive power point potential P becomes the operating threshold of the main transistor. The first main transistor 11 is opened at time t1 when the voltage is turned off. On the other hand, the MOS of the second gate drive voltage switch means 50
The transistor 51 is opened at time to, and the gate drive voltage of the second D1 dynamic voltage generating circuit, which had been short-circuited, is immediately released, so that the second main transistor 1
The gate potential v2 of the second gate drive voltage V2 starts to rise immediately from time 10, and eventually rises to the Zener voltage Vz2 of the Zener diode 31 in the second gate drive voltage generation circuit. The time constant of this rise is the second main transistor 1
The rise of the gate potential v2 of the main transistor in FIG. As shown, it is much slower than that of the gate potential v1 for the first main transistor. Therefore, the gate potential ν2 of this second main transistor is the operating threshold value vt of this main transistor.
The time t2 at which the second main transistor 12 is closed upon reaching h is later than the time t1 at which the first main transistor 11 is opened, so there is no period during which the amphibian transistors are simultaneously in the closed state. Short circuit currents no longer occur as in the prior art. Note that the closing operation time in the circuit of the present invention for the second main transistor from time to to time t2 described above is by no means longer than in the case of the prior art, and is essentially the same as in the case of the conventional circuit. On the contrary, the opening time for the first main transistor is much shorter in accordance with the present invention than in conventional circuits, thereby eliminating the occurrence of short circuit current. As a result of the above, when the first main transistor 11 opens, the supply of the MR voltage to the output Vo to the load is cut off.
Due to the closing operation of the second main transistor 12 after eL, the residual voltage at the load is immediately erased by the short circuit caused by the second main transistor. When the logical value of the bit signal O5 becomes "1" again, 'vl?' is output from the output Vo as described above. I! The voltage is output again, but the opening operation time for the first main transistor 11 at this time is slower than the opening operation time for the second main transistor 12 for the same reason as mentioned above, and in this case as well, the opening operation time for the first main transistor 11 is slower than the opening operation time for the second main transistor 12. The invention can eliminate the possibility of short circuit current occurring. In addition to the embodiments described above, the present invention can be implemented in various embodiments. The Zener diode in the dynamic voltage generation circuit is the most desirable in order to generate a stable gate drive voltage for the main transistor even if the power supply voltage fluctuates, but the resistance In many cases, it is more advantageous to replace it with a 1MO5 transistor (or resistive connection).Also, as a gate drive voltage switch means, various known technologies can be combined to create a configuration depending on the application, and the opening/closing operation time of the main transistor is determined. The time constant of the above-mentioned change in gate potential over time can also be adjusted within the spirit of the present invention by appropriately selecting circuit constants to adjust the slowing speed and the opening/closing order of the main transistors. Effects of the Invention As can be seen from the above description, in the present invention, a power supply voltage having a predetermined value is outputted on and off from an output point according to a bit signal input for a pair of main transistors. A gate drive voltage generation circuit and a gate drive voltage switch means are provided, and the gate drive voltage switch means is alternately opened and closed according to the logic state of the bit signal, thereby alternately opening and closing the main transistor. Since the on/off output is taken out from the mutual contact point, first of all, even if the supply voltage from the power supply is increased, the voltage between the gate and source of the main transistor is higher than the gate drive voltage generated by the gate drive voltage generation circuit. There is no fear of voltage being applied, and a high output voltage value can be obtained by using a MOS transistor used as the main transistor with a low gate withstand voltage value. Secondly, according to the present invention, the gate drive voltage generated by the gate drive voltage generation circuit can be short-circuited and opened by the gate drive voltage switching means described above, so that the opening operation time of the main transistor is shorter than the closing operation time. This makes it possible to prevent the two main transistors from being in a closed operating state at the same time, so that a short circuit T! between a pair of power supply points!
It is possible to eliminate wasteful power consumption in the voltage conversion circuit that generates the first current or is based on it. Alternatively, if the circuit constants are appropriately selected depending on the application, that is, the load conditions of the voltage conversion circuit, the simultaneous closing of the two main transistors can be limited to only a short period of time, thereby preventing the occurrence of harmful overvoltage in the load. It can also be done to prevent. Thirdly, as is already clear from the above description, according to the present invention, the operation of the voltage conversion circuit can be made faster. As can be seen from the illustrated circuit, the circuit of the present invention can be easily integrated into an integrated circuit. For example, as a display drive circuit for multi-bit pattern data on a display panel, a large number of voltage conversion circuits can be integrated into a small semiconductor. Advantageous for integration within the channel.

[Brief explanation of the drawing]

Figures 1 and 2 are for explanation of the present invention. FIG. 1 is a circuit diagram showing an embodiment of the voltage conversion circuit according to the present invention together with related circuits, and FIG. 2 is a waveform diagram of main signals in the circuit of the present invention for explaining its operation. Fig. 3 is a simplified circuit diagram showing a conventional example of a voltage conversion circuit, Fig. 4 is a circuit diagram showing a circuit related to the applicant's earlier application, and Fig. 5 is an internal diagram of the circuit to explain the problems it has. In Figure 0, which is a waveform diagram of the main signals, 1: an electronic circuit or flip-flop that generates bit signals; 11: first main transistor; 12: second main transistor; 20: first gate drive voltage generation circuit. ,2
1: Zener diode, 22: Resistor, 30: Second gate drive voltage generation circuit, 31: Zener diode, 3
2: resistor, 40: first gate drive voltage switch means,
41: MOS transistor, 42: another MO3I-transistor, 43.44: resistor, 50: second gate drive voltage switch means, 51: MOS transistor, aS:
Bit signal, BS: Complementary signal of the bit signal, N: Negative power supply point or its potential, P: Positive power supply point or its potential, tO: Output switching operation start time, tl: Main transistor closing operation time, tll : operating time of another MOS transistor, t2: closing operation time of the main transistor, vo: output or output voltage of the voltage conversion circuit, vl: gate potential of the first main transistor, V2: gate potential of the main transistor of m2, vll: gate potential of another MOS transistor, Vth: operating threshold of the MOS transistor, Vzb: generated gate drive voltage of the first gate drive voltage generating circuit or Zener voltage of the Zener diode in the circuit, Vz2: second gate drive voltage This is the gate drive voltage generated by the gate drive voltage generation circuit or the Zener voltage of the Zener diode in the circuit. ,〆7 →Married woman W Toyamaguchi & i” ゝ, er4 Figure 5

Claims (1)

[Claims] 1) A circuit that inputs each digital bit signal and converts the bit signal into an on/off output having a predetermined voltage value, the circuit comprising a pair of power supplies that supply a DC voltage of the predetermined value. A pair of main transistors connected in series between power points and each configured as a MOS transistor, and a pair of gates inserted between the pair of power points to divide the power supply voltage and generate gate drive voltages for the main transistors. A drive voltage generation circuit, and a pair of gate drive voltage switch means connected to each of the gate drive voltage generation circuits so that the gate drive voltages generated can be short-circuited, the gate drive voltage switch means being connected to the bit signal. 1. A voltage conversion circuit characterized in that the main transistors are alternately opened and closed according to the logic state of the main transistors, and an on/off output is taken out from a mutual connection point of both main transistors. 2) The voltage conversion circuit according to claim 1, wherein the pair of main transistors is composed of a P-channel MOS transistor and an N-channel MOS transistor. 3) The circuit according to claim 1, characterized in that each gate drive voltage generation circuit is a series connection circuit of a Zener diode and a resistor, and the Zener voltage of the Zener diode is generated as the gate drive voltage. voltage conversion circuit. 4) In the circuit according to claim 3, the resistance values in both gate drive voltage generation circuits are selected according to the gate capacitances of both main transistors so that the closing operation times of both main transistors are separated from each other. A voltage conversion circuit characterized in that: 5) In the circuit according to claim 3, the resistance values in both gate drive voltage generation circuits are selected according to the gate capacitances of both main transistors so that the closing operation times of both main transistors slightly overlap. A voltage conversion circuit characterized by: 6) A voltage conversion circuit according to claim 1, wherein each gate drive voltage switch means is configured as a MOS transistor.