JPS6392273U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a block diagram showing a conventional gain control device.
FIGS. 3 to 6 are diagrams showing the received power level with respect to the distance of the gain control device. In the figure, 1 is the receiver, 2 is the attenuator, and 3 is the A/
D converter, 4 clutter suppression circuit, 5 first S
TC circuit, 6 is an adder, 7 is a second STC circuit,
A is the target signal (target reflected signal), B is the clutter signal (unwanted reflected signal), and C is the received power saturation level of the receiver. Note that the same reference numerals in each figure indicate corresponding parts.

Claims (1)

[Scope of utility model registration request] A receiver that receives reflected waves from a target, an attenuator that attenuates the received power level so that the receiver does not become saturated, a temporal sensitivity adjustment circuit that changes the received level according to the distance, and a receiver that receives reflected waves from the target. In radar equipment that consists of an A/D converter that converts analog signals into digital signals and an unnecessary reflected signal suppression circuit that suppresses unnecessary signals in the received signal, saturation of the received power level of the receiver due to unnecessary reflected signals What is claimed is: 1. A gain control device comprising: a temporal sensitivity adjustment circuit for preventing a target reflected signal; and a temporal sensitivity adjustment circuit for equalizing a received power level of a receiver due to a target reflected signal.