JPS6390252A - Direct current compensating circuit - Google Patents

Abstract

PURPOSE:To eliminate a fluctuation in the direct current level of a direct current interrupted Return to Zero input pulse train by providing a slicer, an integration circuit, a direct current amplifier and an adder circuit, detecting the scale of a direct current signal to be compensated and adding a direct current voltage corresponding to the value to the input pulse train. CONSTITUTION:Only the positive part of the pulse (or only negative part) is taken out by the slicer 13, the output is integrated in the integration circuit 14, thereafter, amplified to a proper level by the direct current amplifier 15, the output is added to a main signal by the adder circuit 16, thereby, the direct current can be compensated to the main signal. In this case, the quantity p' of the fluctuation in a direct current level is linearly changed, however, an integrated value is not changed linearly to a mark ratio, so that the direct current cannot be completely compensated. However, for instance, when the gain of the direct current amplifier circuit 15 is determined as indicated by the curve 31 of broken lines in which the difference between an integrated value to mark ratio characteristic and the quantity P' of the fluctuation in the direct current level is minimum, the direct current fluctuation can be suppressed with an error of about 7% of a pulse duration to all the mark ratio.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit for compensating the DC component for a previously input signal whose DC component is blocked by a transmission line or the like in a receiving side device of a digital communication system. In particular, the present invention relates to a DC compensation circuit when the input signal is an RZ (return-to-zero) pulse.

2. Description of the Related Art Conventionally, this type of DC compensation circuit has generally included a DC clamp circuit using a diode and a capacitor in the main signal path. FIG. 7 is a block diagram showing the configuration of one example, which consists of a clamp circuit 71, an input buffer 72, and an output buffer 73. Therefore, in this conventional DC compensation circuit, in order to reduce the error in the DC clamp operation caused by the diode of the clamp circuit 71, a DC clamp circuit is connected between the input buffer 72 with low output impedance and the output buffer 73 with high input impedance. 71 is connected, but when trying to apply such a circuit to an ultra-high-speed pulse transmission device where the input signal speed is several hundred bits per second or more, (1) Such an ultra-high-speed pulse transmission device It becomes difficult to realize buffer circuits 72 and 73 that can sufficiently reduce the output impedance or sufficiently increase the input impedance in the (ultra-wideband) region, and clamping is not performed completely, resulting in incomplete DC compensation.

(2) Since it becomes difficult to make the frequency vs. gain characteristic of the buffer flat over an ultra-wide band, the input signal waveform is distorted, which causes the DC compensation characteristic to deviate from its ideal value.

(3) For input buffers and output buffers, a seven-emitter follower circuit using bipolar transistors or a source follower circuit using field effect transistors such as GaAs FETs (gallium arsenide FETs) is usually used, but as shown in FIG. When such circuits are connected in two stages in series, there are drawbacks such as extremely low oscillation at extremely high frequencies and difficulty in obtaining stable operation.

Problems to be Solved by the Invention The purpose of the present invention is to solve the above-mentioned drawbacks, namely, in ultra-high-speed pulse transmission lines, DC compensation is incomplete and distortion occurs.
Another object of the present invention is to provide a DC compensation circuit which solves problems such as easy oscillation at extremely high frequencies.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a slicer for slicing binary R, Z input signals subjected to direct current interruption at a ground potential, and an integrator for integrating the output of this slicer. A configuration is adopted that includes a circuit, a DC amplifier that amplifies the output signal of the integration circuit, and an addition circuit that adds the output voltage of the DC amplifier to the input signal.

Operation Since the present invention is configured as described above, the input signal to be compensated is sliced by a slicer, further integrated by an integrating circuit, amplified to an appropriate level by a DC amplifier, and added to the main signal using an adder circuit. Thus, the DC component can be compensated for.

Example Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which shows a block diagram of an embodiment of the present invention, the DC compensation circuit of the present invention includes a signal input terminal 11, a slicer 13 that divides this input signal into two and slices it at ground potential, and this output signal. It consists of an integrating circuit 14 that integrates, a Vi fluency amplifier 15 that amplifies the output of this integrating circuit 14, an adding circuit 16 that adds this output to the main signal, and an output terminal 12 that outputs the added data. There is.

Next, the operation buttons of this embodiment will be explained. For simplicity, the pulse is assumed to be a rectangular wave with an occupancy rate of 50%. The ratio of the number n of marks to the total number N of binary pulses (marks t or spaces) that arrive at the input terminal within a certain period of time is called mark rate sn = n / I''J. When subjected to DC interruption, the DC level of this manual pulse train varies depending on the mark rate.This situation is shown in Figure 2 for the case of N = 4.As is clear from the example in this figure, the RZ pulse train When the amplitude value of is 1, the amount of variation from the DC reference level (ground potential) (positive direction is P).

(the negative direction is y) is P” for any mark rate m
(1-m)/2 (0<m≦1), P'=m/2
(0≦m≦1). FIG. 3 shows the DC level fluctuation amount P' with respect to the mark rate m.

On the other hand, when the input binary R, Z pulse train is sliced at ground potential, only its positive part (or only its negative part) is extracted, and it is integrated by an integrating circuit, the output signal is It changes as shown in Figure 4. Note that the absolute value of the integral value is the same whether only the positive part is extracted or if only the negative part is extracted, and only the polarity is different. Therefore, only the positive part (or only the negative part) of the pulse is extracted by the slicer 13, and the output is sent to the integrating circuit 1.
4, the DC amplifier 15 amplifies the signal to an appropriate level, and the adder circuit 16 adds the output to the main signal, thereby making it possible to perform DC compensation on the main signal. In this case, the DC level fluctuation amount P' in Fig. 3 changes linearly, whereas the integral value in Fig. 4 does not change linearly with respect to changes in mark ratio, so it is not possible to compensate completely. However, if the gain of the DC amplifier circuit 15 is determined as shown in curve a31 of the broken line in FIG. On the other hand, DC fluctuations can be suppressed with an error of about 7 inches in pulse width, which is sufficient for practical use.

Depending on whether the slicer extracts the positive part or the negative part of the pulse, it is possible to select whether the phase between the input and output of the DC amplifier (Fig. 1, 15) is positive or negative. do it.

FIG. 5 shows a specific example of a DC amplifier (15 in FIG. 1), which is a circuit used when extracting the negative part of a pulse using a slicer. Phase amplification is performed. 53 is a power supply for adding an appropriate offset voltage to the DC voltage applied to the adder circuit (16 in FIG. 1) K. When extracting the positive part of the pulse, for example, the operational amplifier 51 may be omitted and the output signal of the integrating circuit may be applied to the terminal 54.

FIG. 6 shows a concrete example of the adder circuit (16 in FIG. 1),
The DC-blocked input signal is applied from the input terminal 61 to the gate electrode of the field effect transistor 62 . On the other hand, the DC compensation signal obtained as the output of the DC amplifier (15 in Figure 1) is added to the main signal via the resistor 63, so that the DC level is always maintained no matter how the mark rate of the main signal changes. compensated to remain constant. This DC-compensated output signal is amplified by the FET 62 and output from the output terminal 64.

Note that even when the pulse occupancy is other than 50%, the DC level can be compensated by similarly changing the gain of the DC amplifier.

Effects of the Invention As explained above, according to the present invention, a slicer, an integrating circuit, a DC amplifier, and an adding circuit are provided, and the magnitude of the DC signal to be compensated is detected, and the DC signal is adjusted according to the value. By adding the voltage to the input pulse train, it is possible to eliminate DC level fluctuations in the RZ input pulse train that has undergone DC interruption. Furthermore, since a circuit for direct current compensation is provided separately from the path through which the main signal passes, there is no need to insert an input buffer or an output buffer in the main signal path. Therefore, practically sufficient DC compensation characteristics can be easily obtained even for ultrahigh-speed pulse signals. Furthermore, since the main signal path is simplified, there is less band deterioration and an output waveform with less distortion can be obtained. Furthermore, since there is no cascade connection of buffers, there is no fear of oscillation and the operation is stable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between DC level fluctuation of an input pulse train and mark rate, and FIG. 3 is a diagram showing the relationship between DC level fluctuation and mark rate in FIG. 2. Fig. 4 is a diagram showing the relationship between the output signal (integral value) of the integrating circuit and the molar ratio, Fig. 5 is a circuit diagram of a specific example of a DC amplifier, Fig. 6 is a circuit diagram of a specific example of an adder circuit, and FIG. 7 is a block diagram of a conventional DC compensation circuit. 11...Signal input terminal, 12...Signal output terminal, 13...Slicer, 14...
・Integrator circuit, 15...DC amplifier, 16...
... Addition circuit, 31 ... Curve showing integral value versus mark rate characteristics, 51.52 ... Operational amplifier, 5
3...Power supply, 54...Terminal, 61...
... Input terminal, 62 ... Field effect transistor, 63 ... Resistor, 64 ... Output terminal. $2 3m brown 4 100m 7m

Claims (1)

[Claims] Binary R that has received DC cut-off at the receiving side device of digital communication
A DC compensation circuit for compensating the DC component of a Z (return-to-zero) pulse input signal includes a slicer that slices the input signal at a ground potential, an integration circuit that integrates the output of this slicer, and this integration circuit. 1. A DC compensation circuit comprising: a DC amplifier that amplifies the output signal of the DC amplifier; and an addition circuit that adds the output voltage of the DC amplifier to the input signal.