JPS6389928A - Arithmetic unit - Google Patents

Abstract

PURPOSE:To reduce signal delay time and heighten performance by providing plural computing elements, an output data register, converted data register and plural converters as exclusive logical sum circuit. CONSTITUTION:The bit width of input data 151, 152 and output data register 102 are made to 8 bits, and the interface 154 of data bus to external equipment is set to require parity of 8 bit data and 1 bit. Output bit of a computing element 101B is converted to bit by a converter 103 as an exclusive logical sum circuit and stored in a converted data register 104. Exclusive logical sum of the output of 4 bits of the register 104 is taken by a converter 105 as an exclusive logical sum circuit and converted to 1 bit. Thereby, data 8 bits and parity 1 bit are sent out to the interface 154 with outside. Thus, as it is enough to pass through one step of the circuit 103, reduction of signal delay time becomes possible and performance can be heightened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an arithmetic unit in an information processing device, and particularly to an arithmetic unit with a duplex configuration.

(Prior Art) Conventionally, in order to check the normality of data output from an arithmetic device, a method has generally been used in which a parity pit is added to each unit of data, for example, every 1 byte or 8 bits.

This parity bit generation method involves parity prediction that creates a parity bit for the final output based on the parity bit added to the input data of the arithmetic unit and the input data itself, using logic separate from the data calculation. The method and arithmetic circuit section are completely duplicated, one arithmetic circuit is used for output data as is, and the other arithmetic circuit performs all the same arithmetic operations as the arithmetic circuit for output data. Parity Piratra is generated from the result. A duplex system is well known.

Figure 2 shows an example of the latter duplex method. show. In FIG. 2, arithmetic units 201A and 201B are circuits of exactly the same logic that perform arithmetic/logical operations designated by a calculation mode 253 on input data 251, 252 given thereto.

The output of the arithmetic unit 201A is sent directly to the output data register 2.
It is stored in 02. Now suppose that the output bit width of the arithmetic unit is 8.
In terms of bits, the output data register is a 20248-bit register.

The parity generation circuit 203 generates an exclusive OR of the 8-bit output from the arithmetic unit 201B. The resulting output is stored in the output parity register 204. Eight bits of the output data register 202 and one bit of the output parity register 204 are sent to the external data bus as a set of data 254.

Does the parity generation circuit 203 generate even parity for 8-bit data? As shown in FIG. 3, the basic circuit block 30 calculates the exclusive OR of every 2 bits.
It is made by combining seven 1'i.

As is clear from the example in Figure 2, the signal delay time required to generate parity bit i from input data is equal to the signal delay time required to obtain data output plus 7 8-bit exclusive ORs. This is the sum of the signal delay time.

(Problems to be Solved by the Invention) As mentioned above, in the conventional duplex type arithmetic device as shown in FIG. In such cases, the disadvantage is that the increase in signal delay for parity generation hinders performance improvement.

An object of the present invention is to provide an arithmetic device with a shorter signal delay time compared to conventional duplex arithmetic devices.

(Means for Solving the Problems) In order to achieve the above object, an arithmetic device according to the present invention performs logically the same operation on input data consisting of a plurality of bits according to a given operation mode, and first and second arithmetic units that obtain output data consisting of a bit width equal to the output data, which stores all of the output data of the first arithmetic unit; and an output data register having a bit width equal to or smaller than that of the input, according to a predetermined first condition. A first converter that outputs conversion data, a conversion data register that stores all outputs of the first converter, and input to all bits of the conversion data register according to a predetermined second condition. a second converter that outputs a second converted data having a bit width smaller than that of the input;
and means for collectively sending the output of the output data register to the outside.

(Example) Next, drawings about the present invention? Refer to and explain.

FIG. 1 is a block diagram showing an embodiment of an arithmetic device according to the present invention.

In FIG. 1, arithmetic units 101A and 10IB are both
These are arithmetic circuits having exactly the same logic and are designed to perform arithmetic/logical operations specified in the °C operation mode 153 on given input data 151 and 152.

The output of the arithmetic unit 101A is sent directly to the output data register 1.
It is stored in 02.

In this embodiment, in order to simplify the explanation, the bit width of the input data 151, 152 and the output data register 102 are all 8 bits (1 byte), and the data bus interface with the external device is 8 bit data. 1
Assume that bit parity is required. It is clear that the explanation of this embodiment can be applied even when the data width is a plurality of bytes when viewed in byte units.

Now, how the 8 bits output from the arithmetic unit 101B are used will be explained.

The 8 bits output from the arithmetic unit 101B are converted into 4 bits by the converter 103.
The data is converted into bits and stored in the conversion data register 104, and its specific contents are the exclusive OR of all 2 bits out of 8 bits. The 4-bit output of the conversion data register 104 is exclusive-ORed by the converter 105 and converted into 1-bit.

This 1 bit is nothing but an even parity bit corresponding to 8 bits of data in the output data register 102.

The 8 bits of data and 1 bit of parity thus obtained are sent to the interface 154 with the outside.

If we compare the parity generation circuit 203 shown in FIG. 2 as an example of the conventional device with the converter 103 of FIG. In order to get The signal delay time is clearly reduced.

The signal delay time of the parity bit output to the external interface 154 increases as the converter 105 performs exclusive OR on the output of the conversion data register 104, but this is because there is no margin in the signal delay time of the external interface. If there is, it is realistically possible, and if the margin is small, allocating the number of bits of the exclusive OR between converters 103 and 105 properly allocates the necessary performance improvement money. It is possible to achieve this goal.

Bit width of conversion data register? Widening can reduce the signal delay time in the converter 103 even if the amount of metal in the register increases slightly, so in order to improve performance, various bit width combinations are used in the actual device design. An attachment can be considered.

(Effects of the Invention) As explained above, the present invention can be applied to cases where the signal delay time is longer than that of a logic circuit that only performs data operations, such as a logic circuit for generating parity bits in a duplex arithmetic unit. By reducing the increase in delay, it is possible to realize a higher performance arithmetic device than in the past.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an arithmetic device according to the present invention, FIG. 2 is a block diagram showing an example of a conventional arithmetic device, and FIG. 3 is a specific circuit of the parity generation circuit 203 in FIG. FIG. 101A, l01B, 201A, 201B...Arithmetic units 102.202, 204...Registers 103.105
, 203... Exclusive OR circuit patent applicant NEC Corporation representative Patent attorney Hisashi Inoro 1FM Figure 22 Figure 3

Claims (1)

[Claims] first and second arithmetic units that perform logically identical operations on input data consisting of a plurality of bits according to a given operation mode to obtain output data consisting of a plurality of bits; an output data register which stores all bits of the output data of the arithmetic unit and has a bit width equal to the output data, and a predetermined first a first converter that outputs first converted data having a bit width equal to or less than that of the input according to a condition; and a converted data register that stores the output of the first converter;
a second converter that receives all bits of the conversion data register as input and outputs second conversion data having a bit width smaller than that of the input according to a predetermined second condition; and the output 1. An arithmetic device comprising means for collectively transmitting the outputs of the data register and the outputs to the outside.