JPS6387978U - - Google Patents
Info
- Publication number
- JPS6387978U JPS6387978U JP18271086U JP18271086U JPS6387978U JP S6387978 U JPS6387978 U JP S6387978U JP 18271086 U JP18271086 U JP 18271086U JP 18271086 U JP18271086 U JP 18271086U JP S6387978 U JPS6387978 U JP S6387978U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- converter
- output
- latch memory
- generates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 3
- 230000004044 response Effects 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Selective Calling Equipment (AREA)
Description
第1図はこの考案の一実施例の構成を示すブロ
ツク図、第2図は変換器の一例の具体的なブロツ
ク図、第3図は変換器の他の例の具体的なブロツ
ク図、第4図および第5図はそれぞれその動作を
示すフローチヤート、第6図および第7図はそれ
ぞれ従来例を示すブロツク図である。
21…第1の操作部、22…第2の操作部、2
3…第1の変換器、24…ラツチメモリ、25…
レベル比較器、26…第2の変換器、27…伝送
部。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention, FIG. 2 is a concrete block diagram of one example of the converter, FIG. 3 is a concrete block diagram of another example of the converter, and FIG. 4 and 5 are flowcharts showing the operation, and FIGS. 6 and 7 are block diagrams showing the conventional example, respectively. 21...first operation section, 22...second operation section, 2
3...First converter, 24...Latch memory, 25...
Level comparator, 26...second converter, 27...transmission section.
Claims (1)
操作量信号を発生する第2の操作部と、この第2
の操作部から出力される操作量信号をパラレルコ
ード信号に変換する第1の変換器と、この第1の
変換器の出力をトリガ信号に応答して記憶保持す
るラツチメモリと、前記第1の変換器の出力と前
記ラツチメモリの出力とを比較し両者が異なると
きにトリガ信号を発生して前記ラツチメモリへ与
えるレベル比較器と、前記第1の操作部の操作時
に前記第1の操作部から出力されるオンオフ操作
信号をシリアルコード信号に変換するとともに前
記第1の変換器から出力されるパラレルコード信
号を前記トリガ信号に応答してシリアルコード信
号に変換する第2の変換器と、この第2の変換器
から出力されるシリアルコード信号を電波、赤外
線、超音波等の発信信号に変換して放射する伝送
部とを備えた遠隔操作装置の送信器。 a first operation section that generates an on/off operation signal;
a second operating section that generates a manipulated variable signal;
a first converter that converts a manipulated variable signal output from the operating section of the converter into a parallel code signal; a latch memory that stores and holds the output of the first converter in response to a trigger signal; and a latch memory that stores and holds the output of the first converter in response to a trigger signal; a level comparator that compares the output of the device and the output of the latch memory and generates a trigger signal when the two differ and supplies it to the latch memory; a second converter for converting an on-off operation signal into a serial code signal and converting a parallel code signal output from the first converter into a serial code signal in response to the trigger signal; A transmitter for a remote control device that includes a transmission section that converts a serial code signal output from a converter into a transmission signal such as radio waves, infrared rays, or ultrasonic waves and emits the signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18271086U JPS6387978U (en) | 1986-11-26 | 1986-11-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18271086U JPS6387978U (en) | 1986-11-26 | 1986-11-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6387978U true JPS6387978U (en) | 1988-06-08 |
Family
ID=31128762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18271086U Pending JPS6387978U (en) | 1986-11-26 | 1986-11-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6387978U (en) |
-
1986
- 1986-11-26 JP JP18271086U patent/JPS6387978U/ja active Pending
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