JPS6387660A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To stably control a phase locked loop (PLL) by reproducing a signal having a specific frequency different from frequencies of the other signals in a recording signal to measure its period and controlling the PLL in accordance with the measured value. CONSTITUTION:A digitally modulated information signal and a clock are outputted by a PLL 17 from the reproduced signal reproduced from a recorded recording medium on which the area where the digitally modulated information signal is recorded and the area where a specific signal in a frequency area different from that of the digitally modulated information signal is recorded are provided on each track independently of each other. Meanwhile, the specific signal has the frequency selected and taken out and its period is measured. This measured value is converted to a signal having a period corresponding to this value after being held, and this period is compared with the period of the output clock of the PLL 17 by a control means 15, and it is converted to such control signal that both periods have a certain rate, and this signal is supplied to the PLL 17. Thus, the measured value of the period of the specific signal is held to stably control the PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal reproducing apparatus, and more particularly to a reproducing apparatus capable of reproducing a recorded edge digital signal of a recorded magnetic tape at an arbitrary speed ratio using a rotary head.

2. Description of the Related Art Digital signal recording and reproducing apparatuses have been known that record digitally modulated information signals (for example, pulse code modulated digital audio signals) on a magnetic tape using a rotating head and reproduce the recorded information. During playback, the playback signal is waveform-equalized and then phase-locked.
A pit clock is generated by looping (PL), and the original digital signal is demodulated from the reproduced signal using this pit clock. For this reason, the frequency characteristics of the waveform equalization circuit and the lock range and capture range of the PLL are related to the bit rate of the reproduced signal, so the relative linear velocity (hereinafter referred to as relative velocity) between the rotating head and the running speed of the magnetic tape is
It is necessary to detect the relative speed and control the relative speed to be constant based on the detection result, or to variably control the relative speed so that the bit rate of the reproduced signal is constant. Also,
In order to search for a recorded signal in a short time, even during high-speed playback when playing back recorded edge digital signals from a magnetic tape whose running speed is faster than that during recording, the signal is moved in the same direction (in the same direction as during recording). Since the tape is run in the opposite direction (direction) or in the opposite direction, it is necessary to detect and control the above-mentioned relative speed.

For this reason, the tape speed has traditionally been detected by generating pulses corresponding to the number of rotations of a rotary encoder that is in contact with the magnetic tape while the tape is running, and measuring this pulse. ■Parts accuracy control is required; ■Encoder tends to slip during high-speed feeding, causing errors in speed detection. ■ Errors occur in speed detection due to aging of bearings due to wear. ■Since an encoder is added to the driving system, there are drawbacks such as affecting driving performance. It is also possible to form a linear track other than the track recorded by the rotating head and record and reproduce speed detection signals there, but this requires a fixed head and a recording/reproducing circuit dedicated to the linear track, which reduces the number of parts. This will increase the cost. Moreover, all of the above methods detect the running speed of the magnetic tape, and do not detect the relative speed.

For this reason, a method of detecting the relative velocity from the reproduction signal of the rotary head was proposed, for example, in Japanese Patent Laid-Open No. 60-231952. This method calculates the tape speed based on the number of tracks that the rotary head traverses during one rotation during high-speed feeding, and controls the speed of the single motor accordingly to keep the relative speed constant.

According to this method, when recording and reproducing using two rotary heads with different azimuth angles, the recording track is reproduced from the track (main track) recorded by the rotary head having the same azimuth angle as the rotary head during reproduction. Rebirth of time R
Since the F signal level and the reproduced RF signal level when a track recorded by a rotating head with a different azimuth angle (reverse track) is significantly different depending on the presence or absence of the azimuth loss effect, it is possible to scan across the track. In this case, the number of tracks traversed is counted by utilizing changes in the envelope of the reproduced RF signal, and the relative speed is detected based on the number of tracks crossed.

Problems to be Solved by the Invention However, in the above-mentioned conventional relative velocity detection method, the envelope of the reproduced RF signal itself tends to have undulations during high-speed feeding.
In addition, since the output level fluctuates due to fluctuations in tape speed, the threshold settings for detecting changes in the envelope of the reproduced RF signal and shaping the waveform in order to count the number of traversed tracks become extremely delicate. There was a problem above.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a digital signal reproducing device capable of detecting relative speed.

Means for Solving the Problems Digital Signal Re/4. The device includes means for frequency selecting a signal in a specific frequency range from a reproduced signal, a measuring means for opening the period of the specific signal, a holding means for holding the measured value, and a signal having a period corresponding to the held value. -6" It consists of a control means for controlling the phase locked loop.

From a recorded recording medium in which an area in which a digitally modulated information signal is recorded and an area in which a specific signal in a frequency range different from that of the digitally modulated information signal is provided separately in each track. The reproduced signal is outputted as a digitally modulated information signal and a clock by a phase-locked loop, while a frequency selection means selects and extracts the frequency of the above-mentioned specific signal, and its period is set to the open side. Measured by means.

After this measured value is held by the holding means, it is converted into a signal with a period corresponding to the value by the signal generating means, and is further compared with the period of the output clock of the phase locked loop by the control means, so that both periods are constant. is converted into a control signal with a ratio of , and then supplied to the phase-locked loop.

Therefore, even during a period when no reproduced signal is obtained, the holding means holds the measured value of the period of the specific signal until the next measured value arrives, so that the phase locked loop is always controlled.

Embodiment FIG. 1 shows a block diagram of an embodiment of a digital signal reproducing apparatus according to the present invention. In the figure, a magnetic tape 2 pulled out from inside a cassette 1 is placed at a predetermined angle (for example, 90 mm) against a head drum 3 having a diameter of 30 am+ during recording and reproduction.
It is spliced and wound over a distance of This magnetic tape 2 has
Two rotary heads having different azimuth angles alternately record digital audio signals by sequentially forming tracks that are inclined with respect to the longitudinal direction of the tape.

On this inclined track, for example, a total of 196 blocks of signals are recorded per track, with 288 bits as one block, of which the above-mentioned digital audio signal (for example, sampling frequency 48 kHz) is recorded.

The quantization bit number (16 bits) is recorded in the center of each 128-block track, for example, along with parity and synchronization bits, and the remaining 68 blocks before and after the digital audio signal recording area of each track are each recorded with a margin. , subcode, auto-tracking code, etc. are recorded.

Here, the transmission frequency fch is, for example, 9.408 MHz
The signals recorded on each track are (1/2) f ch, (1/2) except for the auto tracking code.
6)・fch etc., whereas the first and second synchronization signals recorded as auto tracking codes are fch etc.
/18 and fch/12. The erase signal is f ah/
6. The frequency of the pilot signal is selected to be f ch/72. That is, in the area where the auto-tracking code is recorded (the so-called ATF area), a particularly low-frequency pilot signal that has a significantly different frequency from other signals and has little azimuth loss effect is recorded.
This pilot signal can be reproduced by either rotating head.

On the other hand, looking at the bit rate during high-speed tape feeding, for example, if the rotation of the head drum 3 is maintained at the same number of rotations as during recording, but the tape running speed during playback is made different from that during recording, Assuming that the traveling speed is sufficiently smaller than the linear velocity (circumferential velocity) of the rotary head and ignoring the azimuth loss effect, the bit rate change rate r3 can be expressed by the following equation.

(However, N: Tape speed ratio, VNP: Tape running speed during normal playback, VH: Circumferential speed of rotating head, θni racking angle) In equation (1), tape speed ratio N is the tape running direction. It takes a negative value when it is in the forward direction, and a positive value when it goes in the reverse direction.

Now, the tape running speed is set to 200 times the speed (that is, N-±
200) and VN p -8,15 shoes/s.

VH = 3.133m/s, θ-6°22'59''
Then, the bit rate change rate r3 is 1 from equation (1).
It will be about ±0.52. As mentioned above, the pilot signal is a recording signal with a frequency as low as ++ -10-, and has a frequency 1/4 times that of the first synchronizing signal, which has the next lowest frequency, so it can be recorded at a tape running speed of about 200 times or less. If so, it is possible to identify the pilot signal by observing the reproduced signal.

Returning to FIG. 1 again, in this embodiment, the number of revolutions of the head drum 3 is set to the same number of revolutions as that during recording (for example, 20
00rDI) and performs high-speed playback.

The reproduction signal reproduced from the recorded magnetic tape 2 by the two rotary heads A and B mounted 180 degrees facing each other on the rotating surface of the head drum 30 is supplied to the low-pass filter 5 through the head amplifier 4, where it is After only the frequency signal is extracted, it is converted into a rectangular wave by the comparator 6 and supplied to the counter 7. On the other hand, a drum pulse generator 8 extracts a drum pulse having a period corresponding to the rotational speed of the head drum 3 and supplies it to an ATF gate signal generator 9 . Since the ATF area is reproduced at a constant timing when the rotation speed of the head drum 3 is constant, a gate signal indicating that the area is approximately in the ATF area is extracted from the ATF gate signal generator 9 and supplied to the counter 7. be done. Thereby, the counter 7 can visually measure the reproduced signal only during the input period of this gate signal (within the ATF region) and can detect the pilot signal with high reliability.

The counter 7 is supplied with a pulse train of frequency fch (here, 9.408 MHz) extracted from the crystal oscillator 10 as a clock, counts the reproduced signal from the comparator 6 as R1, and also outputs the gate signal from the ATF gate signal generator 9. This clock is counted only during the incoming period of the signal. During normal reproduction, this δ1 value Np per period of the reproduced pilot signal is ``72'' when calculated by 84 using the above clock.
], but the count value Ns per cycle of the reproduced pilot signal during high-speed reproduction is 1-0.6≦rB≦1 when the rate of change of the bit rate r8 at 200 times speed culm is 1-0.6≦rB≦1 when traveling in the forward direction. (2) When driving in the reverse direction, 1≦r3≦1+0.6 (If considered as 33, when driving in the forward direction, approximately 72≦Ns≦180 (=7210.4) (
4), and when traveling in the opposite direction, approximately 45 (=72/1.6)≦Ns≦72 6).

The pilot signal selection circuit 11 assumes that a signal whose period is within the range of Ns in which the count value of the counter 7 is expressed by equation (4) or (5) is a pilot signal, and stores the count value in the register 12. Supply and hold. The holding period of the register 12 is the period until the next count value arrives. In this case, based on the signal from the system controller 13, the pilot signal selection circuit 11 limits the count value of the counter 7 to be within the range of the "g value Ns" shown by equation (4) during high-speed regeneration in forward direction. Furthermore, during high-speed regeneration when traveling in the opposite direction, the reliability of pilot signal detection is increased by limiting the value to be within the range of the value Ns shown by equation (5). 1 ATF
Since 10 or more clocks are recorded in the area, the pilot signal selection circuit 11 selects the same period several times (
For example, when detected four times), the reliability of detection can be further improved by regarding it as a pilot signal.

The value held in the register 12 is the held value periodic signal generator 1.
4, where it is converted into a signal with a period of the held value based on the clock pulse from the crystal oscillator 10, and then
The signal is supplied to a constant ratio PLL control circuit 15. On the other hand, P.L.
The output signal frequency of L17 is the frequency f during normal reproduction.
ch (here, 9.408 MH2), and changes in accordance with the relative speed during high-speed playback, and changes at the same rate as the rate of change rB of the bit rate. Therefore, as long as the PLL 17 is locked during both normal playback and high-speed playback, the PLL
The period ratio between the output signal of the LL 17 and the signal having the period of the held value from the held value periodic signal generator 14 is a substantially constant ratio of 1 to 2 or very close to it.

Therefore, the constant ratio PLL control circuit 15
The period of 72 clocks of the output signal of the L17 is compared with the period of the output signal of the held value period signal generator 14, and a control signal corresponding to the period difference obtained by the comparison is supplied to the PLL 17 for control. For example, if the period of the signal with the period of the held value is significantly shorter than the period of 72 clocks of the output signal of PLLI 7, the output signal frequency of PLL 17 is assumed to be low, and the output signal frequency of PLL 17 is increased. In the opposite case, it is assumed that the output signal frequency of the PLL 17 is high, and the output signal frequency of the PLL 17 is controlled to be low.

On the other hand, the reproduced digital signal taken out from the head amplifier 4 is waveform-equalized by the waveform equalization circuit 16 and then passed through the level comparator 20 in the PLL 17 having the configuration shown in FIG.
The signal is supplied to the data latch 21 and the phase comparator 22 after being converted into a digital signal. The phase comparator 22 generates an error voltage according to the phase difference between the reproduced digital signal from the level comparator 20 and the output signal from the voltage controlled oscillator (VCO) 24, and passes it through a low-pass filter 23 to the VCO 24 as a control voltage. The oscillation frequency is variably controlled. The output signal of the VC024 is also output as a clock to the digital system, and is also applied to the data latch 21 as a latch pulse to latch the reproduced digital signal. This data latch 2
The output signal No. 1 is outputted to the digital system as reproduced digital data.

The clock frequency of the above PLL 17 is 9.0 during normal playback.
The transmission frequency fch is 408 MHz, but during high-speed reproduction, the transmission frequency fch is proportional to the rate of change r3 of the bit rate, as described above. Especially when playing at high speed, P L
Since the lock range of L and 17 is set wide, it may lock at the harmonic of the transmission frequency fch, or the PL
The input signal of L17 and the output signal of VC024 may lock at a certain frequency ratio, and in the case of such a pseudo-lock operation, normal data acquisition becomes impossible.

Further, the recorded magnetic tape 2 is placed on the head drum 3, for example, at 9.
While the rotary heads A and B travel while being spliced and wound within the angular range of 0', the rotary heads A and B are mounted facing the head drum 3 at 180° as shown in FIG. The rotary head A or B scans the magnetic tape 2 to obtain a reproduction signal every 90° rotation period of the head drum 3, and the reproduction signal is in a burst form. That is, during the 180° rotation period of the head drum 3, there is a 90° rotation period in which neither the rotary heads A nor B are slidingly scanning the magnetic tape 2, and no reproduction signal is obtained during this 90'' rotation period. Therefore, the phase comparison information in the PLL 17 is lost, and the oscillation frequency of the VCO 24 deviates from the playback bit rate, or the oscillation frequency of the VC024 deviates significantly due to the phase comparison information due to noise.As a result, the next playback signal is input. When the PLL17
It takes a while for it to lock.

In order to solve these problems, in this embodiment, the PLL 17 is controlled in the following manner.

During high-speed playback, the period of the pilot signal during normal playback (this is obtained by counting the output signal of the crystal oscillator 10 by "72") is significantly different from the period of the signal from the held value period signal generator 14, so it is constant. The ratio PLL control circuit 15 detects this and changes the frequency characteristic of the waveform equalization circuit 16 to a predetermined characteristic, and also switches the lock range and capture range of the PLL 17 to be wider than during normal reproduction using known means. Note that the system controller 13 may change the frequency characteristics of the waveform equalization circuit 16 and switch the lock range or capture range of the PLL 17 based on input of a high-speed reproduction instruction.

In addition, when the PLL 17 is in a pseudo lock operation, the period difference between the two human input signals of the constant ratio PLL control circuit 15 is significantly different, so the output error voltage of the phase comparator 22 in the PLL 17 shown in FIG. A control signal that forcibly sets the signal to a high level or [I- level for a certain period of time is supplied from the fixed ratio PLL control circuit 15 to the phase comparator 22, thereby adjusting the oscillation frequency of the VCO 24 so that the first period difference becomes near zero. control.

In this way, the digital signal can be read stably even during high-speed reciprocation, and the PLL 17 can be stably controlled even when the reproduced signal is obtained intermittently.

By the way, during normal playback or special playback (such as skip playback) in which the bit rate of the playback signal has little change from normal playback, the counter 7 for the playback pilot signal - period
The count value Np is "72j" as described above, and this is known, so during these reproductions, the system controller 13 fixes the value held in the register 12 to "72".

Thereby, the PLL 17 can be controlled.

In this case, the PLL 17 can be stably controlled in the same manner as described above regardless of the pilot signal detection ability.

In addition, in counting the pilot signal, the count value Ns within the range of equation (5) has a resolution of only one clock of the crystal oscillator 10.
Either by increasing the repetition frequency of the 0 output pulse (clock), or by maintaining the period of several clocks and controlling it using this, since the pilot signal is recorded for example 10 clocks in one ATF area. Accuracy can be increased. For example, if the output clock frequency of the crystal oscillator 10 is increased to 4@, the number of words per period of the pilot signal during normal reproduction is r288J (=
4x72), and the resolution per clock of the output clock of the crystal oscillator 10 increases. Also, if we decide to count the period of 4 clocks of the pilot signal, similarly t
' A count value of 288.1 can be obtained and the accuracy can be improved.

In addition, the waveform equalization circuit 16 is often configured using a delay line, and the delay line is COD.
(Charge coupled device)
As is well known, the delay time is determined by the clock frequency (sampling period) and the number of CCD stages.
The configuration may be such that control is performed using the generation frequency of the VCO 24 of the PLLI 7 whose operation can be switched depending on the value of the output of the PLLI 5.

−1υ − Effects of the Invention As described above, according to the present invention, a signal of a specific frequency that is different in frequency from other signals in a recorded signal such as a pilot signal is reproduced, its period is measured, and its value is calculated. Since we decided to hold this value and control the PLL using that value, compared to conventional devices that detect level changes in the envelope of the reproduced signal,
@There is no problem in setting the value, and accurate relative speed can be detected.
In addition, since the measured value is held until the next measured value is obtained, the PLL can be controlled at all times even during periods when the regenerated pilot signal is not obtained, and until the PLL locks when the next regenerated signal is input. This device has the following features: it can significantly shorten the time required, it can always perform stable PLL control, and it can stably read the reproduced digital signal even during high-speed reproduction.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the device of the present invention;
FIG. 2 shows a block system diagram of an embodiment of the main part of the block system shown in FIG. 1 U-2... recorded magnetic tape, 3... head drum, 7
...Counter, 9...ATF gate signal generator, 1
0... Crystal oscillator, 11... Pilot signal selection circuit, 12... Register, 13... System controller, 14... Hold value cycle signal generator, 15... Fixed ratio PLL control circuit, 16 ... Waveform equalization circuit, 17.
...Phase Locked Loop (PLL), 22...
- Phase comparator, 24...voltage controlled oscillator (VCO).

Claims (2)

[Claims] (1) A recorded device in which each track has a separate area in which a digitally modulated information signal is recorded and a specific signal in a frequency range different from that of the digitally modulated information signal. A digital signal reproducing device that reproduces a recorded signal on a recording medium and outputs a clock and the digitally modulated information signal from the reproduced signal using a phase-locked loop. a means for selecting; a measuring means for measuring the period of the specific frequency-selected signal; a holding means for holding the output measured value of the measuring means for a period until the next measured value is input; and the holding means. a signal generating means for generating a signal with a period corresponding to the measured value held by the signal generating means; and an output signal of the signal generating means and the phase locked signal.
Compare both periods of the output clock of the loop, and always set the phase locked clock so that the two periods have a constant ratio.
1. A digital signal reproducing device comprising: control means for controlling a loop. (2) During normal playback and during special playback where the bit rate of the playback signal is little different from that during normal playback, the holding means replaces the measured output value of the measuring means with a previously known periodicity value of the specific signal. 2. The digital signal reproducing apparatus according to claim 1, further comprising a switching means for switching to fix and hold the digital signal.