JPS6387015A - Delay pulse generating circuit - Google Patents

Abstract

PURPOSE:To easily control the phase difference by providing plural delay pulse generating basic circuits that can set optionally the delay value of an input reference pulse and supplying a delay value selecting signal and an address signal from outside for selection of those basic circuits. CONSTITUTION:An input reference pulse 1 is supplied to the delay pulse generating basic circuits 10i (i = 0-n) via a drive circuit 2. The circuit 10i contains a delay element 4, a selection circuit 5 and a holding circuit 8 and selects one of outputs 4-1 of the element 4. Then addresses are produced 14 by clock signals 17 and 18 and an address clock is selected 12 to supply clock signals 11-19 to the circuit 10i. A selection signal is produced 9 by the signal 17 and supplied to holding circuits 8-24 respectively. The circuits 8-24 receive address clocks 11-19 and deliver a selection signal 7 to select one of delay outputs 4-1 and to obtain pulses 6-22 delayed by the desired value. Thus it is possible to easily control the phase difference between a reference pulse and a delay pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay pulse generation circuit, and particularly to a delay pulse generation circuit. The present invention relates to a delay Noculus generation circuit that allows easy phase adjustment of pulses.

[Conventional technology]

As shown in FIG. 3, the conventional delay pulse generation circuit includes terminals 35 corresponding to each output terminal 34 of a delay element 33, and adjustment jumpers for electrically connecting these terminals 34 and 35. It has a terminal 36.

A desired delayed pulse output is obtained from the output terminal of the delay element 33 by attaching and detaching the UIJ to and from the jumper terminal 36,
A plurality of these basic delayed pulse generation circuits were incorporated and mounted on a printed circuit board. In the figure, 31 is a reference input pulse, and 32 is a drive circuit.

37 is an output circuit.

[Problem that the invention seeks to solve]

Said delay! The pulse generation circuit is generally built into a board (hereinafter referred to as a package), and this package is packed together with other logic control packages. Recently, a three-dimensional mounting configuration has been adopted so that the device is mounted on a cage frame having a board and provides a function as a kind of control device.

In such a case, when setting the phase difference between the delayed pulse signal and the reference pulse in the delay pulse generation circuit used in this control device, always check that the delay pulse generation circuit is installed. Remove the current cage from the cage frame, reset the delayed pulse output terminal of the delay element mounted on this package, and then attach it to the cage frame again to connect the reference input pulse and the delayed pulse.
? The phase difference between the pulses is checked, and if this phase difference does not satisfy the desired value, the above operation is performed again. This type of work is generally required to match the phase difference between the clock signal of the device and the clock signal of other devices, and is especially necessary when the device is shipped to the user and adjustments are made on site, or when this circuit is adjusted. If the package that is equipped with the system breaks down, it becomes a special task to replace it with a new maintenance package, and the disadvantage is that it takes a considerable amount of time to adjust the delay phase difference.

The present invention solves these drawbacks of the conventional circuits and provides a delay pulse generation circuit that can easily generate a delay pulse having a desired phase difference and requires only a short adjustment time.

[Means for solving problems]

The delay pulse generation circuit of the present invention includes a delay element which uses an input reference pulse as an input signal and can select a desired delay time, and a pulse obtained from each delay time selection output terminal of the delay element as an input signal. a plurality of basic delay/elusion generation circuits comprising a selection circuit that selects and outputs one of the selection circuits and a holding circuit that temporarily stores the selection signal to the selection circuit; and a selection signal that is an input signal to each of the holding circuits. A selection signal generation circuit (the content is a binary counting circuit) that generates the delay signal ? an address generation circuit that generates an address for logically addressing each pulse generation basic circuit;
The device includes an address clock selection circuit which takes the output signal of the address generation circuit as an input signal and selectively supplies a clock signal to the holding circuit.

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention.

In FIG. 1, 1 is an input reference pulse, 2 is a drive circuit that receives the applied reference pulse 1 and supplies it to the delay element 4;
3 is the output signal of the drive circuit 2, 4 is a delay element capable of extracting a pulse signal with an arbitrary delay time, 4-1 is a delayed pulse signal line from the delayed pulse output terminal of the delay element 4, and 5 is a signal line 4-1 as an input signal, each delay/? inputted by the switching selection signal 7. 6 is the output delay pulse signal of the selection circuit 5; 8 is a holding circuit that temporarily stores the selection signal 7; 9
10 is an output signal of the binary counting circuit 9; 11 is a clock signal that causes the holding circuit 8 to perform a holding function; 12 is an address clock selection circuit; 14 is a delay element 42 selection circuit 5.
The basic delay/loss generation circuit 0 ('1
00) to delay pulse generation basic circuit n (10n
) is an address generation circuit that calculates a one-to-one logical correspondence and generates an address for address assignment.
It is composed of a binary counting circuit that operates in accordance with a clock signal 18. 13 is an output signal of the address generation circuit 14, which serves as an address signal.

17 is a clock signal which is generated later than the clock signal 18 and is supplied to the binary counting circuit 9 and also to the delay circuit 1.
6 is also supplied. 15 is the output signal of the delay circuit 16;
The clock signal exhibits a phase lag with respect to the clock signal 17.

20.20-1.21, 22.23 and 24 are the delay elements 4. Delay pulse signal line 4-19 selection circuit 5° output delay signal 69 corresponding to selection signal 7 and holding circuit 8,
These constitute a delay Noculus generation basic circuit n (1on).

Therefore, when address assignment is performed using the address generation circuit 14 and the address clock selection circuit 12.

Delay address O Noculus generation basic circuit 0 (100)
, the address n is made to correspond to the delay/main pulse generation basic circuit n
(Ion).

The phase adjustment work of this embodiment will be explained below using the time chart of FIG. Note that in FIG. 2, in order to simplify the explanation, it is assumed that four output terminals are provided per delay element.

In Figure 2, (1) is the input reference pulse corresponding to 1 in Figure 1, and (4-1) is the output terminal of the delay element corresponding to 4-1 and 20-1 in Figure 1 over time. shows the delayed pulse obtained from . In addition.

In the symbol tij, i is the output terminal number of the delay element.

j indicates a logical address number assigned to the delayed pulse generation basic circuit. (18) is a clock signal to the address generation circuit (binary counting circuit) 14 corresponding to 18 in FIG. 1, and (13) indicates an output signal of the address generation circuit 14. Based on this signal, the address clock selection circuit 12 shown in FIG. 1 determines which delay clock generation basic circuits 0 to n will perform the delay clock phase adjustment. The time domain of TAO shown in the front (bottom) of the figure is based on the clock signal (
18), the output (13) of the address generation circuit 14 becomes 'OO', indicating that the basic circuit corresponding to address 0 is selected.

(17) corresponds to the clock signal 17 in FIG. 1 and is applied after applying the clock signal (18). The selection circuit 5 provided in each basic circuit according to this clock signal (17)
Generate a selection signal to. That is.

Each delay element has four output terminals, and these are switched by a 2-bit selection signal.

(10) shows the output signal 10 of the binary counting circuit 9 of FIG. 1, which is a selection signal for selecting the output terminal of the delay element described above. (15) corresponds to the clock signal 15 in FIG. 1, and is a clock signal delayed in phase from the clock signal (17) by the delay circuit 16. This clock signal (15) serves as a clock to the holding circuit 8 included in the delayed pulse generation basic circuit selected by the clock address selection circuit 12. Therefore, in the time domain of TAO, the clock signal (11) corresponding to the clock signal 11 in FIG. 1 is output, and the output signal (10) of the binary counting circuit input to the holding circuit 8 in FIG. (7) is further output.

Further, in the time domain of Too, the selection circuit 5 selects the output signal of 100, and in the domain of +TiO, selects the output/mother pulse of tlo. In Figure 2, (6) shows the delayed Noculus signal after these selections, and the previous signal (
It is shown that phase adjustment was observed between 1) and 2, and the desired adjustment was obtained in the region of exactly T10. Therefore, the adjustment in the basic delay node generation circuit for address 0 has been completed, and the 9th delay node corresponding to address 1 is 9th.
Now we move on to adjusting the basic pulse generation circuit.

Instead, a clock signal (18) is applied to change the information in the address generation circuit 14. As a result, the clock signal (11) is stopped when the adjustment is completed, and the selection signal of the delay element output terminal for address 0 remains held.

By repeating this adjustment up to the basic delay and pulse generation circuit corresponding to address n, the adjustment of the basic delay and pulse generation circuit for all delay elements is completed.

The time domain of TAn in FIG. 2 shows the state at the time of adjustment of the n-th address, and shows an example in which the desired phase adjustment is completed in the region of +'rtn. Note that the clock signal (19), selection signal (23), and output signal (2
2) shows the output states of 19, 23 and 22 in FIG. 1, respectively.

In the above embodiment, the input reference pulse 1 is input to the drive circuit 2.
The circuit output 3 is used as the input signal of the delay element 4, but the input reference pulse 1 may be subjected to the same processing as in the above drive circuit outside of FIG. Since the circuit output 3 of the circuit is considered to be functionally the same as the input reference Noculus 1, it is possible to omit the drive circuit 2 in FIG. 2 and input the input reference pulse 1 directly to the delay element 4. good.

〔Effect of the invention〕

From the above explanation, 1. The present invention allows the phase difference between the reference pulse and the delayed pulse to be easily adjusted, and the disadvantages of the conventional configuration have been overcome. The delay and master pulse can be set to a desired phase value without requiring operations such as attaching and detaching the IJ ring, which has the effect of greatly shortening the adjustment time.

[Brief explanation of the drawing]

FIG. 1 shows a configuration diagram of an embodiment of the delayed pulse generation circuit of the present invention, FIG. 2 shows a time chart accompanying phase adjustment of delayed pulses, and FIG. 3 shows a configuration diagram of an example of a conventional delayed pulse generation circuit. . Explanation of symbols: 1 is input reference Noculus, 2 is drive circuit, 4
．． 20 is a delay element, 5.26 is a selection circuit, 6°22 is an output delay signal, 7.23 is a selection signal, 8.24 is a holding circuit, 9 is a selection signal generation circuit (binary counting circuit), 100
10n is a delay pulse generation basic circuit, 11.degree. 19 is a clock signal, 12 is an address clock selection circuit, 14 is an address generation circuit, 16 is a delay circuit, and 17 and 18 are clock signals, respectively.

Claims (1)

[Claims] 1. A delay element, each of which uses an input reference pulse as an input signal and can select a desired delay time. A pulse obtained from each delay pulse output terminal of the delay element is used as an input signal, and one of the input signals is selected. a plurality of basic delay pulse generation circuits comprising a selection circuit to output and a holding circuit that temporarily stores a selection signal to the selection circuit; a selection signal generation circuit that generates a selection signal to be an input signal to each of the holding circuits; An address generation circuit that generates addresses for logically addressing each of the delayed pulse generation basic circuits, and an address clock selection that uses the output signal of the address generation circuit as an input signal and selectively supplies a clock signal to the holding circuit. A delayed pulse generation circuit comprising a circuit.