JPS6386928A - Encoding/decoding circuit - Google Patents

Abstract

PURPOSE:To miniaturize an apparatus by providing a decoding circuit having a means for multiplying a syndrome generated by a syndrome generating means, by a constant, and a circuit for changing its constant in case of encoding, and using multiplex a multiplying means. CONSTITUTION:At the time of executing double error correction and encoding, a syndrome generating circuit is operated by setting input data in-3-in to '0'. Therefore, a clear input of a register which has latched a receiving word J is dropped to L during in-3-in. Accordingly, when in-3=0 is being inputted, a syndrome SI=(S0, S1, S2 and S3) generated by receiving words of il-in-4 is generated. At the time of executing double error correction and encoding, when syndromes SI-SIV are drived by a syndrome generating circuit, the syndrome and a double error correction and encoding constant are multiplied in order to generate parities in-3-in. In this way, the encoding/decoding processing is allowed to flow like a pipeline, a high processing speed is maintained, and also, it is realized to make the correction capacity and the code length variable, and the circuit scale can be made small by common use of circuits and multiplexing of the circuit of the encoding/decoding circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to the field of error correction, and particularly to a BCH code encoding Φ decoding circuit.

[Prior Art] Conventionally, BCH codes have been encoded by a division circuit using a generator polynomial, and decoded by a circuit using various algorithms (Petersonno method, Berlecumbe Matsusei's method, etc.).

#Ossification and decoding used different circuits. Also,
When processing using multiple circuits using microprogramming, etc., it was necessary to make detailed changes in the processing for encoding and decoding. Therefore, encoding and decoding can be performed on the same board or
In the case of using a chip, the amount of circuitry or ROM capacity increases. Furthermore, when pipeline processing is performed to increase processing speed, there is a drawback that the circuit scale increases. As a result, there is a disadvantage in that the size of equipment such as optical disks equipped with these devices becomes larger.

[Objective] In order to eliminate the drawbacks of the above-mentioned conventional example, the present invention realizes an encoding circuit by only changing a part of the decoding circuit, and
The purpose is to perform pipeline processing using only two multiplication circuits and a division circuit.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

The present applicant has proposed an error correction device in Japanese Patent Application No. 60-79674. This example relates to an encoding/decoding circuit for an error correction device that can be used for optical disks such as DAT.

First, consider performing encoding using the processing shown in equations (1) to (8) below.

In terms of procedure, as soon as syndromes 31 to S Parity is generated. Therefore, encoding consists of one multiplication circuit, a syndrome generation circuit that serially outputs Sn=SIV, a circuit that serially outputs an encoding constant in synchronization with Sn=SIV, and a 4-clock cycle.
This is realized by the configuration of the block diagram shown in FIG. 1 using EXOR circuits for each k (each block will be explained in detail).
.

Next, consider performing decoding using the processes shown in equations (11) to (20). At first, the syndrome S is multiplied by code length correction constants α-n to α-37, so it can be realized with the same configuration as encoding (however, the values of the constants are different).

), and a block diagram for carrying out the schemes (11) to (20) is shown in FIG. Here, the pattern generation circuit is 4cl
If it is an EXOR circuit for each ock, this circuit can also be shared with the encoder.

The process up to this point is as shown in the patent application (7) filed on September 30, 1985, and since the processing of each block flows in a pipeline manner and each process is a simple process, a high processing speed can be achieved. Here, consider reducing the three multiplication circuits used to one.

AO2(AO+A1)-1ty) divide it'
) If the Tameni division circuit shown in patent application (5) filed on September 30, 1985 is used, it will have a built-in multiplier and the 4c
It can be seen that the multiplication for lock is performed.

Since it operates with the syndrome generation circuit eso-S3 at a cycle of 4 CIOCk, 4 clocks is considered to be the basic cycle.

Therefore, the remaining multiplications in equations (11) to (20) are
A□eA2 and y * X 14 no 2 used in the division circuit
This is a multiplication for the clock. Since code length correction is performed for each code table, it is not performed for each code word.

Since the operation of multiplying α-n to α-3n takes 3 clocks, 1 clock remains. Then, AO*A2 is performed, and the multiplication by y-x14 is not performed only when code length correction is performed. Although an error pattern is not generated for the code word in this case, there is no problem if the code word is made to be the parity part.

Therefore, each block that can be easily configured by configuring the encoding/decoding circuit as shown in FIG. 3 can be simplified by configuring it as follows.

[Syndrome Generation Circuit] When using one multiplier as shown in FIG. 3, it is necessary to serially output from the syndrome generation circuit using a pass line. Therefore, the syndrome generation circuit shown in patent application (1) filed on September 30, 1985 is used.

In the case of encoding, parity is good, but in case parity is not matched, do the following.

In double error correction encoding, Sl to S shown in equation (7)
To realize a TV, input data 1n-3 to int-
The syndrome generation circuit can be operated as 0. To do this, the clear input of the register that latches the received ffM J is set between 1n-3 and 1in.
When inputting n-3=O, the syndrome SI=[SO
, 31°S2, 53] are generated. Also, 1n-2=
When 0 is input, the syndrome generation circuit continues to operate, so that Sn=[SO, α-3l.

α2・52. α3·33] is generated. Similarly 1n-
When inputting 1=0, 1n=0, Sm=[SO, α2・
Sl, α4・32. α8・S3].

5IV=[SO, α3-3l, α6-32. α9・S3
] is generated.

Similarly, when there is a single error, when 1n-1=0 is input, SI=[30
, 311 is inputting the following c7) i n = 0, 5u = (so, α Sll is generated. Therefore, the encoding syndrome generation circuit controls 5PCL of the decoding syndrome generation circuit. The timing is shown in Figure 4.

[Constant output circuit] In double error correction encoding, when the syndrome S~S is found in the syndrome generation circuit, the parity 1n
It is necessary to multiply the syndrome by a double error correction coding constant to generate -3~in. Since the encoding constant is fixed as one in the case of single error correction and in the case of double error correction as shown in equations (7) and (8), the corresponding constant is added to the multiplier in synchronization with SI~S■. The block diagram of the circuit which outputs the output signal is shown in FIG.

Pct...16 is an output obtained by shifting Pct by a shift register, thereby Pcl...16
The output of is assigned according to equation (7). FIG. 5 shows a circuit that outputs the double error correction coding constant output assigned as described above to the input bus line Y of the multiplier of BLocklO by EOW control. PCI...1
A double error correction encoding constant output circuit according to No. 6 can be realized as shown in FIG. This timing is shown in Figure 9. In the case of single error correction encoding, when syndrome S is generated, SCL becomes L, so PC may be Pct...8, which corresponds to 5I-5II. An encoding constant is assigned. In addition, in the case of single error correction encoding, S2
．． Since S3 has no meaning, 0 is output for 32°S3. As a result, the single error correction coding setting circuit also has two
It can be provided as shown in FIGS. 7 and 8 using the same principle and configuration as the heavy error correction encoding circuit. The timing is shown in FIG.

The code length correction constant is generated in accordance with the block diagram of FIG. 10 in the same way as the encoding constant. 1. α-n to α-3n are
If n is a fixed length, it can be constructed by an OR circuit as shown in Figure 6.8.

Encoding/decoding is given by D, correction ability is given by T, and EOW (
Encoding, T=2), KO3 (encoding, T=1), HOE
(Decoding) operates according to the settings of T and D, and becomes H in cases other than the settings.

[Pattern generation circuit] In order to realize equation (19), first, the first
Clear the output from the register in Figure 2, and at the same time
Extract KO from D by KGT and put it in the register,
Next is the output from the selector.

Extract the output from ZS by XGT to x254・A02, that is, AO2 (AO+AI)-1, and EXOH it with the output of the register (Others are EXOHed as O)
This generates an error pattern. This is common to single errors and double errors. The timing is shown in FIG.

However, PCL=H at the time of decoding.

Next is the case of parity generation, which is performed at the time of encoding.In double error correction encoding, the value obtained by multiplying the syndrome SI~S■ by the encoding constant from 2 is output.
By setting POZ=XGT=H, KGT=L and applying the ZS output to the register output cleared by CKB6, and then EXOHing it until the register output is cleared again by CKB6, parity 1n-3 to in is sequentially generated.
The above operation is limited to the period when SI~S■ is output from Z, so the output of EP other than that is meaningless. Therefore, P
By setting CL to L, the output of EP is set to O. The situation is shown in FIG. 14, and the case of single error correction coding is shown in FIG. 15.

[K generation circuit] The K generation circuit 1 generates Sio code length corrected from equation (15).
It is a circuit that multiplies αi by the code length (formula (16)),
Involved only in decryption. Therefore, it can be realized with the same configuration as the syndrome generation circuit, but since there is no need to perform EXOH with the received word, the configuration is as shown in FIG. 19. 19th
Figure 20 shows a configuration in which the switch shown in the figure is 3-setate controlled and has a pass line control configuration like a syndrome generation circuit. SO does not need code length correction from equation (15), but 5l-33 has a code length It is necessary to correct the length to S1~S3'. Code length correction is performed by multiplying 31 to S3 by a code length correction constant. S1゛~S3'
is output in synchronization with SE, SO becomes SOo
By latching SO with CK3 and outputting with KE in order to match the timing of S1 to S3,
' are input to the generation circuit in this order. For this purpose, the output enable control signal REI of the latch for 3 is applied to KO~.
4 operates in opposition as in FIG. 4, but must remain open while S' is input at KE and SE.

The timing is shown in FIG. 21.The feature of this circuit is that, like the syndrome generation circuit, it can receive S'' of the pass line configuration and generate K with a small circuit scale.

As a result, in K, 3 is outputted to KO- every four cycles.

[Comparison circuit] A block diagram of the comparison circuit is shown in FIG.

Check whether AO・A2 and A12 match by a comparator, that is, L2=AI2+AO−A2=0 or L2≠0(
By determining (see equation (20)) and latching it at CK6, error position detection for double errors can be performed. Also 1
Error position detection for heavy errors is performed using equation (20) as Ll=A
This can be done by determining whether O or L1≠0 and latching it with CK6.

[A generation circuit] The A generation circuit 2 consists of a circuit that EXORs KO~ generated by the K generation circuit with 3 to generate AO~A2, and an AO+Al, AO2, and A12 generation circuit according to equation (17). , is only involved in decoding. KO ~ 3 is,
Because they are not sent at the same time due to the pass line configuration, −
A is generated by latching K by MCK, sending it one clock, and EXOHing K with the output delayed by one clock. The circuit configuration is shown in Fig. 22, and the timing is shown in Fig. 23. From Fig. 23 onwards, the shaded area indicates that the signal is inva lid. has no meaning in the subsequent algorithm, and AO+
The value of AI is output only in the part synchronized with the AI of A, and the other parts have no meaning. Make 9 + AO and AI with CK1 and A
Equation (18) generates O2 and A12.

This is due to timing considerations for calculating (19).

Also, the x2 circuit is a vector representation of X (p (x) = X8
+X4+X3+X2+1 (7) case) x =V7
e a7+V6 * a”+V5 e a5+V4 *
a'LV3 e a2+V1 h a+VO then x2-V71+ a14+V8 e A12 +V5
* alO+V4 a a8+V3a aSAJ2 e
a4+V1 e a2+VO"V7* (a'+a
+1) +V8e (a7+a8+a”+a2+1
)+V511 (αLct5+aLa2) +V4-
(α”Q3+α2+1)+l[e a8+V2 @a4
+Vl order α2+V.

-V8 * a7+ (VB+V5+V3) A8 +V
5- A5 + (V7 wall H4 + V2) * a' + (V
B◆v4) Meeting A3 + (V8+V5+V4+V
1) * A2 -! -V7 battle a+(V7+VB
+V4+VO), which is determined by the circuit configuration shown in FIG.

Next, as mentioned above, the case of the encoder will be explained. The relationship between the parity check matrix H, which is the basis of the Reed-Solomon code, and the code 35I can be expressed by equation (1).

Dividing equation (1) into a parity part and a data part, 1n-3~
in: Multiplying A-1 on both sides of the parity decomposes B. ■ I A-1 and C are combined into A-1φB ■ SI Therefore, in = [, 218 (x15B , 15Ei , 21
2], [30-head double correction coding constant and single correction coding constant are also as follows: [cx23I Q2300 0], [SO official single correction coding constant SI Binding SI S2 S3] T S ■ ■ ・Sl α2 Order s2 α3・8311 8m IT ■ α3 SI Waist 31 S2 S3]” Sl a * Sl a 2 Fist S2
a 3 eS3]-"- Also, the decoder will be explained. The presence or absence of an error can be determined by generating a syndrome.

However, ■ Cao I: code word = J E:
Therefore, the syndrome S is expressed as a product of check matrices H using equation (13).

S=H@J=He (I+E)=H*I+HeHere,
Consider the case where errors ei and ej occur at positions i and j. (1) Syndrome generation 2) Code length correction error E (from the equation) E=H1IE (13).

7) Judgment ■ In case of no error (ei=ej=0) Ll=O L2=O e =0 ■ In case of single error (ei≠0. ei=o) Ll:
0 only when ni=i L2=O e: ei only when ni=i ■ In case of double error (e i≠o, e j≠0)
Ll: Undefined L2: ni=i, Oe only when k=j: ni=i
ei when k=j, ej when k=j... (20) When n is variable, the code length correction circuit uses a ROM or a code length correction circuit as shown in patent application (3) filed on September 30, 1988. Using the exponential vector conversion circuit and the period generating the first syndrome, we use the multiplier described above to calculate α
−n and then further in the multiplier α−2n
, α-3n, latching the output into a 3-state register, and performing OE sub-control of the register using NCKI~3. Its block diagram is shown in FIG. 16, and its timing is shown in FIG. 17.

Z in the period NO to N7 in FIG. 17 is as shown in the above patent application (3).

[Effects] As explained above, the encoding/decoding process is executed in a pipeline, maintaining high processing speed, and making the correction usage and code length variable. The circuit scale can be reduced by sharing circuits and multiplexing circuits.

Furthermore, by using the circuit of the present invention, it has become possible to miniaturize and increase the size of equipment equipped with the circuit.

[Brief explanation of the drawing]

Figure 1 is an encoding circuit block diagram, Figure 2 is a decoding circuit block diagram, Figure 3 is an encoding/decoding circuit block diagram, Figure 4 is a timing diagram of the syndrome generation circuit during encoding, and Figure 5 is a timing diagram of the syndrome generation circuit during encoding. Double error correction encoding constant circuit block diagram, Figure 6 is a diagram showing a double error correction encoding constant output circuit, Figure 7 is a single error correction encoding constant circuit block diagram, Figure 8 is a single error correction encoding constant circuit block diagram. A diagram showing the correction encoding constant output circuit, FIG. 9 is a timing diagram of the encoding constant circuit, FIG. 10 is a block diagram of the code length correction constant circuit, FIG. 11 is a timing diagram of the code length correction constant circuit, and FIG. 12 is a block diagram of the pattern generation circuit, FIG. 13 is a timing diagram of the pattern generation circuit in decoding, FIGS. 14 and 15 are timing diagrams of the pattern generation circuit in encoding, and FIG. 16 is a block diagram of the variable code length correction circuit. Figure 17 is a timing diagram of the variable code length correction circuit, Figure 18 is the x2
Figure 13 is an explanatory diagram of the generation circuit. Figure 20 is an explanatory diagram of the generation circuit for pass line control.
Figure 22 is a diagram explaining the timing of the generation circuit, Figure 22 is a configuration diagram of the A generation circuit, Figure 23 is a diagram explaining the timing of the A generation circuit, Figure 24 is a block diagram of the comparison circuit, 1 is the generation circuit, 2 is the A generation circuit

Claims (1)

[Claims] a decoding circuit having a syndrome generating means, a means for multiplying the syndrome generated by the syndrome generating means by a constant, and a circuit for changing the constant during encoding, and multiplexing the multiplication means. An encoding/decoding circuit characterized in that it is used.