JPS6385915A - Resetting system - Google Patents

Abstract

PURPOSE:To perform resetting even in a specific case when a normal interruption processing is impossible to be performed, by performing the resetting by the interruption keeping the state of a CPU as it is, and performing the resetting by a hardware reset signal in the specific case when the resetting by the interruption is impossible. CONSTITUTION:When a reset switch 1 on a panel is depressed, the reset signal 5 becomes active. Since a reset interruption signal 6 is set inactive, the hardware reset signal 8 is inactive. A reset interruption flip-flop 3 is set at the trailing edge of the reset signal 5, and the interruption signal 6 becomes active, and the interruption is applied on the CPU. When an interruption table is damaged, and interruption processing is performed, the flip-flop 3 remains being set. When the reset switch 1 is depressed again, the reset interruption signal 6 and the reset signal 5 become active, and the hardware reset signal 8 becomes active, and the resetting is applied on the CPU2 mechanically. Thereby, a reset processing can be performed by depressing the reset switch 1 twice.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention provides a C
This relates to a reset method used for PU.

(Prior art) The reset described here refers to a forced IPL using a mechanical switch, etc., mainly for the purpose of taking a memory dump, when software falls into an unrecoverable state for some reason.
(In1t1al Program Load) Refers to the operation of starting a routine.

There are two conventional reset methods: one using an interrupt and the other using a hardware reset signal. Examples of the respective circuits are shown in FIGS. 6 and 7.

(Problem that the invention attempts to solve) First, a method using an interrupt will be explained.

In this method, as shown in FIG. 6, when a reset switch 61 on the operation panel is pressed, it is detected and an interrupt is issued to the CPU 64.

When an interrupt due to a reset occurs, the CPU 64 performs a reset function by interrupting processing and transferring control to the IPL routine. In this method, the stack pointer etc.
Although it has the advantage that the state of the PU is saved and memory dump analysis is easy, if the CPU has an interrupt table in the main memory and the interrupt table in the main memory is destroyed, the interrupt processing will not be possible. There was a problem in that it was not possible to reset because it was not performed normally.

Next, regarding the method using a hardware reset signal, the seventh
This will be explained using figures. In this method, first, when the reset switch 71 on the operation panel is pressed, it is detected;
Generate a hardware reset signal □. :C,PU
73 is IPL when the hardware reset signal is released.
Start a routine. Since this method uses a hardware reset signal, it has the advantage that it can be reset in any state, unlike the above-mentioned interrupt method, but on the other hand, the contents of registers, including the stack pointer inside the CPU, will be destroyed. However, this method had the disadvantage of making it difficult to analyze memory dumps.

The present invention has been made based on the above drawbacks, and
The purpose is to provide a new reset method that combines only the advantages of previous methods.

[Structure of the Invention (Means and Operations for Solving the Problems)] In order to achieve the above object, the present invention normally performs a reset using an interrupt so that the state of the CPU can be saved, and prevents interrupts such as the interrupt table from being corrupted. In special cases where it is not possible to perform a reset using a hardware reset signal, the configuration is such that a reset is performed using a hardware reset signal. For this reason, the components listed below are added.

(1) means for generating a reset signal in response to an operator's operation; (2) a flip-flop that is reset by the reset signal and generates a reset interrupt to the CPU; (3)
means for resetting the flip-flop in response to a command from the CPU; (4) detecting that the flip-flop remains set and a reset signal has newly become active, and transmitting a hardware reset signal to the CPU; Normally, a reset interrupt is generated and reset processing is performed using (1) to (4) above, and if the reset interrupt is not processed and there is a reset request from the operator again, a hardware reset is performed. Generates a signal and performs reset processing.

This makes it possible to reset even in special cases where interrupt processing cannot be performed normally.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1.1 is a reset switch on the operation panel, and 2 is a CPU. A flip-flop 3 detects the ON state of the reset switch 1, detects the CPU, and generates a reset interrupt signal to the CPU 2. 4 indicates that the interrupt signal is active and the reset switch 1 is set to ℃N.
This gate detects the state of the gate 9, and its output is supplied to one input terminal of the gate 9. In addition, 5 is a reset signal indicating that the reset switch 1 on the operation panel has entered the ff1N state, 6 is an interrupt signal to the CPU, and 7 is a C
A signal for canceling a reset interrupt generated by the PU2, and 8 are signal lines through which a hardware reset signal for the CPU2 is propagated.

IO is a gate, to which a reset release signal is supplied via line 7 and a power-6N clear signal via line 11, the output of which is supplied to the clear terminal of flip-flop 3. Further, the other input terminal of the gate 9 is supplied with a hardware reset signal which is an output of the gate 4.

FIGS. 2 and 3 are timing charts showing the operation of the embodiment of the present invention, and show the respective operation timings when the reset interrupt is valid and when the reset interrupt is not valid. Note that the numbers assigned in the figure match those of the signals shown in FIG.

4 and 5 are flowcharts showing the operation of the embodiment of the present invention, and show the reset operation by the operator and the reset interrupt processing, respectively.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. First, normally, when the reset switch 1 on the operation panel is pressed, the reset signal (line 5) becomes active. At this time, the reset interrupt signal (line 6) is inactive, so the hardware reset signal (line 6) for CPU2 is
Line 8) remains inactive. At the trailing edge of the reset signal (line 5), the reset interrupt flip-flop 3 is set and the reset interrupt signal (line 6) becomes active, interrupting the CPU. C.P.
U2 receives the reset interrupt and starts the reset process, but at this time, as shown in the processing flow in Figure 5, it outputs a signal (line 7) to cancel the reset interrupt and clears the reset interrupt flip-flop 3. do. This ensures the operation when the reset switch 1 is pressed again.

The timing of this operation is shown in FIG.

Next, a case will be described in which the interrupt table is destroyed and reset interrupt processing is not performed normally. in this case,
Since the process of canceling the reset interrupt is not performed, the reset interrupt flip-flop 3 remains in the set state. At this time, when you press reset switch 1 on the operation panel again, both the reset interrupt signal (line 6) and the reset signal (line 5) become active, the condition of gate 4 is satisfied, and the hardware reset signal (
Line 8) becomes active. Therefore, the CPU 2 is reset in terms of hardware.

After the reset is released, the CPU performs a reset process.

By pressing the reset switch 1 twice in this way, a hardware reset signal is generated and reset processing becomes possible. The timing of this operation is shown in FIG.

Incidentally, the operation flow of the operator when performing a reset in the embodiment of the present invention is shown in FIG.

[Effects of the Invention] As explained above, according to the present invention, in normal cases, the CPU is reset while preserving its internal state, and even in special cases where interrupt processing cannot be performed normally,
It becomes possible to perform a reset.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are timing charts showing the operation of the embodiment of the present invention. Figure 4. FIG. 5 is a diagram showing an example of a conventional reset circuit used to explain the operation of the embodiment of the present invention, and shows each reset method using a hardware reset signal caused by an interrupt. 1...Reset switch, 2...CPU, 3...
Flip-flop, 4.9.10...gate. Applicant's Representative Patent Attorney Takehiko Suzue Figure 2 Figure 3 Figure 1 Figure 7 Figure 4 Figure 5

Claims (1)

[Claims] A flip-flop that detects the state of a reset switch operated by an operator and issues a reset interrupt to the CPU, and a flip-flop that detects that this flip-flop has become significant and that the reset switch has newly become significant Normally, a reset interrupt is issued to perform the reset process.If the reset interrupt is not processed and a reset request is made again, the hardware is reset via the gate circuit. A reset method characterized by generating a reset signal and performing reset processing.