JPS6384082A - Semiconductor element - Google Patents

Semiconductor element

Info

Publication number
JPS6384082A
JPS6384082A JP61229246A JP22924686A JPS6384082A JP S6384082 A JPS6384082 A JP S6384082A JP 61229246 A JP61229246 A JP 61229246A JP 22924686 A JP22924686 A JP 22924686A JP S6384082 A JPS6384082 A JP S6384082A
Authority
JP
Japan
Prior art keywords
base
atoms
transistor
band width
atom
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61229246A
Other languages
Japanese (ja)
Inventor
Keishi Saito
恵志 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP61229246A priority Critical patent/JPS6384082A/en
Priority to US07/098,791 priority patent/US4887134A/en
Priority to DE19873732418 priority patent/DE3732418A1/en
Priority to CN87107592A priority patent/CN1009688B/en
Publication of JPS6384082A publication Critical patent/JPS6384082A/en
Priority to US07/413,776 priority patent/US5093704A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H01L29/247—Amorphous materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/109—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/11—Devices sensitive to infrared, visible or ultraviolet radiation characterised by two potential barriers or surface barriers, e.g. bipolar phototransistor
    • H01L31/1105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by two potential barriers or surface barriers, e.g. bipolar phototransistor the device being a bipolar phototransistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
    • H01L31/204—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System including AIVBIV alloys, e.g. SiGe, SiC
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

PURPOSE:To improve the frequency characteristics of a junction tran sistor by constituting a base of the transistor of silicon atoms, forbidden band width adjusting atoms and localized level reducing atoms. CONSTITUTION:A collector 102, a base 103 and an emitter 104 are deposited onto a substrate 101 in succession, and layers 105, 106 into which an impurity is doped in high concentration for taking an ohmic are each deposited onto the collector 102 and the emitter 104. Leads 107, 108 and 109 are connected to each layer. A gas containing silicon consisting of an silane compound such as SiH4, a gas containing forbidden band width adjusting atoms composed of a carbon compound such as CH4 and a nitrogen compound such as NH3 and a gas containing localized level reducing atoms made up of hydrogen and a halogen compound are used as a raw material gas for depositing the base.

Description

【発明の詳細な説明】 ［発明の属する分野］ 本発明は、Ｐ−ｎ−Ｐ接合または、ｎ−Ｐ−ｎ接合トラ
ンジスターで、特にベース領域の半導体のバンドギャッ
プが傾斜しているトランジスターに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a P-n-P junction or n-P-n junction transistor, and particularly to a transistor in which the band gap of the semiconductor in the base region is inclined. It is.

［従来技術の説明コ 従来、禁制帯幅が傾斜したベースを有するトランジスタ
ーは、トランジスターの周波数応答を速くすることや、
光トランジスターの光応答性を速くするために提案され
ていた。[Description of the Prior Art] Conventionally, a transistor having a base with a sloped forbidden band width is used to speed up the frequency response of the transistor,
It was proposed to speed up the photoresponsiveness of phototransistors.

従来の前記トランジスターへの試みは、結晶半導体、特
にＧａＡｓ　（ＡＡ）半導体のみで行なわれていた。（
Ｆ、ＣＡＰＡＳＳＯ，５ｕｒｆａｃｅ　　５ｃｉｅｎｃ
ｅＧａ、Ａｓ（ＡＪ）半導体を用いる場合、トランジス
ターは、基板上に分子線エピタキシー法で作られていた
。Previous attempts at such transistors have been made only with crystalline semiconductors, particularly GaAs (AA) semiconductors. (
F, CAPASSO, 5 surface 5 science
When using eGa, As (AJ) semiconductors, transistors have been fabricated on a substrate by molecular beam epitaxy.

分子線エピタキシー法は、超高真空を必要とし、また、
半導体膜の堆積速度も遅い。さらに、大面積化に不向き
であり、量産化が困難であった。加えてＧａやＡｓは毒
性も強く、工業的に取り扱うには、問題の多い材料であ
る。Molecular beam epitaxy requires ultra-high vacuum and
The deposition rate of semiconductor films is also slow. Furthermore, it is not suitable for increasing the area, and mass production is difficult. In addition, Ga and As are highly toxic and are problematic materials to handle industrially.

一方、工業的には安価で、半導体素子に多く使われてい
るＳｉ、　Ｇｅは、結晶では格子定数が異なるため混合
して欠陥のない単結晶を作ることは困難であった。とこ
ろが、５ｉＧｅの合金は非晶質半導体の分野では広く研
究されている。On the other hand, Si and Ge, which are industrially inexpensive and often used in semiconductor devices, have different lattice constants in crystals, so it has been difficult to mix them to form defect-free single crystals. However, 5iGe alloys have been widely studied in the field of amorphous semiconductors.

非晶質半導体の場合、格子定数を考える必要はな（、ま
た構造的な自由度も高（さらに未結合手の補償のために
水素やフッ素などのハロゲン原子が導入されるために欠
陥密度の少ない５ｉＧｅ合金が期待されている。In the case of amorphous semiconductors, there is no need to consider lattice constants (and there is a high degree of structural freedom) (in addition, halogen atoms such as hydrogen and fluorine are introduced to compensate for dangling bonds, so the defect density can be reduced). Less 5iGe alloys are expected.

非晶質の５ｉＧｅ合金の応用としては現在、太陽電池、
センサ、電子写真用感光体などが研究されている。Currently, the applications of amorphous 5iGe alloy are solar cells,
Sensors, photoreceptors for electrophotography, etc. are being researched.

また、非晶質５ｉＧｅ合金では、ＳｉとＧｅの割合を変
えることで、該合金の禁制帯幅を連続的に変化させるこ
とができる。Furthermore, in an amorphous 5iGe alloy, the forbidden band width of the alloy can be continuously changed by changing the ratio of Si to Ge.

同様に、非晶質ＳｉＣ，非晶質ＳｉＮ、非晶質ＳｉＯな
ど、多（の非晶質材料が構成元素の比を変えることで禁
制帯幅を連続的に変えることができる。Similarly, the forbidden band width of multiple amorphous materials such as amorphous SiC, amorphous SiN, and amorphous SiO can be changed continuously by changing the ratio of constituent elements.

しかしながら、非晶質半導体では、電荷の易動度が小さ
いために、実用的なトランジスターの作製をあまり行な
われていない。However, since amorphous semiconductors have low charge mobility, practical transistors are not often manufactured.

また、非晶質半導体で、禁制帯幅を連続的に変化させて
トランジスターを作製する試みは、特開昭５５−１１３
３０に示されているものの、該特開昭での試みは、禁制
帯幅の異なる半導体を連続的に接続し界面に生ずる欠陥
や、不整合を除去することが目的である。Furthermore, an attempt to fabricate a transistor by continuously changing the forbidden band width using an amorphous semiconductor was made in JP-A-55-113.
The purpose of the attempt in the Japanese Patent Application Laid-open No. 30 is to connect semiconductors having different forbidden band widths in a continuous manner and eliminate defects and mismatches that occur at the interface.

したがって、非晶質半導体の易動度が小さいことを回避
してトランジスターを作製するには致っていない。Therefore, it has not been possible to manufacture a transistor while avoiding the low mobility of an amorphous semiconductor.

［発明の目的コ 本発明は、非晶質半導体で作製したトランジスターの周
波数特性の改善を目的としている。[Objective of the Invention] The present invention aims to improve the frequency characteristics of a transistor made of an amorphous semiconductor.

また、本発明は工業的に安価で量産に向いたトランジス
ターを提供することを目的としている。Another object of the present invention is to provide a transistor that is industrially inexpensive and suitable for mass production.

また更に、本発明は光応答性の優れた光トランジスター
を提供することを目的としている。A further object of the present invention is to provide a phototransistor with excellent photoresponsiveness.

［発明の構成］ 本発明は、ｎ−Ｐ−ｎおよびＰ−ｎ−Ｐ接合トラジスタ
−において、ベースが少なくとも硅素原子、禁制帯幅調
整原子および局在準位低減原子から構成された非単結晶
からなり、該ベースの禁制帯幅が連続的に傾斜している
ことを特徴としている。[Structure of the Invention] The present invention provides n-P-n and P-n-P junction transistors in which the base is a non-single crystal composed of at least a silicon atom, a bandgap adjustment atom, and a localized level reduction atom. It is characterized in that the forbidden band width of the base is continuously sloped.

本発明は、単に従来ＧａＡｓ　（Ａｌ）系半導体で行な
われていたことを、非晶質材料などの非単結晶に応用し
たものではない。非晶質材料や粒界のある非単結晶は、
易動度は小さいものの格子定数を考えなくても良いこと
から多くの材料をとりあつかうことかでき、非単結晶材
料と傾斜したバンドギャップのベースを用いたトランジ
スター（以下「傾斜ベーストランシスター」と略記する
）とを組み合せることによって、初めて光のスペクトル
に対応した高速な光トランジスターを作ることが可能と
なる。The present invention does not simply apply what has conventionally been done with GaAs (Al) based semiconductors to non-single crystals such as amorphous materials. Amorphous materials and non-single crystals with grain boundaries are
Although the mobility is small, many materials can be used because there is no need to consider the lattice constant, and transistors using non-single-crystal materials and a base with a tilted band gap (hereinafter referred to as a "tilted base transistor") can be used. (abbreviated)), it becomes possible for the first time to create a high-speed optical transistor that is compatible with the spectrum of light.

また、非単結晶材料は、結晶Ｓｉや結晶ＧａＡｓなどよ
りも禁制帯幅の広い材料（たとえばＡ　　Ｓ　ｉＣ％Ａ
−３ｉＮなど）を作ることもでき温度や高エネルギー粒
子に対して、強いトランジスターを作ることができる。In addition, non-single crystal materials are materials with a wider forbidden band width than crystalline Si or crystalline GaAs (for example, ASiC%A
-3iN, etc.), making it possible to create transistors that are resistant to temperature and high-energy particles.

またさらに、非単結晶材料は、単結晶材料よりはるかに
大面積化が容易である。そのため量産化に優れている。Furthermore, non-single-crystal materials are much easier to grow in area than single-crystal materials. Therefore, it is suitable for mass production.

以下図面に従って説明する。This will be explained below according to the drawings.

第１図は本発明の傾斜ベーストランシスターの模式的説
明図である。基板１０１上に、コレクター１０２、ベー
スｌＯ３、エミッター１０４が順に堆積され、コレクタ
ー１０２とエミッター１０４上には、それぞれオーミッ
クをとるための高濃度にドーピングした層１０５，１０
６が堆積されている。各層にはリード線１０７．１０８
，１０９が接続されている。FIG. 1 is a schematic illustration of a tilted base transistor of the present invention. A collector 102, a base 1O3, and an emitter 104 are sequentially deposited on a substrate 101, and highly doped layers 105 and 10 are respectively deposited on the collector 102 and the emitter 104 to obtain ohmic properties.
6 are deposited. Each layer has lead wires 107.108
, 109 are connected.

第２図は本発明の傾斜ベーストランシスターの熱平衡状
態の模式的なバンド図である。FIG. 2 is a schematic band diagram of the thermal equilibrium state of the tilted base transistor of the present invention.

エミッター２０３、べ“−ス２０４、コレクター２０５
の伝導帯２０１１価電子帯２０２、フェルミレベル２０
６を示している。ベース２０４はエミッター側が広（コ
レクター側が狭くなっていることが望ましい。またベー
スとエミッターとの界面およびベースとコレクターとの
界面に、ハツチやスパイク等の不連続性が生ずる場合、
ベースとエミッター問およびベースとコレクター間で構
成元素を連続的に分布させる方が望ましい。Emitter 203, base 204, collector 205
Conduction band 2011, valence band 202, Fermi level 20
6 is shown. The base 204 is preferably wide on the emitter side (narrow on the collector side).Also, if discontinuities such as hatches or spikes occur at the interface between the base and emitter or the interface between the base and collector,
It is preferable to continuously distribute the constituent elements between the base and emitter and between the base and collector.

また、本発明の効果を有効に発揮するためには、ベース
の最も禁制帯幅の大きいところと小さいところの禁制帯
幅の差は０．１ｅＶ以上が好ましく、最適には０．２ｅ
Ｖ以上である。In addition, in order to effectively exhibit the effects of the present invention, the difference in the forbidden band width between the largest and smallest forbidden band widths of the base is preferably 0.1 eV or more, and optimally 0.2 eV.
V or more.

さらに、ベースの層厚は、本発明の傾斜ベーストランシ
スターの特性を決める因子として重要なものであって、
種々の材料によって異なるものの、好ましくは２μｍ以
下、より好ましくは１μｍ以下、最適には０．７μｍ以
下である。Furthermore, the layer thickness of the base is an important factor determining the characteristics of the graded base transistor of the present invention, and
Although it varies depending on the various materials, it is preferably 2 μm or less, more preferably 1 μm or less, and optimally 0.7 μm or less.

一方、本発明の傾斜ベーストランシスターを、光トラン
ジスターとして用いる場合には、エミッターの禁制帯幅
がベースの禁制帯幅より広いことが望ましい。On the other hand, when the graded base transistor of the present invention is used as a phototransistor, it is desirable that the forbidden band width of the emitter is wider than that of the base.

第４図は、本発明の傾斜ベーストランシスターを作製す
るための堆積膜形成装置の一例である。FIG. 4 is an example of a deposited film forming apparatus for manufacturing the tilted base transistor of the present invention.

本発明で使用した堆積膜形成装置は、容量結合型である
。減圧にし得る堆積室４０１、反応空間４０２、アノー
ド電極４０３、基板加熱用ヒーター４０４、ヒータ制御
装置４０５、カソード電極４０６、高周波電源４０７、
基板４０８、排気系４０９、真空ゲージ４７０１原料ガ
ス供給管４１０．原料ガスボンベ４１１〜４１４、圧力
ゲージ４２１〜４２４．４８１〜４８４．１次バルブ４
３１〜４３４．２次バルブ４４１〜４４４、マスフロー
コントローラー４６１〜４６４、バルブ４５１〜４５４
から堆積膜形成装置は構成されている。The deposited film forming apparatus used in the present invention is of a capacitive coupling type. Deposition chamber 401 that can be reduced in pressure, reaction space 402, anode electrode 403, substrate heating heater 404, heater control device 405, cathode electrode 406, high frequency power source 407,
Substrate 408, exhaust system 409, vacuum gauge 4701, raw material gas supply pipe 410. Raw material gas cylinders 411-414, pressure gauges 421-424.481-484.Primary valve 4
31-434. Secondary valves 441-444, mass flow controllers 461-464, valves 451-454
The deposited film forming apparatus is constructed from the following.

本発明の傾斜ベーストランシスターは、次の様にして作
製した。まず、アノード電極に基板を設置し、堆積室４
０１内を約ｔｏ−’Ｔｏｒｒに排気し、ヒータ制御装置
４０５のスイッチを入れ、基板を５０°Ｃ〜６００°Ｃ
に加熱した。基板が所定の温度になったことを確認して
、コレクター形成用の原料ガスを、原料ガスボンベから
所定流量をマスフローコントローラーを介して、堆積室
に導入する。真空ゲージ４７０で堆積室４０１の内圧が
所定の圧力０．０１〜１０Ｔｏｒｒになったことを確認
して、高周波電源４０７のスイッチを入れ、高周波電力
を堆積室内に０．ＯＩＷ／ｃｒｒｉ’−１０Ｗ　／　ｃ
　ｒｒ？に投入した。所定の時間グロー放電を行って、
コレクターを０．０５μｍ〜１０μｍ堆積した。コレク
ターが形成された後、堆積室４０１内を十分に排気し、
基板温度を室温にまで下げ、コレクターを堆積した基板
を堆積室外へ取り出し、コレクターの形状を所定の形状
になる様にエツチングした。The tilted base transistor of the present invention was manufactured as follows. First, a substrate is installed on the anode electrode, and the deposition chamber 4
Evacuate the inside of 01 to about to-'Torr, turn on the heater control device 405, and heat the board to 50°C to 600°C.
heated to. After confirming that the substrate has reached a predetermined temperature, a predetermined flow rate of raw material gas for collector formation is introduced from the raw material gas cylinder into the deposition chamber via a mass flow controller. After confirming with the vacuum gauge 470 that the internal pressure of the deposition chamber 401 has reached the predetermined pressure of 0.01 to 10 Torr, the high-frequency power source 407 is turned on, and the high-frequency power is supplied to the deposition chamber at 0.0 Torr. OIW/cri'-10W/c
rr? I invested in it. Perform glow discharge for a predetermined time,
The collector was deposited from 0.05 μm to 10 μm. After the collector is formed, the inside of the deposition chamber 401 is sufficiently evacuated,
The substrate temperature was lowered to room temperature, the substrate on which the collector was deposited was taken out of the deposition chamber, and the collector was etched into a predetermined shape.

その後再び堆積室４０１内にコレクターを堆積した基板
を設置し、コレクターと同様な操作手順で、ベースを２
μｍ以下堆積した。ベースの禁制帯幅を連続的に変化さ
せて堆積するには、禁制帯幅調整元素を含有した原料ガ
スの流量を連続的に減少または増加させて行った。そし
て、コレクターを堆積した後と同様に基板を堆積室外に
とり出して所定のパターニングを行い。また再び堆積室
内にコレクターとベースを堆積した基板を設置し、コレ
クター堆積と同様な操作手順で、エミッターを堆積した
。以上の様にして、傾斜ベーストランシスターを形成し
た。After that, the substrate on which the collector was deposited was placed again in the deposition chamber 401, and the base was removed from the base 2 using the same operating procedure as for the collector.
Deposits were less than μm. In order to deposit the base while continuously changing the forbidden band width, the flow rate of the raw material gas containing the forbidden band width adjusting element was continuously decreased or increased. Then, in the same way as after depositing the collector, the substrate was taken out of the deposition chamber and predetermined patterning was performed. In addition, the substrate on which the collector and base were deposited was placed in the deposition chamber again, and the emitter was deposited using the same operating procedure as the collector deposition. In the manner described above, a tilted base transistor was formed.

本発明のベース堆積用の原料ガスとしては、硅素含有ガ
スは、ＳｉＨ４、ＳｉＦ４　、Ｓｉ２Ｈ６，５ｉ２Ｆａ
、Ｓｉ３Ｈ８、ＳｉＨ３Ｆ、ＳｉＨ２Ｆ２・・・等の鎖
状シラン化合物、または、５ｉ５Ｊ。、５ｉ６Ｈ，□、
Ｓｉ　４　ＨＢ・・・等の環状シラン化合物等が有用で
ある。禁制帯幅調整原子含有ガスは、禁制帯幅拡大する
ものでは、ＣＨ４、ＣＨ２Ｆ２、Ｃ２Ｈ６、Ｃ２Ｈ４、
Ｃ２Ｉ４□、Ｓｉ（ＣＨ３）４．５ｉＨ（ＣＨ３）３な
どの炭素化合物、　Ｎ２、ＮＩ］３、Ｈ２ＮＮＨ２、Ｈ
Ｎ３、ＮＨ４Ｎ３、Ｆ３Ｎ１Ｆ４Ｎ等の窒素化合物、０
゜、ＣＯ２、Ｎ０１ＮＯ２，０３、Ｎ２０１Ｎ２０３、
Ｎ２Ｏ４、ＮＯ３等の酸素化　合物が有用であり、禁制
帯幅縮小するものでは、ＧｅＨ４、ＧｅＦ４・・・等の
ゲルマニウム化合物、ＳｎＨ４等のスズ化合物が有用で
ある。さらに、局在準位低減原子を含有する原料ガスと
しては、Ｆ２、Ｆ２、Ｃ１２、・・・等の水素およびハ
ロゲン化合物が有用である。As the raw material gas for base deposition of the present invention, silicon-containing gases include SiH4, SiF4, Si2H6, 5i2Fa.
, Si3H8, SiH3F, SiH2F2, etc., or 5i5J. ,5i6H,□,
Cyclic silane compounds such as Si 4 HB... are useful. The forbidden band width adjusting atom-containing gases that expand the forbidden band width include CH4, CH2F2, C2H6, C2H4,
Carbon compounds such as C2I4□, Si(CH3)4.5iH(CH3)3, N2, NI]3, H2NNH2, H
Nitrogen compounds such as N3, NH4N3, F3N1F4N, 0
゜, CO2, N01NO2,03, N201N203,
Oxygen compounds such as N2O4 and NO3 are useful, and germanium compounds such as GeH4, GeF4, etc., and tin compounds such as SnH4 are useful for reducing the forbidden band width. Furthermore, hydrogen and halogen compounds such as F2, F2, C12, . . . are useful as the raw material gas containing localized level reducing atoms.

局在準位低減原子は、本発明を効果的に行うにあたって
重要な因子である。ベースに含有される局在準位低減原
子の１は、好ましくは１〜６ｏ原子％、より好ましくは
５〜４０原子％、最適には１０〜３５原子％である。The localized level reduction atom is an important factor in effectively carrying out the present invention. The local level reducing atoms contained in the base preferably range from 1 to 6 atom %, more preferably from 5 to 40 atom %, and optimally from 10 to 35 atom %.

さらにまた、本発明のベースに含有される伝導性を制御
する原子として、周期律表で第■族原子または／および
第Ｖ族原子が使用される。Furthermore, atoms of group 1 and/or atoms of group V in the periodic table are used as atoms controlling conductivity contained in the base of the present invention.

具体的には、第■族原子としては、Ｂ（硼素）、Ａｌ（
アルミニウム）、Ｇａ　（ガリウム）、Ｉｎ（インジウ
ム）、Ｔｌ　（タリウム）等を挙げることができるが、
特に好ましいものは、Ｂ１Ｇａである。Specifically, the Group Ⅰ atoms include B (boron), Al (
Aluminum), Ga (gallium), In (indium), Tl (thallium), etc.
Particularly preferred is B1Ga.

また第Ｖ族原子としては、Ｐ（燐）、Ａｓ（砒素）、ｓ
ｂ　（アンチモン）、Ｂｉ　（ビスマン）等を挙げるこ
とができるが、特に好ましいものはｐ、ｓｂである。Group V atoms include P (phosphorus), As (arsenic), s
b (antimony), Bi (bismane), etc. can be mentioned, but particularly preferred are p and sb.

ベースに含有される伝導性を制御する原子は、ベースに
均一に含有されても不均一に分布して含有されてもよい
。The conductivity-controlling atoms contained in the base may be contained uniformly or non-uniformly distributed in the base.

ベースに含有される伝導性を制御する原子の含有量は、
好ましくは５％以下、より好ましくは３％以下、最適に
は１％以下である。The content of atoms that control conductivity contained in the base is
Preferably it is 5% or less, more preferably 3% or less, and optimally 1% or less.

以下実施例に従って、本発明を説明する。The present invention will be described below with reference to Examples.

実施例１ 第４図の堆積膜形成装置を用いて、コーニング社製７０
５９ガラス上に所定の手順に従って第１表の条件で、第
１図の層構成、第２図のバンド図の本発明の傾斜ベース
トランシスターを作製した。Example 1 Using the deposited film forming apparatus shown in FIG.
EXAMPLE 1 A tilted base transistor of the present invention having the layer structure shown in FIG. 1 and the band diagram shown in FIG. 2 was fabricated on No. 59 glass according to a predetermined procedure under the conditions shown in Table 1.

各層はＲＨＥＥＤで測定したところ非晶質であった。Each layer was amorphous as measured by RHEED.

ベース内のゲルマニウムの含有量はＳＩＭＳで測定した
ところ０から３０原子％と連続的に変化していた。The content of germanium in the base was measured by SIMS and was found to vary continuously from 0 to 30 atomic %.

さらに、ゲルマニウムを含有していないアモルファスシ
リコン層の禁制帯幅は１．７ｅＶあり、ゲルマニウムを
３０原子％含有しているアモルファスシリコン層の禁制
帯幅は１．４５ｅＶであった。Furthermore, the forbidden band width of the amorphous silicon layer not containing germanium was 1.7 eV, and the forbidden band width of the amorphous silicon layer containing 30 atomic percent germanium was 1.45 eV.

本実施例のトランジスターは、比較例に示すトランジス
ターと比較して、周波数特性が１．７倍改善された。The frequency characteristics of the transistor of this example were improved by 1.7 times compared to the transistor shown in the comparative example.

実施例２ 第４図の堆積膜形成装置を用いて、コーニング社製７０
５９ガラス上に所定の手順に従って、第２表の条件で、
第１図の層構成、第５図のバンド図の本発明の傾斜ベー
ストランシスターを作製した。Example 2 Using the deposited film forming apparatus shown in FIG.
59 on glass according to the prescribed procedure and under the conditions shown in Table 2.
A tilted base transistor of the present invention having the layer structure shown in FIG. 1 and the band diagram shown in FIG. 5 was manufactured.

各層はＲＨＥＥＤで測定したところ非晶質であった。Each layer was amorphous as measured by RHEED.

ベース内の炭素含有量は、ＳＩＭＳで測定したところ、
２０原子％から０原子％で分布していた。また、炭素２
０原子％含有するアモルファスシリコン層の禁制帯幅は
２．ＯｅＶであった。The carbon content in the base was measured by SIMS.
It was distributed from 20 atomic % to 0 atomic %. Also, carbon 2
The forbidden band width of an amorphous silicon layer containing 0 atomic % is 2. It was OeV.

本実施例のトランジスターは、比較例に示すトランジス
ターと比較して、ＳＮ比が１．５倍改善された。The transistor of this example had an SN ratio improved by 1.5 times compared to the transistor shown in the comparative example.

実施例３ 第４図の堆積膜形成装置を用いて、コーニング社製７０
５９カラス上に所定の手順に従って、第３表の条件で、
第１図の層構成、第６図のバンド図の本発明の傾斜ベー
ストランシスターを作製した。Example 3 Using the deposited film forming apparatus shown in FIG.
59 on the crow according to the prescribed procedure and under the conditions of Table 3,
A tilted base transistor of the present invention having the layer structure shown in FIG. 1 and the band diagram shown in FIG. 6 was manufactured.

各層はＲＨＥＥＤで測定したところ非晶質であった。Each layer was amorphous as measured by RHEED.

ベース内の炭素含有量は、ＳＩＭＳで測定したところ、
３０原子％からＯ原子％で分布していた。The carbon content in the base was measured by SIMS.
The distribution ranged from 30 atomic % to O atomic %.

また、禁制帯幅は一番広いところで２．２ｅＶであった
。Further, the forbidden band width was 2.2 eV at its widest point.

可視光に対する応答のＳＮ比は、比較例に示すトランジ
スターと比較して、２倍改善されていた。The SN ratio in response to visible light was improved by two times compared to the transistor shown in the comparative example.

比較例 第４図の堆積膜形成装置を用いてコーニング社製７０５
９ガラス上に所定の手順に従って、第４表の条件で、第
１図の層構成、第３図のバンド図の本発明の比較例のト
ランジスターを作製した。Comparative Example Using the deposited film forming apparatus shown in FIG.
A comparative transistor of the present invention having the layer structure shown in FIG. 1 and the band diagram shown in FIG.

［効果の説明〕 以上説明したように、非晶質半導体トランジスターの周
波数特性や、光応答性をベースの禁制帯幅を傾斜させる
ことによって著しく改善できる。[Explanation of Effects] As explained above, the frequency characteristics and photoresponsiveness of an amorphous semiconductor transistor can be significantly improved by tilting the forbidden band width of the base.

また、本発明は、非単結晶材料で傾斜ベーストランシス
ターを作るために工業的に非常に容易に量産することが
できる。Moreover, the present invention can be industrially mass-produced very easily to make graded base transistors with non-single crystal materials.

また更に、非単結晶材料で傾斜ベーストランシスターを
作るために、禁制帯幅や材料の自由度が広がり、目的に
合った傾斜ベーストランシスターを作ることができる。Furthermore, since the graded base transistor is made of a non-single-crystal material, the bandgap width and the degree of freedom of the material are widened, and a graded base transistor suitable for the purpose can be made.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の傾斜トランジスターの層構成図である
。 第２図、第５図、第６図は実施例で用いた本発明の傾斜
トランジスター模式的バンド図である。 第３図は比較例の模式的バンド図である。 第４図は本発明の傾斜トランジスターを作製するための
堆積膜形成装置である。FIG. 1 is a layer structure diagram of a tilted transistor of the present invention. FIG. 2, FIG. 5, and FIG. 6 are schematic band diagrams of the gradient transistor of the present invention used in Examples. FIG. 3 is a schematic band diagram of a comparative example. FIG. 4 shows a deposited film forming apparatus for manufacturing the tilted transistor of the present invention.

Claims (5)

【特許請求の範囲】[Claims] （１）ｎ−Ｐ−ｎ又はＰ−ｎ−Ｐ接合トランジスターに
おいて、ベースが少なくとも硅素原子、禁制帯幅調整原
子および局在準位低減原子から構成された非単結晶から
なり、該ベースの禁制帯幅が連続的に傾斜していること
を特徴とするトランジスター。(1) In an n-P-n or P-n-P junction transistor, the base is made of a non-single crystal composed of at least a silicon atom, a forbidden band width adjusting atom, and a localized level reducing atom; A transistor characterized by a continuously sloping band width. （２）前記禁制帯幅調整原子の内、禁制帯幅拡大原子と
して、炭素原子、窒素原子、酸素原子の内少なくとも１
種を構成原子とするベースを有する特許請求の範囲第１
項記載のトランジスター。(2) Among the forbidden band width adjustment atoms, at least one of a carbon atom, a nitrogen atom, and an oxygen atom is used as a forbidden band width expanding atom.
Claim 1 having a base consisting of species as constituent atoms
Transistor described in section. （３）前記禁制帯幅調整原子の内、禁制帯幅縮小原子と
して、ゲルマニウム、スズ原子の内少なくとも１種を、
構成原子とするベースを有する特許請求の範囲第１項記
載のトランジスター。(3) Among the forbidden band width adjusting atoms, at least one of germanium and tin atoms is used as a forbidden band width reducing atom,
The transistor according to claim 1, which has a base as a constituent atom. （４）前記局在準位低減原子が、水素、フッ素原子の内
、少なくとも一方である特許請求の範囲第１項記載のト
ランジスター。(4) The transistor according to claim 1, wherein the localized level reducing atom is at least one of hydrogen and fluorine atoms. （５）前記ベースが非晶質半導体で構成されている特許
請求の範囲第１項記載のトランジスター。(5) The transistor according to claim 1, wherein the base is made of an amorphous semiconductor.
JP61229246A 1986-09-26 1986-09-26 Semiconductor element Pending JPS6384082A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP61229246A JPS6384082A (en) 1986-09-26 1986-09-26 Semiconductor element
US07/098,791 US4887134A (en) 1986-09-26 1987-09-21 Semiconductor device having a semiconductor region in which either the conduction or valence band remains flat while bandgap is continuously graded
DE19873732418 DE3732418A1 (en) 1986-09-26 1987-09-25 Semiconductor component having a semiconductor region in which a band (energy) gap is continuously stepped
CN87107592A CN1009688B (en) 1986-09-26 1987-09-25 Semiconductor device having semiconductor region in which band gap being continuously graded
US07/413,776 US5093704A (en) 1986-09-26 1989-09-28 Semiconductor device having a semiconductor region in which a band gap being continuously graded

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61229246A JPS6384082A (en) 1986-09-26 1986-09-26 Semiconductor element

Publications (1)

Publication Number Publication Date
JPS6384082A true JPS6384082A (en) 1988-04-14

Family

ID=16889105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61229246A Pending JPS6384082A (en) 1986-09-26 1986-09-26 Semiconductor element

Country Status (1)

Country Link
JP (1) JPS6384082A (en)

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