JPS6381513U - - Google Patents
Info
- Publication number
- JPS6381513U JPS6381513U JP17539186U JP17539186U JPS6381513U JP S6381513 U JPS6381513 U JP S6381513U JP 17539186 U JP17539186 U JP 17539186U JP 17539186 U JP17539186 U JP 17539186U JP S6381513 U JPS6381513 U JP S6381513U
- Authority
- JP
- Japan
- Prior art keywords
- power
- turned
- power supply
- supply voltage
- control terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001052 transient effect Effects 0.000 claims 1
- 230000007704 transition Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第1図は本考案の一実施例の構成を示す回路図
、第2図は第1図の動作説明用のタイミングチヤ
ート図、第3図は電源オフ後、再びオンした場合
における第1図の動作説明用のタイミングチヤー
ト図、第4図は本考案の他の一実施例を示す回路
図、第5図は本考案のさらに他の一実施例を示す
回路図、第6図は従来のミユート回路を示す回路
図、第7図は第6図の動作説明用のタイミングチ
ヤート図である。
11……ミユート回路、12,13……抵抗、
16……差動アンプ、17……コンデンサ、18
……トランジスタ、19……アナログスイツチ、
21,22……抵抗、23……コンデンサ、24
……トランジスタ、26……リレー。
Fig. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of Fig. 1, and Fig. 3 is a diagram showing the configuration of Fig. 1 when the power is turned on again after being turned off. 4 is a circuit diagram showing another embodiment of the present invention, FIG. 5 is a circuit diagram showing still another embodiment of the present invention, and FIG. 6 is a conventional MIUTO diagram. A circuit diagram showing the circuit, and FIG. 7 is a timing chart for explaining the operation of FIG. 6. 11... Mute circuit, 12, 13... Resistor,
16...Differential amplifier, 17...Capacitor, 18
...transistor, 19...analog switch,
21, 22...Resistor, 23...Capacitor, 24
...transistor, 26...relay.
Claims (1)
時における回路の不安定動作時に対して映像出力
又は音声出力をスイツチのオン、オフ制御で停止
させるものであつて、 しきい値レベル以上であるか否かで前記スイツ
チをオン、オフする制御端に、電源オンによる電
源電圧の上昇よりも遅い時定数で上昇するバイア
ス電圧を印加するバイアス印加手段と、互いに異
る時定数のバイアス電圧が差動入力端に印加され
た差動増幅手段と、電源オフ時における前記差動
入力端に生じた微小の電位差を前記差動増幅手段
で増幅して前記制御端の電位をしきい値と交差す
るように転移させる転移手段とを設けたことを特
徴とするミユート回路。[Claims for Utility Model Registration] A device that stops video output or audio output through on/off control of a switch in response to unstable operation of a circuit during transient changes in power supply voltage when the power is turned on or off. bias applying means that applies a bias voltage that increases with a time constant slower than the increase in power supply voltage due to power-on to a control terminal that turns on and off the switch depending on whether or not the voltage is equal to or higher than a threshold level; A differential amplifying means has a constant bias voltage applied to the differential input terminal, and the differential amplifying means amplifies a minute potential difference that occurs between the differential input terminals when the power is turned off, thereby increasing the potential of the control terminal. A miute circuit characterized in that it is provided with a transition means for transitioning so as to cross a threshold value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17539186U JPS6381513U (en) | 1986-11-17 | 1986-11-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17539186U JPS6381513U (en) | 1986-11-17 | 1986-11-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6381513U true JPS6381513U (en) | 1988-05-28 |
Family
ID=31114674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17539186U Pending JPS6381513U (en) | 1986-11-17 | 1986-11-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6381513U (en) |
-
1986
- 1986-11-17 JP JP17539186U patent/JPS6381513U/ja active Pending
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