JPS6381419U - - Google Patents
Info
- Publication number
- JPS6381419U JPS6381419U JP17395586U JP17395586U JPS6381419U JP S6381419 U JPS6381419 U JP S6381419U JP 17395586 U JP17395586 U JP 17395586U JP 17395586 U JP17395586 U JP 17395586U JP S6381419 U JPS6381419 U JP S6381419U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- signal
- address
- memory
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図はこの考案の一実施例を示すブロツク回
路図、第２図は従来の選局電圧プリセツト装置を
示すブロツク回路図である。
２２……キースイツチ、ＶＴ……選局電圧、Ｂ
ＳＷ……バンド切換信号。
FIG. 1 is a block circuit diagram showing an embodiment of this invention, and FIG. 2 is a block circuit diagram showing a conventional channel selection voltage presetting device. 22...Key switch, VT...Tuning selection voltage, B
SW...Band switching signal.
Claims (1)
る電子同調チユーナと、 選局電圧をデジタル信号として発生する手段と
、 前記デジタル信号をアナログ信号に変換して前
記チユーナに印加する手段と、 前記チユーナの出力である中間周波信号の搬送
波の周波数を弁別してチユーナの受信状態を判別
し所定放送信号を受信したときに受信判別信号を
出力する手段と、 前記デジタル信号を記憶するメモリと、 前記デジタル信号発生手段の出力デジタル信号
を連続的に変化させ前記受信判別信号が出力され
たときにその変化を停止させそのデジタル信号を
前記メモリの第１のアドレスに記憶させる手段と
、 前記メモリの第１のアドレスに記憶されている
デジタル信号を読出して第２のアドレスに記憶さ
せる手段と、 前記メモリの第２のアドレスに記憶されている
デジタル信号を読出して前記デジタル信号発生手
段に移しそのデジタル信号を変化させ前記受信判
別信号が出力されたときにその変化を停止させそ
のデジタル信号を前記メモリの第２のアドレスに
記憶させる手段とを具備したことを特徴とする選
局電圧プリセツト装置。[Claims for Utility Model Registration] An electronic tuning tuner whose tuning frequency is set by applying a tuning voltage, means for generating the tuning voltage as a digital signal, and converting the digital signal into an analog signal to generate the tuning frequency. means for applying voltage to the tuner; means for discriminating the frequency of the carrier wave of the intermediate frequency signal output from the tuner to determine the reception state of the tuner and outputting a reception discrimination signal when a predetermined broadcast signal is received; and the digital signal. a memory for storing the output digital signal of the digital signal generating means, and a memory that continuously changes the output digital signal of the digital signal generating means, stops the change when the reception discrimination signal is output, and stores the digital signal at a first address of the memory. means for reading a digital signal stored at a first address of the memory and storing it at a second address; and means for reading a digital signal stored at a second address of the memory and storing the digital signal at a second address. A selection characterized in that it comprises means for transferring the digital signal to the generating means, changing the digital signal, stopping the change when the reception discrimination signal is output, and storing the digital signal at the second address of the memory. Local voltage preset device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17395586U JPS6381419U (en) | 1986-11-14 | 1986-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17395586U JPS6381419U (en) | 1986-11-14 | 1986-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6381419U true JPS6381419U (en) | 1988-05-28 |
Family
ID=31111903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17395586U Pending JPS6381419U (en) | 1986-11-14 | 1986-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6381419U (en) |
-
1986
- 1986-11-14 JP JP17395586U patent/JPS6381419U/ja active Pending
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