JPS6380572A - Conductivity modulation vertical mos-fet - Google Patents

Abstract

PURPOSE:To suppress a latchup phenomenon due to a parasitic thyristor by providing a series resistor through a polysilicon layer and an insulating oxide film over both a source layer and a first conductivity type base layer. CONSTITUTION:A P<+> type layer 5 and a P-type base layer 6 are formed in an N<-> base layer 4, a gate polysilicon layer 9 is formed on an N<-> type gate layer, a resist mask 20 for metal-contacting with the layer 5 is attached to the hole, and As ions are implanted in a self-aligning manner by the mask 20 and the layer 9. Then, when the mask 20 is removed, an N<+> type source layer 8 is formed. Then, a PSG film 10 is formed on the surface, only a part metal-contacted with the layer 5 remains by a photoetching process, a resistor 15 of polysilicon to which an impurity dopant undoped or is suitably added to exhibit an N-type conductivity is added to the surface is formed, and a source electrode 1 is then formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a vertical MOS-FET that utilizes bipolar operation by adding a region of conductivity type opposite to the source on the drain side.

[Prior art and its problems]

For example, an N-channel MOS using hahaibora operation.
FET generally has a structure as shown in FIG.

Figure 4 shows a schematic cross-sectional view of the main parts.
The main components are source electrode 1, gate electrode 2. Drain electrode 3. N-base layer 4° 2 layers 5. P base layer 6.
P drain layer 7. N source layer8. Gate Porin 11 Con Eyebrow 9. It consists of an insulating oxide film 10. symbol S
is source, G is gate.

D represents a drain.

When a voltage higher than a certain threshold value is applied to the gate electrode 2 of the source electrode 1 of an element having such a structure,
The surface of the P base layer 6 under the gate resistor 11/11J9 is inverted to form an electron channel, and the source and drain are brought into conduction. Through this channel N'
``When the electrons flowing into the base 14 reach the P drain layer 7, they cause hole injection. Due to the hole injection, the N-base layer 4 undergoes conductivity modulation, and the conductivity increases significantly, causing a large current to flow. This current is equal to the normal vertical power M without adding the P+ drain layer 7.
A major advantage is that it is 107-20 times as large as the OS-FET.

Next, the operation of the above element will be explained with reference to FIG. 5, which shows an equivalent circuit of the element having the structure shown in FIG.

The circuit of FIG. 5 is a base short resistor RP, PN)' tone sister 12. NPN transistor 13. hiO
It consists of 8-FET14. The PNP transistor 12 is formed of the P base layer 6. in FIG. N-base layer 4. The NPN transistor 13 is formed by the P drain layer 7, and the NPN transistor 13 is formed by the N+ source layer 8. P base layer 6. It is formed by an N-base layer 4. The base short resistance RP is the resistance when the P base layer 6 and the P layer 5 shown in FIG. 4 are connected in series to the source. The device operates by applying a voltage higher than a threshold to the gate to turn on the MOS-FET 14, and then electrons flow from the source to the base of the PNP transistor 12, turning the device off.

However, as mentioned above, this conductivity modulation type vertical QMO3-F has the advantage of being able to flow a large current.
As is clear from FIG. 5, one drawback of the ET is that it is accompanied by a latch-up phenomenon originating from the parasitic thyristor formed from the NPN transistor 13 and the PNP transistor 12. That is, in a region where the current between the source and drain is small, the voltage drop due to the base short resistor RP is small, so the NPNI transistor 13 can hardly conduct current, and the PNP transistor 12
Only the current is flowing. When the gate voltage of the MOS-FET 14 is increased and a large amount of current begins to flow through the PNP l-transistor 12, the voltage drop due to the base short resistance RP increases, and the parasitic thyristor finally turns on. Even if no gate voltage is applied to the FET 14, the parasitic thyristor portion spontaneously supplies current, making it impossible to cut off the main current. Latch on to this condition.

This latch-up phenomenon limits the maximum current value that can flow through the vertical MOS-FET.

This chirp and pull-up phenomenon is particularly likely to occur at turn-off immediately after the gate voltage is turned off. That is, in Fig. 5, M
When the OS-FET 14 is turned off, the MOS-FET 14 flowing into the base of the PNP transistor 12
Since the flow of electrons from the base is suddenly stopped, there are no more electrons recombining at the base, and as a result, a large number of holes recombine.

- flows to the resistor RP. This is because the parasitic thyristor operates more easily.

In this way, when switching off the vertical MOS-FET,
That is, since the chirp phenomenon is likely to occur in the turn-off state, the turn-off time cannot be made faster, which is a major drawback when using this vertical MOS-FET as a switching element.

[Purpose of the invention]

The present invention has been made in view of the above points, and its purpose is to provide a vertical MOS capable of suppressing the latch-up phenomenon caused by parasitic thyristors, increasing the maximum operating current, and ensuring reliable device switching operation. - To provide an FET.

[Key points of the invention]

The present invention forms a resistor in series with the source region to create an appropriate voltage drop with respect to the electron current, and as a result, maintains a potential that is approximately the same as the voltage drop caused by the hole current, thereby reducing the parasitic thyristor. This is a vertical type MOS-FET that is less susceptible to the phenomena caused by

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of the main part of the vertical MOS-FET achieved by the present invention, and FIG. 2 is its equivalent circuit diagram.
They can now be compared and corresponded to Figures 4 and 5, respectively, and the parts common to Figures 1 and 2 are given the same reference numerals. The difference from FIG. 4 is that a resistor 15 having an appropriate value is provided in series with the source region. This resistor 15 can be made of polysilicon, for example. In this way, electrons passing through the inversion region directly under the gate 9 of the board 11 pass through the resistor 15 from the source. That is, electrons flow from the source, through the resistor 15, through the gate 9, and into the N''-base layer 4.

Next, it will be explained that the added resistor 15 suppresses the latch-up phenomenon of the element and also prevents dynamic chi-up during switch-off (turn-off state).

The equivalent circuit of this element is shown in Fig. 2, which differs from Fig. 5 in that a resistance RN is added using the resistor 15 in Fig. 1 through which electrons flow, and the hole current is shown in the direction indicated by the arrow. If Ih is the electron current, and I is the total current, then the thyristor operates at almost the same time as the NPN transistor 13.
The base voltage is the built-in voltage VB (0.6 to 0.7
V).

Therefore, the conditions for the parasitic risk not to latch up are Rp h < Ie RN + VB...
・・・・・・・・・・・・・・・・・・・・・・・・(1
). Further, if the gain of the common base current of the PNP l-run risk 12 is α, then the following equation is obtained. Substituting equation (2) into equation (11), we get: Therefore, if the resistance RN is determined to satisfy equation (11), then equation (11) is satisfied for any current I. In other words, latch-up can never occur. .

Also, when the switch is off (turn-off state), the Hall current Ih flowing through the resistor RP shown in FIG.
- When the run risk 13 starts operating, the electronic current e also increases, and the potential of the emitter 19 of the NPNI run risk 13 increases, which eventually works to suppress the occurrence of the chirp phenomenon.

Regarding the question of whether the on-voltage increases because the resistor 15 is added in series, the answer is
Since the '4 voltage at the base 17 of the NPN transistor 13 is about 0.6 to 0.7 V when turning on, the voltage drop due to the resistor ItN is also 8 degrees, which is fatal due to an increase in the on-voltage. It cannot be a serious drawback.

Next, a manufacturing process for obtaining the configuration of the vertical MOS-FET of the present invention will be described. FIG. 3 shows (1) the main steps required for the present invention. Two layers 5. P base layer 6. After forming a gate polysilicon layer 9 on the N-base layer and attaching a resist mask X for making metal contact with the opening ICP 45, this resist mask is applied and ions are implanted into the gate polysilicon layer ( al. Then resist mask 2
0 is removed, but at this time fbl where the N source layer 8 is formed. Next, a PSG film 10 is formed on the surface, and a photoetching process is performed to leave only the portion where the two layers 5 come into contact with metal. Similarly, a resistor 15 made of undoped polysilicon or polysilicon doped with an appropriate impurity dopant exhibiting N-type conductivity is further formed on its surface (d), and then a source electrode is provided (el).

In the above manufacturing process, the resistance value of the resistor 15, which is the key point of the present invention, is determined by
If a compound is used, the amount of impurities can be easily controlled by a suitable gas such as a doped in vivo compound such as phosphine (PH3) during the formation of polysilicon. Therefore, since the resistance value of the resistor 15 can be arbitrarily determined, it is possible to optimally design an element that meets the purpose of the present invention. In addition, the wafer process required for the present invention requires only one step of forming silicon holes and photoetching in addition to the normal wafer process. First, there is no particular problem in manufacturing the device.

〔Effect of the invention〕

Although vertical MOS-FETs that utilize bipolar operation are capable of passing large currents, they have the disadvantage that the current is limited by the chirp phenomenon caused by parasitic cystars. On the other hand, in the present invention, as described in the embodiment, by adding a resistor of an appropriate value in series with the source region, the potential due to the voltage drop of the electron current and the potential due to the voltage drop of the hole current are almost the same. In this way, it is possible to suppress the operation of the parasitic cylindrical star and prevent the occurrence of the chirp phenomenon.Moreover, it is possible to use the resistor as a resistor in the normal wafer process in the device manufacturing process. It has many advantages, such as simply adding the formation process of the capacitor, the resistance value can be set arbitrarily, it is possible to perform an optimal element design, and the on-voltage is stable. be.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of the main part of the vertical mMOS-FET of the present invention,
FIG. 2 is an equivalent circuit diagram, FIG. 3 is a diagram of the main construction process, FIG. 4 is a sectional view of the top of the conventional device, and FIG. 5 is an equivalent circuit diagram. 1... Source electrode, 2... Gate electrode, 3... Drain In, 4... N-base column, 5... P4.6
... P base layer, 7... Drain layer, 8... N source layer, 9... Gate polysilicon layer, 1u... Insulating oxide film, 12... PNP transistor, 13...
NPN transistor, 14...MOS-FET, 1
5...Resistor, 17...Base of transistor 13, 19...Emitter of transistor 13, or...Photomass Figure 1

Claims (1)

[Claims] 1) A first conductive type semiconductor substrate serving as a drain layer, a second conductive type base layer formed on the substrate, and a first conductive type base layer formed on the surface of the second conductive type base layer. a conductive type base layer; a second conductive type source layer formed on the first conductive type base layer;
A conductivity modulated vertical MOS comprising the source layer and a gate polysilicon layer formed via a gate oxide film on the surface which becomes a channel region between the second conductivity type base layer.
- A conductivity modulation vertical type FET, characterized in that a series resistor is provided across both the source layer and the first conductivity type base layer via an insulating oxide film with the polysilicon layer. MOS-FET. 2) A conductivity-modulated vertical MOS-FET according to claim 1, characterized in that polysilicon is used as a resistor.