JPS63792U - - Google Patents
Info
- Publication number
- JPS63792U JPS63792U JP1986092233U JP9223386U JPS63792U JP S63792 U JPS63792 U JP S63792U JP 1986092233 U JP1986092233 U JP 1986092233U JP 9223386 U JP9223386 U JP 9223386U JP S63792 U JPS63792 U JP S63792U
- Authority
- JP
- Japan
- Prior art keywords
- set value
- switch
- manipulator
- push button
- value signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 2
- 230000001105 regulatory effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Input From Keyboards Or The Like (AREA)
- Position Input By Displaying (AREA)
Description
第１図は本考案の一実施例を示すブロツク回路
図、第２図は同詳細回路図、第３図は本考案の一
実施例により発生された設定値信号によりマニプ
レータを制御するためのブロツク回路図、第４図
は従来例を示すブロツク回路図である。
１，３，４，６……スイツチ、２……積分器、
５……加算器。
FIG. 1 is a block circuit diagram showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the same, and FIG. 3 is a block diagram for controlling a manipulator by a set value signal generated by an embodiment of the present invention. Circuit Diagram: FIG. 4 is a block circuit diagram showing a conventional example. 1, 3, 4, 6...Switch, 2...Integrator,
5...Adder.
Claims (1)
作に応じて設定値信号を発生するマニプレータの
設定値信号発生回路において、押しボタンモード
とジヨイステイツクモードとを選択するスイツチ
と、押しボタンモードに際し、設定値の増加およ
び減少の方向を指令するスイツチと、前記指令ス
イツチにより規制され、かつ出力電圧制限機能を
有する積分器と、前記積分器の出力とジヨイステ
イツクレバーの操作角に対応した信号およびマニ
プレータの関節位置信号とを加算する加算器とを
備えてなることを特徴とするマニプレータの設定
値信号発生回路。 In the set value signal generation circuit of a manipulator that generates a set value signal in response to the operation of a push button and joystick lever, there is a switch that selects between push button mode and joystick mode, and a switch that increases the set value in push button mode. and a switch that commands the direction of decrease, an integrator regulated by the command switch and having an output voltage limiting function, a signal corresponding to the output of the integrator and the operating angle of the joystick lever, and a joint position signal of the manipulator. 1. A set value signal generation circuit for a manipulator, comprising: an adder for adding up and down.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986092233U JPS63792U (en) | 1986-06-17 | 1986-06-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986092233U JPS63792U (en) | 1986-06-17 | 1986-06-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63792U true JPS63792U (en) | 1988-01-06 |
Family
ID=30953753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986092233U Pending JPS63792U (en) | 1986-06-17 | 1986-06-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63792U (en) |
-
1986
- 1986-06-17 JP JP1986092233U patent/JPS63792U/ja active Pending