JPS6378500U - - Google Patents
Info
- Publication number
- JPS6378500U JPS6378500U JP17221686U JP17221686U JPS6378500U JP S6378500 U JPS6378500 U JP S6378500U JP 17221686 U JP17221686 U JP 17221686U JP 17221686 U JP17221686 U JP 17221686U JP S6378500 U JPS6378500 U JP S6378500U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- delayed signal
- delayed
- inputted
- delay circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 8
Description
第１図は本考案信号再生回路の回路構成図、第
２図はマイクジヤツクにおけるスイツチ接片の切
換状態を示す図、第３図はサラウンド時とエコー
時に左右チヤンネル出力端子に現われる各信号の
状態を示す図である。
１，２…入力端子、３…増幅器、６…第１遅延
回路、８…第２遅延回路、１０，１２…増幅器、
１１，１３…フロントのスピーカ出力端子、１４
，１５…リヤのスピーカ出力端子、１６…マイク
ジヤツク、１７…マイクプラグ、１８，１９…増
幅器、２２…抵抗。
Figure 1 shows the circuit configuration of the signal reproducing circuit of the present invention, Figure 2 shows the switching states of the switch contacts on the microphone jack, and Figure 3 shows the states of each signal appearing at the left and right channel output terminals during surround and echo. FIG. 1, 2... Input terminal, 3... Amplifier, 6... First delay circuit, 8... Second delay circuit, 10, 12... Amplifier,
11, 13...Front speaker output terminal, 14
, 15...Rear speaker output terminal, 16...Microphone jack, 17...Microphone plug, 18, 19...Amplifier, 22...Resistor.
Claims (1)
路による第１遅延信号及び該第１遅延回路及び第
２遅延回路による第２遅延信号を作成し、前記左
チヤンネルの原信号と第１遅延信号の和信号をフ
ロントの左スピーカに入力すると共に前記右チヤ
ンネルの原信号と第２遅延信号の和信号をフロン
トの右スピーカに入力し、前記第１遅延信号をリ
ヤの右スピーカに入力すると共に前記第２遅延信
号をリヤの左スピーカに入力するように構成し、
前記左右チヤンネルの原信号に対しマイクロホン
入力信号をミキシングすると共に前記第１遅延信
号を第１遅延回路の入力側にフイードバツクする
ように構成したことを特徴とする信号再生回路。 A first delayed signal by the first delay circuit and a second delayed signal by the first delay circuit and the second delay circuit are created based on the original signal of the left and right channels, and the original signal of the left channel and the first delayed signal are The sum signal is inputted to the front left speaker, the sum signal of the original signal of the right channel and the second delayed signal is inputted to the front right speaker, and the first delayed signal is inputted to the rear right speaker, and the sum signal of the right channel original signal and the second delayed signal is inputted to the front right speaker. 2 delayed signal is configured to be input to the rear left speaker,
A signal reproducing circuit characterized in that it is configured to mix a microphone input signal with the original signals of the left and right channels and feed back the first delayed signal to the input side of the first delay circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17221686U JPS6378500U (en) | 1986-11-10 | 1986-11-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17221686U JPS6378500U (en) | 1986-11-10 | 1986-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6378500U true JPS6378500U (en) | 1988-05-24 |
Family
ID=31108557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17221686U Pending JPS6378500U (en) | 1986-11-10 | 1986-11-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6378500U (en) |
-
1986
- 1986-11-10 JP JP17221686U patent/JPS6378500U/ja active Pending