JPS6377209A - Filter tuner for tuner input stage - Google Patents

Filter tuner for tuner input stage

Info

Publication number
JPS6377209A
JPS6377209A JP22315086A JP22315086A JPS6377209A JP S6377209 A JPS6377209 A JP S6377209A JP 22315086 A JP22315086 A JP 22315086A JP 22315086 A JP22315086 A JP 22315086A JP S6377209 A JPS6377209 A JP S6377209A
Authority
JP
Japan
Prior art keywords
tuning
voltage
input stage
circuit
tuner
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22315086A
Other languages
Japanese (ja)
Inventor
Tadashi Yamada
忠 山田
Akira Usui
晶 臼井
Kazuhiko Kubo
一彦 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP22315086A priority Critical patent/JPS6377209A/en
Publication of JPS6377209A publication Critical patent/JPS6377209A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the deterioration in the disturbance excluding capability by fetching an RFAGC voltage into a comparator at channel selection and using a microcomputer so as to control a D/A converter thereby compensating the deviation of tuning of an input stage tuning circuit. CONSTITUTION:A down-convert output terminal 14 of a down-convert section 3 is connected to a VIF circuit 31, where video detection is executed. Then an output being the result of video detection is fed to an RFAGC circuit 32 and an IFAGC circuit 33, in which an IFAGC voltage and an RFAGC voltage are changed depending on the quantity of a detection output. Then the RFAGC voltage is fetched by a comparator 34 at the channel selection, digital information given to a D/A conversion circuit 35 is detected by varying an output of the comparator 34 by the control of a microcomputer 17. Thus, the microcomputer 17 applies correction to input tuning voltage information of a channel being in channel selection and stored in a digital memory 16 in advance as a prescribed electric field strength so as to correct the tuning deviation of an input stage tuning circuit thereby preventing the deterioration in the disturbance excluding capability of the input stage tuning circuit.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、アップ−コンバート方式チューナの入力段フ
ィルタの同調装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a tuning device for an input stage filter of an up-conversion tuner.

従来の技術 一般に、既存の0ATVコンバータは、局部発振周波数
が受信周波数より高いアップ−コンバート方式と、既存
のテレビ受像機に接続するために特定チャンネルに変換
するダウン−コンバート方式とを縦続接続したアップ・
ダウンコンバート(U P/ D OW N  CON
 V ) 方式C’) 受信方式75: 用イラれてお
り、近年、CATVのチャンネル数の増加につれて、第
11F(fil、)が高くとられるようになり、同調素
子に可変容量ダイオードを使った電子チューナでは、第
1局部発振器と入力段同調フィルタの両者に共通の同調
電圧を加えると、両者の可変範囲の周波数の変化比が具
なるためG′こ、第1局部発振周波数を優先して同調さ
せると入力同調周波数のトラッキング誤差が大きくなる
ので、入力段フィルタとして非同調のBPFi用いるこ
とが多い。ところで一方、入力段フィルタを非同調にす
ると、混変調、相互変調等の妨害特性が悪いので、入力
段フィルタの同調を行なう手段として、第1局部発振器
の同調電圧と独立の入力段同調電圧メモリー機能を備え
た選局装置が提案されている。
Conventional technology In general, existing ATV converters are up-converters that cascade together an up-convert method in which the local oscillation frequency is higher than the receiving frequency, and a down-convert method to convert to a specific channel for connection to an existing TV receiver.・
Down conversion (UP/DOWN CON
V) Method C') Receiving method 75: In recent years, as the number of CATV channels has increased, the 11th F (fil,) has been set higher, and electronic In the tuner, when a common tuning voltage is applied to both the first local oscillator and the input stage tuning filter, the frequency change ratio in the variable range of both becomes constant. Since this increases the tracking error of the input tuning frequency, untuned BPFi is often used as the input stage filter. On the other hand, if the input stage filter is untuned, interference characteristics such as cross modulation and intermodulation will be bad, so as a means of tuning the input stage filter, an input stage tuning voltage memory independent of the tuning voltage of the first local oscillator is used. A channel selection device with this function has been proposed.

第3図は入力段フィルタの同調方式の選局装置のブロッ
ク図を示すものである。以下、図面を参照しながら従来
のアップ・ダウンコンバート方式の選局装置について説
明する。
FIG. 3 shows a block diagram of a tuning device using an input stage filter. Hereinafter, a conventional up/down conversion type channel selection device will be described with reference to the drawings.

第3図において、2はアップ−コンバート部、3はダウ
ン−コンバート部であり、ダウン−コンバート部3は前
者のアップ−コンバート部2の出力と接続されている。
In FIG. 3, 2 is an up-conversion section, and 3 is a down-conversion section, and the down-conversion section 3 is connected to the output of the former up-conversion section 2.

アンテナ入力端子4で受信された信号から、入力段同調
フィルタ5で同調した受信希望周波数(fd)が取り出
され、RFアンプ6で増幅されて、第1ミキサ7の入力
信号端子へ入る。尚、RFアンプ6には端子16よりム
GC電圧が加えられている。第1局部発振器8の同調用
の可変容量ダイオードには、局発電圧制御端子9より、
第1工Fを(fif、)としたとき、第1局部発振周波
数(f LOs)が fLo、=f工f、+fd となるよう同調電圧が加えられ、その出力が第1ミキサ
7の局発信号端子に入る。第1ミキサ7で変換された第
11F(fif、)は、第11Fアンプ10で増幅され
た後、第2ミキサ11の入力信号端子へ入る。第2局部
発振器12は、第2IFを(f、f2)としたとき、第
2局部発振周波数(fl、02)が fLo2=fift  f工f2C7はfLo2=fi
f1+fif2)で発振する固定周波数発振器であり、
その出力は第2ミキサ11の局発信号端子へ入る。第2
ミキサ11で変換された第21F信号(fif2)は第
2IFアンプ13で増幅され、端子14より出力される
The desired reception frequency (fd) tuned by the input stage tuned filter 5 is extracted from the signal received by the antenna input terminal 4, amplified by the RF amplifier 6, and input to the input signal terminal of the first mixer 7. Note that the MUGC voltage is applied to the RF amplifier 6 from the terminal 16. A variable capacitance diode for tuning of the first local oscillator 8 is connected to a local oscillator voltage control terminal 9.
When the first part F is (fif,), a tuning voltage is applied so that the first local oscillation frequency (f LOs) becomes fLo, = f part f, +fd, and its output is the local oscillator of the first mixer 7. Enter the number terminal. The 11th F (fif,) converted by the first mixer 7 is amplified by the 11th F amplifier 10 and then enters the input signal terminal of the second mixer 11. In the second local oscillator 12, when the second IF is (f, f2), the second local oscillation frequency (fl, 02) is fLo2=fift f2C7 is fLo2=fi
It is a fixed frequency oscillator that oscillates at f1+fif2),
The output enters the local oscillator signal terminal of the second mixer 11. Second
The 21st F signal (fif2) converted by the mixer 11 is amplified by the second IF amplifier 13 and output from the terminal 14.

ところで、RF同調周波数Cfd)は次のような手順で
得られる。チャンネル選局指令がマイクロコンピュータ
17に入ると、マイクロコンピュータ17は予じめ任意
のチャンネルデータとその入力段同調電圧情報を記憶し
ているデジタルメモリー16から取り出し、各チャンネ
ルに対し演算補正をする。その演算補正は次のように行
なっている。あるRF倍信号ay)を受信時の局発同調
電圧を(BTLO)、この時の入力段同調フィルタの同
調電圧を(BTRF)とし、新しく選局したRF倍信号
 fRF’)を受信時において、その局発同調電圧を(
BTLO’)  とした時、入力段同調フィルタの同調
電圧(BTRF’)を 但し、fif1’第1IP とする。以上のようにマイクロコンピュータ17で各チ
ャンネルに対し演算補正をした入力段同調電圧情報は、
D/A変換回路18でアナログ電圧に変換され、入力段
フィルタ同調電圧制御端子19から低抗器20を介して
、入力段同調フィルタ5の可変容量ダイオードに加えら
れ、希望入力同調周波数(fd )に同調するよう構成
されている。
By the way, the RF tuning frequency Cfd) can be obtained by the following procedure. When a channel selection command is input to the microcomputer 17, the microcomputer 17 retrieves arbitrary channel data and its input stage tuning voltage information from the digital memory 16 which stores the data in advance, and performs arithmetic correction for each channel. The calculation correction is performed as follows. Let the local tuning voltage at the time of receiving a certain RF multiplied signal ay) be (BTLO), the tuning voltage of the input stage tuning filter at this time be (BTRF), and when receiving the newly selected RF multiplied signal fRF'), The local tuning voltage (
BTLO'), the tuning voltage (BTRF') of the input stage tuning filter is fif1', where the first IP is fif1'. As described above, the input stage tuning voltage information that has been calculated and corrected for each channel by the microcomputer 17 is
It is converted into an analog voltage by the D/A conversion circuit 18, and is applied from the input stage filter tuning voltage control terminal 19 via the low resistor 20 to the variable capacitance diode of the input stage tuning filter 5, and is applied to the desired input tuning frequency (fd). It is configured to be in tune with the

発明が解決しようとする問題点 ところが、デジタルメモリーに記憶されたデジタル情報
は所定の電界強度における設定値であり、市場において
は、各チャンネル毎にその電界強度はまちまちであり、
チューナに加えるRFAGC電圧によpRFアンプの入
力容量が変化し、入力段同調回路の同調がズレるという
問題点があった。
Problems to be Solved by the Invention However, the digital information stored in the digital memory is a set value at a predetermined electric field strength, and in the market, the electric field strength varies for each channel.
There is a problem in that the input capacitance of the pRF amplifier changes depending on the RFAGC voltage applied to the tuner, causing the tuning of the input stage tuning circuit to shift.

本発明は、このような従来の問題点を解決するものであ
り、入力段同調回路の同調ズレを防止し同回路のもつ妨
害排除能力を劣化させないようにしようとするものであ
る。
The present invention is intended to solve these conventional problems, and is intended to prevent tuning deviation of the input stage tuning circuit and to prevent deterioration of the interference rejection ability of the input stage tuning circuit.

問題点を解決するための手段 本発明のチューナ入力段フィルタ同調装置は、可変容量
ダイオードに同調電圧を供給し、かつ第1のデジタル情
報で制御される第1のD/A変換回路と、RFAGCi
電圧と、第2のデジタル情報で制御される第2のD/ム
変換回路を通して得られる任意の基準電位であるアナロ
グ電圧とを比較する比較器を設け、チャンネルを選局し
、局部発振周波数が安定したのち、第2のD / A変
換回路を第2のデジタル情報で制御して比較器の出力を
検出し、第2のデジタル情報に応じた補正値を第1のデ
ジタル情報に加える構成となっている。
Means for Solving the Problems The tuner input stage filter tuning device of the present invention includes a first D/A conversion circuit that supplies a tuning voltage to a variable capacitance diode and is controlled by first digital information, and an RFAGCi.
A comparator is provided to compare the voltage with an analog voltage which is an arbitrary reference potential obtained through a second D/M conversion circuit controlled by second digital information, and the channel is selected and the local oscillation frequency is determined. After stabilization, the second D/A conversion circuit is controlled by the second digital information to detect the output of the comparator, and a correction value according to the second digital information is added to the first digital information. It has become.

作用 本発明の入力段フィルタ同調装置は、RFAGC電圧を
検出することによって予じめ所定の電界強度で設定され
た入力同調電圧のデジタル情報を補正し、RFアンプの
入力容量の変化による同調ズレを補なうものである。
Operation The input stage filter tuning device of the present invention corrects the digital information of the input tuning voltage, which is set in advance at a predetermined electric field strength, by detecting the RFAGC voltage, and corrects tuning deviation due to changes in the input capacitance of the RF amplifier. It is complementary.

実施例 以下、本発明の一実施例のチューナ入力段フィルタ同調
装置を図面を参照しながら説明する。尚第1図において
第3図に示す従来の構成と同一部には同一番号を付して
いる。
Embodiment Hereinafter, a tuner input stage filter tuning device according to an embodiment of the present invention will be explained with reference to the drawings. In FIG. 1, the same parts as those in the conventional configuration shown in FIG. 3 are given the same numbers.

第1図において、第2IFは国内の場合で映像キャリア
を68.75 MHz!/!:選んであり、ダウン−コ
ンバート出力端子14iV I F回路31へ接続し、
映像検波する。映像検波された出力ばRFAGC回路3
2 、IFAGC回路33へ加えられ、その検波出力の
大きさによって第2図のようにIFA(、C電圧、RF
AGG電圧が変化する。
In Figure 1, the second IF is for domestic video carriers at 68.75 MHz! /! : selected and connected to the down-convert output terminal 14iV IF circuit 31,
Detect video. Image detected output RFAGC circuit 3
2 is applied to the IFAGC circuit 33, and depending on the magnitude of its detection output, the IFA (, C voltage, RF
AGG voltage changes.

第2図の場合はIFAGC、RFAGCともり・(−ス
AGOの例を示すものである。RFA(、C電圧はチュ
ーナの端子15を介して、RFアンプ6へ加えられてい
る。またRFAGC回路32と比較器34とは、RFA
GC電圧が比較器34の一端子に印加されるように接続
され、もう一方の+端子はD/A変換回路35に接続さ
れ、マイクロコンピュータ1γで制御されるようにして
いる。
In the case of FIG. 2, an example of IFAGC, RFAGC, and (-S AGO) is shown. and comparator 34 are RFA
A GC voltage is connected to one terminal of the comparator 34, and the other + terminal is connected to a D/A conversion circuit 35, which is controlled by the microcomputer 1γ.

そして比較器34の出力がマイクロコンピュータ17の
入カポ−)Pに入力されるように接続されている。
The output of the comparator 34 is connected to the input port P of the microcomputer 17.

以上のように構成されたチューナ入力段フィルタ同調装
置において、チャンネル選局時に、RFAGC電圧を比
較器34に取り込み、マイクロコンピュータ17でD/
A変換回路36を制御し、比較器出力の変化するD/ム
変換回路35に与えるデジタル情報を検出することによ
り、マイクロコンピュータ17はデジタルメモリー16
に予じめ所定の電界強度でメモリーシている選局された
チャンネルの入力同調電圧情報に補正を加えるものであ
る。
In the tuner input stage filter tuning device configured as described above, when selecting a channel, the RFAGC voltage is input to the comparator 34, and the microcomputer 17 inputs the RFAGC voltage.
By controlling the A conversion circuit 36 and detecting the digital information given to the D/M conversion circuit 35 in which the comparator output changes, the microcomputer 17 converts the digital memory 16 into
In this method, the input tuning voltage information of the selected channel, which is stored in advance at a predetermined electric field strength, is corrected.

発明の効果 以上のように本発明のチューナ入力段フィルタ同調装置
は、チューナに加えるRFA(、C電圧してよってRF
アンプの入力容量が変化し、入力段同調がズレるのを補
正することができ、本来入力段同調回路が持つべき所望
の妨害排除能力をそこなわせることのない効果をもたら
すものである。
Effects of the Invention As described above, the tuner input stage filter tuning device of the present invention applies the RFA (, C voltage) to the tuner, thereby adjusting the RF
It is possible to correct a shift in input stage tuning due to a change in the input capacitance of the amplifier, and this provides an effect without impairing the desired interference rejection ability that the input stage tuning circuit should originally have.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるチューナ入力段フィ
ルタ同調装置のブロック図、第2図は同装置のAGO特
性図、第3図は従来の装置のブロック図である。 17・・・・・・マイクロコンピュータ、18.35・
・・・・・D/A変換回路、34・・・・・・比較器。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
FIG. 1 is a block diagram of a tuner input stage filter tuning device according to an embodiment of the present invention, FIG. 2 is an AGO characteristic diagram of the same device, and FIG. 3 is a block diagram of a conventional device. 17...Microcomputer, 18.35.
...D/A conversion circuit, 34...Comparator. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (2)

【特許請求の範囲】[Claims] (1)チューナの入力段フィルタの同調素子である可変
容量ダイオードに同調電圧を供給し、かつ第1のデジタ
ル情報で制御される第1のD/A変換回路と、第2のデ
ジタル情報で制御される第2のD/A変換回路を通して
得られるアナログ電圧とRFAGC電圧をそれぞれの入
力とする比較器とを備え、チャンネルを選局し、局部発
振周波数が安定したのちに、第2のD/A変換回路を第
2のデジタル情報で制御して前記比較器の出力を検出し
、第2のデジタル情報に応じた補正値を第1のデジタル
情報に加えるように構成したことを特徴とするチューナ
入力段フィルタ同調装置。
(1) A first D/A conversion circuit that supplies a tuning voltage to a variable capacitance diode, which is a tuning element of the tuner's input stage filter, and is controlled by first digital information, and controlled by second digital information. The second D/A conversion circuit is equipped with a comparator that takes as input the analog voltage obtained through the second D/A conversion circuit and the RFAGC voltage, and after selecting the channel and stabilizing the local oscillation frequency, the second D/A conversion circuit A tuner characterized in that the A conversion circuit is controlled by second digital information, the output of the comparator is detected, and a correction value according to the second digital information is added to the first digital information. Input stage filter tuning device.
(2)第1、第2のデジタル情報の制御、比較器出力の
検出、およびデジタル情報の演算をマイクロコンピュー
タで行なうように構成したことを特徴とする特許請求の
範囲第1項記載のチューナ入力段フィルタ同調装置。
(2) A tuner input according to claim 1, wherein the tuner input is configured such that a microcomputer performs control of the first and second digital information, detection of the comparator output, and calculation of the digital information. Stage filter tuning device.
JP22315086A 1986-09-19 1986-09-19 Filter tuner for tuner input stage Pending JPS6377209A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22315086A JPS6377209A (en) 1986-09-19 1986-09-19 Filter tuner for tuner input stage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22315086A JPS6377209A (en) 1986-09-19 1986-09-19 Filter tuner for tuner input stage

Publications (1)

Publication Number Publication Date
JPS6377209A true JPS6377209A (en) 1988-04-07

Family

ID=16793567

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22315086A Pending JPS6377209A (en) 1986-09-19 1986-09-19 Filter tuner for tuner input stage

Country Status (1)

Country Link
JP (1) JPS6377209A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657678B1 (en) 1994-02-14 2003-12-02 Hitachi, Ltd. Digital broadcasting receiver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657678B1 (en) 1994-02-14 2003-12-02 Hitachi, Ltd. Digital broadcasting receiver
US6909470B2 (en) 1994-02-14 2005-06-21 Hitachi, Ltd. Digital broadcast recorder

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