JPS6376584A - Automatic tuning system - Google Patents

Abstract

PURPOSE:To obtain an automatic tuning system that exactly performs a tuning action by constituting the system so that a channel missing is judged depending on the presence/absence of a horizontal synchronization detecting signal in case a tuning key is operated. CONSTITUTION:A key control circuit 21 judges whether horizontal synchronization detecting signals SI are continually inputted or not, and outputs key operating signals key as long as the said signals SI are inputted, accordingly, high- speed down operation is continually executed. When the counting value of a tuning voltage counter 29 passes the channel through which signals are received, the horizontal synchronization detecting signal SI goes to a level 'L', and the output of a NOR circuit 214 comes to a level 'H' to set a flip-flop 212. In association with this passing the channel, as the signals key outputted from the key control circuit 21 return to the level 'H', the output of a NAND circuit 23 comes to a level 'L', and thus the reset of a flow control counter 25 is released.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an auto-tuning method in a television receiver.

[Prior art and its problems] Conventionally, the auto-tuning method in television receivers uses an AFT-tuning method created by a reception judgment circuit shown in FIG.
Reception determination is performed using the H signal and AFT-L signal, and tuning control is performed in accordance with the reception determination signal. That is, as shown in Figure 8, the VCC power supply (-) and G
ND (+) and a resistor connected in series with the voltage 1.2.
3, the divided voltage between resistors 1 and 2 is input as a reference voltage to one terminal of comparator 4, and the divided voltage between resistors 2 and 3 is input as a reference voltage to the child terminal of comparator 5. . Further, an analog switch 6 is connected in parallel to the resistor 2, and the analog switch 6 is on/off controlled by the switch control signal φth, and the comparator 4
．． The level of the reference voltage supplied to the circuit 5 is controlled.

The AFT signal sent from the AFT detection circuit is input to the child terminal of the comparator 4 and one terminal of the comparator 5, and the output signal of the comparator 4.5 is input to one input terminal of the AND circuit 7.8. Ru. Further, the horizontal synchronization detection signal SI is input to the other input terminal of the AND circuit 7.8. Then, from the AND circuit 7, AFT-
The H signal is taken out, and the AFT-L signal is taken out from the AND circuit 8.

In the above configuration, when a tuning key such as a down key is operated, the tuning voltage is forcibly lowered by 32 steps to perform channel dropout, and the voltage is lowered at high speed until AFT-L reaches the "H" level. When the AFT-L signal goes to “H” level, the AFT-H signal goes to “H” level.
When the AFT-H signal reaches the "H" level, the switch control signal φth is set to the "H" level.
level and set the reference voltage to 1/2 Vcc. At the same time, the tuning voltage is increased by 12 steps to step back. Then, the AFT-L signal becomes “H”.
The speed increases slowly until the AFT-L signal reaches the “H” level.
``When the level is reached, the up operation is stopped and the tuning operation is finished.

Further, up-tuning is performed in the same manner.

The tuning operation is performed as described above, but conventionally, when the tuning key is operated, the tuning voltage is forcibly shifted by 32 steps to perform channel omission.

For this reason, it may not be possible to exit the channel accurately.

[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an auto-tuning method that can accurately perform a tuning operation by accurately passing through a channel when a tuning key is operated. do.

[Summary of the Invention] The present invention determines whether a channel is missing based on the presence or absence of a horizontal synchronization detection signal when a tuning key is operated, and ensures tuning operation even when the tuning key is operated between channels. It was designed so that it could be carried out.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example in which the present invention is implemented in a voltage synthesizer system. In the figure, a tuner 11 is provided with a UHF selection terminal BU, a VHF selection terminal BV, and a common terminal BM, and a changeover switch 12 for switching reception hunting is connected to these terminals. This band changeover switch 12 is configured using, for example, a slide switch, and fixed contacts a and b are connected to the terminal BU of the tuner 11.

BV and the movable contact C to the common terminal BM. The common terminal BM of this tuner 11 has, for example, +4
．． A voltage of 3V is being output. The voltage output to this common terminal BM is the contact point c of the band changeover switch 12,
The signal is sent as a UHF/VHF switching signal to the tuning control circuit 13 and the tuning voltage generation circuit 14 via a. The tuning control circuit 13 receives an up/down signal from the key operation for tuning up or tuning down, and also receives an AFT signal and a composite signal C-8 from the intermediate frequency amplification circuit 15.
YNC will be given. When a key operation signal is input, the tuning control circuit 13 controls the up key,
In response to the down key, the TU terminal outputs a PWM (pulse width modulation) signal with a resolution of, for example, 15 bits when UHF is selected and 14 bits when VHF is selected.
The terminal outputs a signal of "H" when UHF is selected, "L" on the LOW band side and "H" on the HIGH band side when VHF is selected, to the tuning voltage generation circuit 14. This tuning voltage generation circuit 14 is used for tuning control. The tuner 11 outputs a tuning voltage BT in response to a signal from the TU terminal of the circuit 13, and a band switching signal BS in response to a signal from the VL terminal.

The tuner 11 receives a band switching signal B55BU.

It performs a channel selection operation according to BV and tuning voltage BT, converts the television reception signal into an intermediate frequency signal IF, and outputs it to the intermediate frequency amplification circuit 15. This intermediate frequency amplification circuit 1
5 amplifies the intermediate frequency signal IF and outputs it to a video detection circuit (not shown), and also outputs the AFT signal and composite signal C obtained by AFT detection of the intermediate frequency signal IF.
-5YNC as described above in the tuning control circuit 13.
Output to.

Next, details of the tuning control circuit 13 will be explained with reference to FIG. In FIG. 2, 21 is a key control circuit, and this key control circuit 21 receives a tuning up signal UP in response to the operation of the tuning key.

As the tuning down signal DOWN is manually input,
A band switching signal U/V for switching the UHF/VHF band from the band switching switch 12 is input. The key control circuit 21 also receives a timing signal φ.
Tl, horizontal synchronization detection signal SI, and channel-on signal ON are input.

This key control circuit 21 outputs an up signal UP and a key operation signal KeySUHF/VHF switching signal U/V according to the input signal.The up signal UP is sent to a decoding circuit 22, and a key operation signal K e y is input to the input terminal (2) of the flip-flop 24 via the NAND circuit 23 and is also input to the reset terminal R of the flow control counter 25, and the UHF/VHF switching signal U/V is input to the comparison counter 26 and The signal is sent to the comparison circuit 27. The key control circuit 21 generates a horizontal synchronization detection signal SI when the tuning up/down key is operated.
and the key operation signal Ke in response to the channel on signal ON.
It outputs y, and is configured as shown in FIG. That is, the operation signal of the tuning up/down key is sent to the flip-flop 2 via the NOR circuit 211.
It is input to the reset terminal R of No. 12. Further, the externally inputted horizontal synchronization detection signal Sl is inputted to the data input terminal I of the flip-flop 213 and the NOR circuit 214, and is also inputted to the NOR circuit 211 via the NAND circuit 215. When the channel on signal is ON, the flip-flop 21
6, the signal read in synchronization with the timing signal φT1 and output from the X terminal is input to the other side of the NAND circuit 215. The flip-flop 213 reads the horizontal synchronization detection signal Sl in synchronization with timing T1, and
The flip-flop 21 is connected to the terminal via the NOR circuit 214.
Output to set terminal S of 2. A signal output from the X terminal of this flip-flop 212 is sent to the NAND circuit 23 as a key operation signal Key.

Therefore, the comparison counter 26 is connected to the pulse generator 2.
Basic clock pulse φ2 of about 3 MHz output from 8
is counted, and the timing signals φT1 and φ shown in FIG.
It generates T2, φM, and φK, and outputs the count value to the comparison circuit 27. In this case, the comparison counter 26 is
The timing signal φM is set to be generated 32 times during each period of the timing signal φ. Further, the count value of the tuning voltage counter 29 is given to the comparison circuit 27 as a comparison signal. This tuning voltage counter 29 has, for example, a 15-bit configuration, and the up-count and down-count modes are designated by the up/down switching signal U/D sent from the decoding circuit 22, and counts the clock pulse φck. Then, the output signal of the comparison circuit 27 becomes the TU terminal output, and the output signal of the most significant bit of the tuning voltage counter 29 and the UHF/VH
The output of the OR circuit 31 with the F switching signal U/V becomes the output of the terminal VL.

Thus, the flow control counter 25 counts the clock pulses ck and outputs the count signals Q1, Q2, Q
3 is output to the decoding circuit 22. Further, the decoding circuit 22 receives a high speed timing signal φM1 and a low speed timing signal φK. This decoding circuit 22 decodes the count output of the flow control counter 25, outputs a tuning up/down switching signal U/D, a channel-on signal ON, and an analog switch control signal φtb, and also outputs a tuning up/down switching signal U/D, a channel-on signal ON, and an analog switch control signal φtb. Outputs a tuning control signal from. The tuning control signals output from the S, l, S2, and S4 terminals are input to each input terminal I of the 4-bit latch circuit 32, and the output from the S5 terminal is input to the reset terminal R of the step-back counter circuit 33. Ru. The latch circuit 32 is composed of flip-flops 32a, 32b, and 32cl and operates in synchronization with the timing signal φT2, and the outputs of the flip-flops 32a and 32b are connected to NOR circuits 34a and 34b.
The output of the flip-flop 32d is input to the NAND circuit 35. The NAND circuit 35 receives the output signal X12 of the step-back counter circuit 33 as well as the timing signal φT1, and its output signal is sent to the NOR circuit 34a.

34b. In addition, this NOR circuit 34a134
The output of the flip-flop 36a, 3Gb is input to b. Then, the outputs of the NOR circuits 34a and 34b are taken out via the NOR circuit 37 and sent to the flow control counter 25 as a clock pulse ck.

Further, the output signal of the flip-flop 32d is inputted to the input terminal (2) of the flip-flop 38 in addition to the NAND circuit 35 described above. This flip-flop 38 operates in synchronization with the timing signal φT1, and its output signal is sent to the AND circuit 39 together with the timing signal φT2. The output signal of this AND circuit 39 is sent to the step-back counter circuit 33 and also to the OR circuit 4.
The signal is input to the set terminals S of the flip-flops 36a and 3Gb via the clock pulse φck, and is further sent to the tuning voltage counter 29 as a clock pulse φck. The step-back counter circuit 33 also has timing signals φK and UHF.
/VHF switching signal U/V is input. The step-back counter circuit 33 generates step-back signals X12 and Xn according to the input signal, and
is input to the NAND circuit 35, and the signal Xn is input to the NAND circuit 23.
Enter. The output signal of this NAND circuit 23 is sent to the flow control counter 25 and flip-flop 24 as described above. This flip-flop 24 operates in synchronization with the timing signal φT2 and outputs an output signal to the OR circuit 40.

In addition, in Fig. 2, 41 to 43 are Vcc power supply (-)
A voltage dividing resistor that divides the voltage between
Voltage divided by resistors 41 and 42 or comparator 4
4 is supplied as base I TJ5 voltage to one terminal of resistor 42.
．． The voltage divided by 43 is supplied to a child terminal of a comparator 45 as a reference voltage. Further, an analog switch 4G is connected in parallel to the resistor 42, and the analog switch 46 is on/off controlled by a switch control signal φth outputted from the decoding circuit 22.

Further, the A F T signal is input to a child terminal of the comparator 44 and one terminal of the comparator 45 . Then, the output of the comparator 44 is input to the AND circuit 47 as the AFT-H signal, and the output of the comparator 45 is input to the AF-H signal.
The signal is input to the ant circuit 48 as a TL signal. The above-mentioned AND circuits 47 and 48 output horizontal synchronization detection signals SI taken out from the comparator 49 via inverters 51 and 52.
gated by A voltage obtained by dividing the Vcc power supply voltage by a resistor 54.55 is input as a reference voltage to a child terminal of the comparator 49, and a signal detected by a horizontal synchronization detection circuit 56 is applied to one terminal via a low-pass filter 57. is input. The horizontal synchronization detection circuit 56 detects a horizontal synchronization signal by comparing the composite signal C-5YNC with an internal synchronization signal created by frequency-dividing the clock pulse φ2, and outputs it to the low-pass filter 57.

Thus, the output signal of the AND circuit 47.48 is sent to the input terminal I of the flip-flop 58.59. The flip-flops 58 and 59 are connected to the timing signal φT.
2, and sends the output signal to the flip-flop 36.
Input to recent terminals R of a and 36b.

Next, the operation of the above embodiment will be explained. In the tuning control circuit 13 shown in FIG. 2, the key control circuit 21 controls the UHF/V
Create HF switching signal U/V. .

The U/V signal output from this key control circuit 21 is
When HF is specified, it becomes "H" level, and when VHF is specified, it becomes "L" level, and is sent to the comparison counter 26 and comparison circuit 27. Switch to Therefore, when the tuning up key is operated in the receiving state of a predetermined channel, the key control circuit 21 controls the U
When the P signal goes to “L” level and the down key is operated, the U
The P signal is set to "H" level and output to the decoding circuit 22. Below, we will explain the 6th case when the down key is operated.
The explanation will be given according to the flowchart shown in the figure.

When the down key is operated, the key control circuit 21
The key operation is detected in step A1 of the figure, and the UP
The signal is converted to "H" and output to the decoding circuit 22.
P signal and output signals Ql, Q of the flow control counter 25
2. The up/down switching signal U/D is created by Q3, and the tuning voltage counter 29 is switched to the down count mode. Further, in the key control circuit 21, if the horizontal synchronization detection signal SI and the channel-on signal ON are at the "H" level when the tuning key is operated, a keystroke is input and the horizontal synchronization detection signal SI goes high. ” level, a key signal of “L” level is output. In other words, if a predetermined channel is being received, the channel-on signal ON is “H” level, and the comparator 4
Since the horizontal synchronization detection signal SI is applied from 9 to the key control circuit 21 via the inverter 5L 52, the output of the NAND circuit 215 in FIG. 3 is at the "L" level in the key control circuit 21. When the tuning key is operated in this state, the output of the NOR circuit 211 in the key control circuit 2I becomes "H" level, the flip-flop 212 is set, and the key operation signal "Key" output from the key control circuit 21 is set. It becomes L level. As a result, the output of the NAND circuit 23 becomes "H" level, and the flow control counter 25 is reset. When this flow control counter 25 is reset, the decoding circuit 22
A timing signal φM is output from the 4 terminals. This timing signal φM is read into the flip-flop 38 in synchronization with the timing signal φτ2, and opens the gate of the AND circuit 39. As a result, the AND circuit 39 outputs the timing signal φT2 as the clock pulse φck. This clock pulse φck causes the tuning voltage counter 29 to start a high-speed down operation. At this time, the key control circuit 21 determines whether the horizontal synchronization detection signal SI is still being input manually, as shown in step A3, and turns off the key operation signal Key while the horizontal synchronization detection signal SI is being input. Since it is being output, the high-speed down operation continues through the processing in steps A2 and A3. Note that during this period, since the flow control counter 25 is reset, no AFT operation is performed. Further, since the output of terminal 85 of the decoding circuit 22 is normally at the "H" level, the step-back counter circuit 33 is reset, and its X12 and Xn outputs are at the "H" level. Furthermore, the 81 terminal output of the decoding circuit 22 becomes “H”.
``Level S2 terminal output becomes ``L'' level, and AFT-
Preparations are made to accept the L signal, but at this point the flow control counter 25 does not operate.

The key control circuit 21 also receives a horizontal synchronization detection signal Sl.
is read into the flip-flop 213 and its output is “L”
level or while the horizontal synchronization detection signal SI is at the "H" level, the output of the NOR circuit 214 is held at the "L" level, and the flip-flop 212 is not set. In this state, when the count value of the tuning voltage counter 29 passes through the channel currently being received, the horizontal synchronization detection signal Sl becomes "L" level, the output of the NOR circuit 214 becomes "H" level, and the flip-flop 212 is set.

You can exit the channel you are currently receiving as described above. When the key signal output from the key control circuit 21 returns to the "H" level due to the above channel omission, the output of the NAND circuit 23 becomes the "L" level.
The flow control counter 25 is reset or canceled. Also, at this time, the set signals of the flip-flops 36a and 3Gb outputted from the OR circuit 40 are canceled, and the AFT-L signal outputted from the comparator 45 via the AND circuit 48 and the flip-flop 59 is used as the clock of the flow control counter 25. It becomes a pulse. In addition, if the state of the flow control counter 25 is "0" or "1", the decoding circuit 2
A high-speed timing signal φM is output from the 84 terminals of 2. Then, until the tuning voltage approaches the vicinity of the next channel, the tuning voltage counter 29 is controlled by the timing signal φM.
is reduced at high speed as shown in step A4. and,
Without performing this high-speed down operation, the presence or absence of AFT-L (No. 4) is determined as shown in step A5, and if there is no AFT-L signal, the process returns to step A4. Above step A4
, A5, the tuning frequency is successively lowered as shown by ■ in the AFT characteristics of FIG. When the tuning frequency becomes close to the channel due to the above tuning down operation, the AFT-L signal created by the curve of the AFT signal is sent to the flip-flop 59 through the AND circuit 48. As a result, one clock pulse ck is input to the flow control counter 25, and its count value becomes "1". Decode circuit 2
2, when the count value of the flow control counter 25 becomes "1", the tuning voltage counter 2 is activated as shown in step A6.
While continuing the high-speed down operation of step 9, the SL output is set to "L" level, the S2 output is set to "H" level, and the AF is activated.
Make it possible to detect the TH signal. In this case, until the AFT-LH signal is output from the comparator 44,
Returning to step A6, the tuning down operation is continued as shown in (■) in FIG. 7, and the optimal tuning position is once passed. In this tuning down operation, the horizontal synchronization detection signal Sl becomes "H level" in the vicinity of the channel and is input to the AND circuit 47. Therefore,
AFT created by the AFT signal curve in this state
-H signal is output from the comparator 44, this A
The FT-H signal is sent to the flip-flop 58 via the AND circuit 47, and further sent to the flow control counter 25 via the flip-flop 36a1 and the NOR circuits 34a and 37, and the count value of the flow control counter 25 becomes "2". It will be counted up. Here, the decoding circuit 22 sets the switch control signal φth to "H# level", turns on the analog switch 4G, and sets the reference voltage of the comparator 44.45 to 1/2 V c c as shown in step A8.
Switch to Further, the decoding circuit 22 sets the S1 terminal output to "H" level, the S2 terminal output to "L" level, and the S5 terminal output to "L" level, and outputs the timing signal φK from the S4 terminal. Furthermore, the up/down switching signal U
/D is set to "L" level, the tuning voltage counter 29 is stepped back, and the count value is incremented. The step back counter circuit 33 keeps the X12 output at "L" level until the tuning voltage counter 29 goes back by 12 steps as shown in step A9.
Prevent the AFT signal from going to the flow control counter 25 as a clock. Then, when the step-back counter circuit 33 performs 12 step banks (up-tuning), the X12 output becomes "H" level, and the AFT-L
A signal is sent to the flow control counter 25.

Then, in step AIO, until the progress has been made by 256 steps in UHF and 512 steps in VHF,
Proceeding to step All, the low-speed timing signal φK is output from the 84 terminal of the decoding circuit 22 to slowly increase the tuning voltage counter 29, and the presence or absence of the AFT-L signal is determined in step A12. This step AL2
If the AFT-L signal is not detected in step AIO, the process returns to step All, and the tuning-up operation continues. That is, the tuning-up operation is performed at a low speed until the AFT-L signal is detected as shown in (2) in FIG. However, 256 at UHF
Step, even if you go back 512 steps in VHF, AFT-
If the L signal is not detected, it is determined to be noise and step A is performed.
13, the analog control signal φth from the decoding circuit 22 is set to "L" level, the analog switch 46 is turned off, and the reference voltage is set to the initial value, that is, 1/3Vc,
After setting the voltage to 2/3 Vcc, the process returns to step A2 and the above-described tuning operation is performed.

When the tuning position reaches the proper position by the above tuning-up operation, the AFT-L signal is output from the comparator 45, and the flow 1 control counter 25 outputs the AFT-L signal.
The count value of is incremented to "3". As a result, the decode circuit 22 changes the switch control signal φth to “
L” level and turn off the analog switch 46,
As shown in step A14, the reference voltage is returned to the initial value, the channel-on signal ON is set to the "H2 level," and the S
4 output to “L” level. As a result, the output of the flip-flop 38 goes to "L" level, closing the gate of the AND circuit 39, inhibiting the output of the clock pulse φck, and keeping the tuning voltage counter 29 in the same state, that is, in the optimum tuning state. This completes the tuning operation.

Also, if the tuning key is operated during the above tuning operation, that is, between channels, the channel on signal ON is “L rubel”, so
In the key control circuit 21 shown in FIG. 3, the output of the NAND circuit 215 is held at the "H" level, and the output of the NOR circuit 211 is held at the "L" level regardless of the operation of the tuning key.

Therefore, even if the tuning key is operated in this state, the flip-flop 212 is not reset and no tuning key operation signal is accepted. Therefore, the tuning operation being performed at that time continues normally, and the next channel can be received correctly.

The above tuning operation has been described for the case where the down key is operated, but when the up key is operated, the same operation as when the down key is operated is performed, except that the order in which the AFT signals are detected is different.

[Effects of the Invention] As detailed above, according to the present invention, when a tuning key is operated, channel omission is determined based on the presence or absence of a horizontal synchronization detection signal. Even if a key operation is further performed between channels after the tuning is performed, the tuning operation can be performed reliably without skipping any channels.

[Brief explanation of the drawing]

Figures T51 to 7 show one embodiment of the present invention, and Figure 1 is a block diagram showing the entire circuit (14 components).
The figure is a block diagram showing details of the tuning control circuit in Fig. 1, Fig. 3 is a circuit diagram showing the configuration of the main parts in the key control circuit in Fig. 2, and Fig. 4 is a timing diagram used in Fig. 2. 5 is a diagram showing the relationship between the human output of the decoder circuit in FIG. FIG. 8 is a diagram showing a circuit configuration of a reception determining section in a conventional auto-tuning system. 11...Tuner, 12...Band selection switch,
13... Tuning control circuit, 14... Tuning voltage generation circuit, 15... Intermediate frequency amplification circuit, 21...
...Key control circuit, 22...Decoding circuit, 25...
・Flow control counter, 26... Comparison counter, 2
7... Comparison circuit, 29... Same 5 [pressure counter, 33
...Step back counter circuit, 44.45...
Comparator, 46...Analog switch, 56...
・Horizontal synchronization detection circuit, 57・Low pass filter. Applicant's agent Patent attorney Takehiko Suzue I Figure 3 Figure 5 Figure 8

Claims (1)

[Claims] An automatic system that creates AFT-H and AFT-L signals by comparing the AFT signal obtained by AFT detection of a TV video signal with a reference voltage, and performs tuning operations based on these AFT-H and AFT-L signals. The tuning method includes a means for performing a high-speed sweep when a tuning key is operated and determining a channel dropout based on the presence or absence of a horizontal synchronization detection signal, and a means for determining a channel dropout based on the presence or absence of a horizontal synchronization detection signal. -H signal or AFT-L signal detection means, and after the AFT-H signal or AFT-L signal is detected by this means, the AFT-H signal is switched to a low-speed sweep and stepped back;
An auto-tuning method characterized by comprising means for determining a tuning position by detecting a signal or an AFT-L signal.