JPS6376189A - Semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To prevent the increase in current consumption due to an erroneous memory cell by providing a means having a function to control stationarily power supply to a power source terminal independently of respective row or column units in conductive and non-conductive. CONSTITUTION:A power source terminal V102 is connected to a power source supplying control circuit P. The power source supplying control circuit P is composed of a P-type transistor Q111 and an N-type transistor Q112, and the lease terminal of the transistor Q111 is connected to one side power source terminal V112, a drain terminal is connected to the drain terminal of the transistor Q112 and a memory cell power source terminal V102, the lease of the transistor Q112 is connected to other power source terminal V111 and the gate terminal of the Q111 and Q112 is connected to a terminal C111. In the normally operatable memory cell, the terminal C111 is at a low level, the transistor Q111 is made into a conducting condition and a power source is supplied to a memory cell C. In the normally operatable memory cell, the terminal C111 is at a high level, the transistor Q111 is made into the non-conducting condition and the power source supply to the power source terminal V102 of the memory cell C is made into the interrupting condition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of Niratojo] The present invention relates to a static type semi-quadratic memory circuit, which is widely used in computer control equipment and the like.

[Conventional technology]

FIG. 2 shows a conventional example of a memory cell in a static semiconductor memory circuit. This memory cell is an example of a transistor configuration, and includes a P-type load transistor Q28.
5, Q286, N-type transfer, transistors Q203, Q204, N-type driver transistors Q201, Q202.

One end of the load transistor is connected to one power supply terminal v202 nl driver transistor Q201.

The lease terminal of Q202 is grounded to the other power supply terminal V2O1. Transfer transistor Q203
, the gate terminal of Q204 is connected to the word pin W2O1, and the source terminal of Q204 is connected to the drive)! i[D201.degree.

The read operation is as shown in the timing diagram in figure #g5.
word! Set W2O1k high level and digit line DIO
V is executed by detecting the signal level difference between I and 0102. That is, the signal level state of the digit lines D201 and D202 indicated by the broken line or solid line in FIG.

The write operation is performed as shown in the timing diagram shown in FIG. That is, the word line W2O1 is set to a high level, one of the digit lines D201 and 0202 is set to a high level, and the other is set to a low level. In the figure, the signal level states of each digit #D201 and D202 are shown by solid lines and broken lines. FIG. 4 shows an example of a conventional static type semiconductor memory circuit with redundant rows using the memory cells shown in FIG.
1 word x 4 bit redundant line'! -1114E indicates the completion of nine circuits.

Memory cells Mij (i=1 to 5.j=1 to 4) are shown in the broken line area Mk in FIG.
5), D201 uD4i1 (i=1-4).

D202iD4i2 (i=1 to 4)

In FIG. 4, if there is a problem in the memory cell M22, by deselecting the word line W402k and selecting the redundant word W405i at that time, normal 4-word x 4-bit memory circuit operation is possible.

[Problem that the invention seeks to solve]

When such word replacement is performed, the memory cell contacts N201 . If there is a leak path in W2O2, etc., the circuit operation can be determined in the case of a town, but the operating current or
The disadvantage is that first class fishing from the shore is expensive.

This invention is proposed to eliminate the drawbacks of conventional memory circuits equipped with redundant cells. Object of the present invention is to provide a static type semiconductor memory circuit with high performance. [Ninth means for solving the problem] The present invention is characterized in that memory cells are arranged in a matrix of a plurality of rows and a plurality of columns. ．． In a static semiconductor memory circuit comprising a cell and a group of redundant cells in one or more rows or columns, the power supply to the power supply terminal is constantly controlled to be conductive or non-conductive independently for each row and column. A means to have seven functions? A static semiconductor device circuit having all redundant row or redundant column cell groups.

[lol example]

The present invention will be explained below based on the drawings.

FIG. 1 shows an example of a memory cell and a power supply control circuit according to an embodiment of the present invention. The difference from the conventional example in FIG. 2 is that the power supply terminal V102 is connected to the power supply control circuit shown in broken MP.

The circuit operation sequence is the same as the conventional example in Fig. 2, and D2XX, Q2XX, and V2XX in Fig. 2 are equivalent to ADIXX, QIXX, VIXX, and V2XX in Fig. 1 respectively.
Correspondingly, the broken line section M in FIG. 2 corresponds to the broken line section C in FIG. Next, the power supply control circuit P will be explained with reference to FIG. P-type transistor Qll in power supply control circuit P
l, N-type transistor Q112 is connected to n, the lease terminal of transistor Q111 is connected to one power supply terminal V11
2, the drain terminal is connected to the drain terminal of the transistor Q112 and the memory cell tTM terminal V102, and the drain terminal of the transistor Q112 is connected to the memory cell tTM terminal V102.
Qllll to the other power terminal v111 to the lease of 112,
Q112 Connected to gate terminal if terminal C111 n
0 If the memory cell is in normal operation, the terminal C1 is at a low level, and the transistor Q111? ! - Power is supplied to the memory cell CKU in a conductive state. In a memory cell that cannot operate normally, the terminal C111 is at a high level, and the transistor Qllll - Power is supplied to the power supply terminal V102 of the memory cell C in a non-conducting state. is cut off.

Next, an embodiment of the present invention will be described with reference to FIG. 3, which is a memory circuit having a 4 word x 4 bit configuration, and includes seven redundant cell groups of 1 word x 4 bits.

The basic operation is the same as the conventional example shown in Fig. 4.
4XX, D4XX, MXX are W3XX in Figure 3
.

Compatible with CXX. 3rd Heichu Pi (0=1~5
) indicates the broken line portion Pk in FIG.

In FIG. 3, when C22 is a memory cell that cannot operate normally, when the decoding function goes low and W3O2 is instructed, the exchange of the F row is carried out to actually select the redundant word W305'. In order to cut off the abnormal current of C22, conduction of the abnormal current can be prohibited by setting the power supply control circuit P2 to a non-conducting state.

It is clear that the above explanation for the case of redundant rows can be similarly applied to the case of redundant columns.

An example of a control circuit for the control terminal C111 in FIG. 1 is shown in FIG. In FIG. 7, a terminal 711 is connected to the 11th/C11l. N-type transistor 0701, G702゜P
In this embodiment, the lease terminal of transistor G703 and transistor G703 is connected to one power supply terminal V702, and the source terminals of transistors G701 and G702 are connected to the other power supply terminal. Grounded to v701 nl transistor G7
The gate terminal of G 01 and the drain terminals of G 702 and G 703 are commonly connected. Normal state frame phase F is in a conductive state, and when processing a defective memory cell,
7 use F is placed in a non-conductive state.

〔Effect of the invention〕

As explained above, the present invention not only has the effect of suppressing the increase in current consumption due to defective memory cells, but also prevents abnormal heat generation of defective memory cells, thereby providing a highly reliable semiconductor memory circuit. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the memory cell and power supply control circuit of the present invention, FIG. 2 is a diagram of an example of a conventional memory cell, and FIG. 3 is a diagram of a semiconductor memory circuit of the present invention having a 4 word x 4 bit configuration. An example? FIG. 4 is a diagram showing a conventional example of a semiconductor memory circuit with a 47-word x 4-bit configuration, FIGS. 5 and 6 are a read operation timing diagram and shaving operation timing factors, and FIG. 7 is a power supply diagram. Control terminal control circuit example of control circuit? 0 C1l ”' Cl14 °°゛00m Storage cell
+----D2Of し ---1---
-Me Otsu diagram V7θl

Claims (1)

[Claims] In a static semiconductor memory circuit comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns and a group of redundant cells in one or more rows or columns, each row or column is independently 1. A static semiconductor memory circuit comprising a group of redundant row or column cells, characterized by comprising means having a function of controlling power supply to a power supply terminal to be constantly conductive or non-conductive.