JPS637496B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character multiplexing type time division multiplexing device used for data communications and the like.

Conventionally, this type of time division multiplexing apparatus has adopted two types: a bit multiplexing system and a character multiplexing system. Of these, the former method is capable of transmitting and receiving break signals of continuous start polarity without taking any special measures. However, in the case of the latter character multiplexing system, the start and stop bits are not transferred on the multiplexed high-speed line, and therefore they are automatically transferred in each line counterpart in the asynchronous receiver/transmitter. Start and stop bits are now added. Therefore, start and stop bits are always added to the serial data output sent from the line corresponding section, and therefore it is not possible to send a break signal that is a series of start bits, and the data at each terminal is The disadvantage was that the transmission of data could not be carried out efficiently.

SUMMARY OF THE INVENTION An object of the present invention is to provide a character multiplexing type time division multiplexing device that can improve communication efficiency in a data communication system by eliminating the above-mentioned drawbacks and making it possible to transmit and receive break signals. .

According to the present invention, in a Kirakuta multiplexing type time division multiplexing device that transfers a control signal of a corresponding line when data is not transferred, each line corresponding section is provided with a first flip-flop circuit for receiving a break signal; A second flip-flop circuit is provided for signal transmission, and the output of the output terminal Q of the first flip-flop circuit is assigned as one bit of the control signal, and is led to the data reception reset terminal of the asynchronous receiver/transmitter for input. Connect terminal D to the voltage source and input terminal R
is connected to the receive data input side of the line, the logic output of the framing error signal of the synchronous receiver/transmitter and the output signal of the receive holding register is connected to the terminal CP, and the terminal CP of the second flip-flop circuit is connected to the terminal CP. It is connected to the latch circuit of the control signal, leads the break signal bit of the control signal to the input terminal D, and connects the output of the output terminal Q to the transmission holding register empty signal output and the transmission register empty signal output of the asynchronous receiver/transmitter. At the same time, a character multiplexing time division multiplexing device is obtained, characterized in that the break signal is transmitted and received by guiding it to the serial data sending side via a logic circuit.

Next, a character multiplexing type time division multiplexing device according to the present invention will be explained in detail with reference to the drawings.

FIG. 1 schematically shows the overall configuration and operation of a conventional data communication system to which the present invention is applied. Among these, (a) is when multiplexed data is transmitted per character, and (b) is
indicates a case where there is free space in the transmission data. In Figure a, when data signals 1 and 2 constituted by start bits, data and stop bits from asynchronous terminals 3a and 4a are received by character multiplexing type time division multiplexer 1a, time division multiplexing is performed here. The signals are multiplexed and sent to the modulation/demodulation device 2a. This multiplexed signal passes through the transmission path from the modulator/demodulator 2b of the partner station to the character multiplexing type time division multiplexer 1b, where it is separated and is separated into asynchronous terminals 3a and 4b.
can be accepted. Also, in the opposite direction, the terminal 3b
and data signals 3 and 4 sent out from 4b
is multiplexed character by character and sent through the modem devices 2b and 2a, the multiplexer 1
At a, the multiplexed data is separated into character units and sent to the respective corresponding terminals 3a and 4a.

In FIG. 1b, no data is sent from the terminal 3a and the terminal 4b on the other side. In this case, multiplexers 1a and 1b multiplex control signals (transmission request signal RS, ready status signal ER, etc.) 1' and 4' sent from terminals 3a and 4b, respectively, and held in the line corresponding parts. The converted data is placed on the time slot of the relevant line and sent out to the transmission line via the modulation and demodulation devices 2a and 2b, respectively. Control signals 1' and 4' sent from opposite directions are sent to opposing modems 2b and 2, respectively.
a, and are distributed to respective line corresponding sections in multiplexers 1b and 1a, and held there. During this distribution, in order to distinguish whether the sent data is a control signal or not, a _bs bit is added before each data (character), and _bs =
In the case of 0, normal data is determined, and in the case of b _s =1, a control signal is determined.

Here, in order to facilitate comparison with the present invention,
Regarding a conventional example of a line corresponding part of a character multiplexing type time division multiplexing device having the above-mentioned signaling system,
This will be explained with reference to the block diagram in FIG. In the figure, data RD from the asynchronous terminal DTE on the local station side enters the terminal RI of the asynchronous receiver/transmitter LSI and is output in the form of parallel data.
Output from RR1 to RR8. At the same time,
A data reception identification signal DR=1 indicating that data has been received from the terminal DR is also output. The central control unit (not shown) of the character multiplexing time division multiplexer adds b _s =0 under the condition of DR=1, and
Import RR8 data. If DR = 0, add b _s = 1 and control signal RC1 from the terminal
~Receive RC8 and place it on the relevant time slot of the multiplexed data. Conversely, the multiplexed data sent from the other station is processed by the Trans mission holding register empty signal obtained from the THRE terminal of the asynchronous receiver/transmitter LSI.
Register Empty) is “1”, therefore transmission load pulse TL is applied and b _s
= 0, the input data is input to the input terminal TR
b _s = 1 input to TR1 to TR8 and output from output terminal TR0 in the form of serial data as SD
If so, consider it as a control signal and connect terminals SC1 to SC.
8 to the own terminal. Output terminal
The serial data output from TR0 is always a character with start and stop bits, or a series of stop bits. Therefore, it has been impossible to continuously generate start bits due to the functionality of the asynchronous receiver/transmitter LSI.

FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention applied to a data communication system. In this figure, if there is no stop bit SP at a predetermined position on the data RD from the asynchronous terminal on the local side, a framing error signal is output from terminal EE of the asynchronous receiver/transmitter LSI', and at that point RR1～RR
If all the outputs of 8 are "0", the break signal receiving flip-flop DF is set. In other words, it is assumed that a break signal has been sent from the terminal. When this break signal reception flip-flop DF is set, the data reception reset signal DRR is set to "1" and is applied to the terminal DRR, and the data reception identification signal DR instantaneously appeared at the terminal DR.
Reset. As a result, DR≠1, and the central control unit of the character multiplexing time division multiplexing device takes in the control signals RC1 to RC8 with b _s =1. Of these, RC8 is the output of the break signal receiving DF.

On the other hand, multiplexed data sent from the other station
TR1 to TR8 are regarded as control signals if b _s =1, and since TR8=1, flip-flop DF8' for transmitting a break signal is set. Furthermore, after both the transmission holding register empty signal from the terminal THRE and the transmission register empty signal from the terminal TRE become "1" and all the data in the asynchronous receiver/transmitter LSI' is output as SD, The AND of the output signal BRK from the flip-flop DF8' and the above two signals is established, the transmission data SD is inhibited, and as a result, a break signal with a start polarity of zero level is sent to the SD line.

Furthermore, at the timing of receiving the break signal, when the break signal from the terminal disappears and RD returns to the stop polarity SP, the flip-flop DF for receiving the break signal is reset, and b _s =1.
As such, RC8=0 is taken. By that,
The break signal transmitting flip-flop DF8' of the corresponding line corresponding section in the time division multiplexing device of the opposite station is also reset, and the break signal is released. The break signal reception timing and break signal transmission timing described above are illustrated in FIGS. 4 and 5, respectively.

As is clear from the above description, according to the present invention, a flip-flop circuit for receiving a break signal and a flip-flop circuit for transmitting a break signal are provided in each line corresponding section of a character multiplexing type time division multiplexer. , it became possible to send and receive break signals, which enabled efficient operation in data communication systems.

[Brief explanation of the drawing]

Figures 1a and 1b are block diagrams for explaining cases in which multiplexed data is transmitted character by character and cases in which there is space for transmission data, respectively, in a conventional data communication system, and Figure 2 is a conventional data communication system. FIG. 3 is a block diagram showing the configuration of an embodiment according to the present invention, and FIG. 4 shows break signal reception in the embodiment of FIG. 3. The chart showing the timing of
3 is a chart showing the timing of transmitting a break signal in the illustrated embodiment. In the figure, LSI,
LSI' is an asynchronous receiver/transmitter, DF is a flip-flop for receiving break signals, DF1~
DF8 is a flip-flop for sending control signals, DF
8' is a flip-flop for transmitting a break signal.

Claims (1)

[Claims] 1 In a character multiplexing type time division multiplexing device that transfers the control signal of the corresponding line when data is not transferred, each line corresponding section has a first flip-flop circuit for receiving a break signal and a second flip-flop circuit for transmitting a break signal. The output of the output terminal Q of the first flip-flop circuit is assigned as one bit of the control signal and is led to the data reception reset terminal of the asynchronous receiver/transmitter, and the input terminal D is connected to the voltage source. , the input terminal R is connected to the receive data input side of the line, and the logical output of the framing error signal of the synchronous receiver/transmitter and the output signal of the receive holding register is connected to the terminal CP, and the second The terminal CP of the flip-flop circuit is connected to the latch circuit of the control signal, the break signal bit of the control signal is introduced to the input terminal D, and the output of the output terminal Q is connected to the transmit holding register empty signal of the asynchronous receiver/transmitter. 1. A character multiplexing type time division multiplexing device, characterized in that a break signal is transmitted and received by guiding it to the serial data sending side through a logic circuit together with an output and a transmission register empty signal output.