JPS6374703U - - Google Patents
Info
- Publication number
- JPS6374703U JPS6374703U JP16864786U JP16864786U JPS6374703U JP S6374703 U JPS6374703 U JP S6374703U JP 16864786 U JP16864786 U JP 16864786U JP 16864786 U JP16864786 U JP 16864786U JP S6374703 U JPS6374703 U JP S6374703U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- drive circuit
- head drive
- erase
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000007493 shaping process Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
Landscapes
- Digital Magnetic Recording (AREA)
Description
第１図は本考案による磁気ヘツド駆動回路の一
実施例を示す接続図、第２図はその消去ヘツド駆
動回路の各部の信号波形図、第３図は従来例を示
す接続図、第４図は同心円状の記録トラツクの１
つを直線状にして書き込み動作のタイミングの説
明に供する略線図、第５図は磁気ヘツドの構成を
示す略線図、第６図は従来の消去信号と消去電流
の関係を示す信号波形図である。
１，１０……磁気ヘツド駆動回路、４……読出
し／書込みヘツド駆動回路、５……消去ヘツド駆
動回路、６……波形整形回路、ＨＲＷ……読出し
／書込みヘツド、ＨＥＲ……消去ヘツド、ＳＥＲ
……消去信号。
FIG. 1 is a connection diagram showing an embodiment of the magnetic head drive circuit according to the present invention, FIG. 2 is a signal waveform diagram of each part of the erasing head drive circuit, FIG. 3 is a connection diagram showing a conventional example, and FIG. 4 is one of the concentric recording tracks
Fig. 5 is a schematic diagram showing the structure of the magnetic head, and Fig. 6 is a signal waveform diagram showing the relationship between the conventional erase signal and erase current. It is. 1, 10...Magnetic head drive circuit, 4...Read/write head drive circuit, 5...Erase head drive circuit, 6...Waveform shaping circuit, HRW...Read/write head, HER...Erase head, SER
...Elimination signal.
Claims (1)
制御するようになされた電源制御部を通じて主電
源に接続された読出し／書込みヘツド駆動回路と
、 直接に上記主電源に接続され、かつ消去ヘツド
に供給する消去信号を整形する波形整形回路を有
する消去ヘツド駆動回路と を具えることを特徴とする磁気ヘツド駆動回路。[Claims for Utility Model Registration] A read/write head drive circuit connected to the main power supply through a power supply control unit configured to change and control the power supply voltage according to reading or writing, and a read/write head drive circuit connected directly to the main power supply. and an erase head drive circuit having a waveform shaping circuit for shaping an erase signal supplied to the erase head.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16864786U JPS6374703U (en) | 1986-10-31 | 1986-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16864786U JPS6374703U (en) | 1986-10-31 | 1986-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6374703U true JPS6374703U (en) | 1988-05-18 |
Family
ID=31101714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16864786U Pending JPS6374703U (en) | 1986-10-31 | 1986-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6374703U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229602A (en) * | 1987-03-19 | 1988-09-26 | Matsushita Electric Ind Co Ltd | Crosstalk reducing device |
-
1986
- 1986-10-31 JP JP16864786U patent/JPS6374703U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63229602A (en) * | 1987-03-19 | 1988-09-26 | Matsushita Electric Ind Co Ltd | Crosstalk reducing device |
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