JPS6372952U - - Google Patents

Info

Publication number
JPS6372952U
JPS6372952U JP1986167576U JP16757686U JPS6372952U JP S6372952 U JPS6372952 U JP S6372952U JP 1986167576 U JP1986167576 U JP 1986167576U JP 16757686 U JP16757686 U JP 16757686U JP S6372952 U JPS6372952 U JP S6372952U
Authority
JP
Japan
Prior art keywords
signal
branching filter
divides
outputs
frequency domain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986167576U
Other languages
Japanese (ja)
Other versions
JPH0419862Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986167576U priority Critical patent/JPH0419862Y2/ja
Publication of JPS6372952U publication Critical patent/JPS6372952U/ja
Application granted granted Critical
Publication of JPH0419862Y2 publication Critical patent/JPH0419862Y2/ja
Expired legal-status Critical Current

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  • Stereo-Broadcasting Methods (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図は第1図に示す信号処理回路周辺の詳細ブ
ロツク図、第3図a〜fは本考案における有信号
時の動作説明波形図、第4図a〜fは本考案にお
ける無信号時の動作説明波形図、第5図はFMス
テレオ波の信号分布図である。 1…FM復調器、2…低域フイルタ、3,4…
帯域フイルタ、5…fP発生器、6…同期検波回
路、7,8…分波器、9…信号処理回路、10…
マトリクス回路、15…検波器、16…信号発生
回路、17…スイツチ回路、18…加算回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
Fig. 2 is a detailed block diagram of the vicinity of the signal processing circuit shown in Fig. 1, Figs. 3 a to f are waveform diagrams explaining the operation when a signal is present in the present invention, and Figs. 4 a to f are during no signal in the present invention. FIG. 5 is a signal distribution diagram of FM stereo waves. 1...FM demodulator, 2...Low pass filter, 3, 4...
Bandwidth filter, 5... fP generator, 6... synchronous detection circuit, 7, 8... duplexer, 9... signal processing circuit, 10...
Matrix circuit, 15...Detector, 16...Signal generation circuit, 17...Switch circuit, 18...Addition circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] FM復調出力から和信号及び差信号を分離し、
これらをマトリクス処理して左耳信号及び右耳信
号を得るFMステレオ受信装置において、前記和
信号をn個の周波数領域チヤンネルに分割出力す
る第1の分波器と、前記差信号を前記第1の分波
器と同一の周波数領域チヤンネル群に分割出力す
る第2の分波器と、前記第1の分波器のチヤンネ
ルの出力信号が設定レベル以上にあるときにのみ
前記第2の分波器の対応するチヤンネルの出力信
号をマトリクス処理部に供給する信号処理回路と
を具備することを特徴とするFMステレオ受信装
置。
Separate the sum signal and difference signal from the FM demodulation output,
In the FM stereo receiving device which obtains a left ear signal and a right ear signal by matrix processing these signals, a first branching filter divides and outputs the sum signal into n frequency domain channels; a second branching filter that divides and outputs the same frequency domain channel group as the branching filter; and a second branching filter that divides and outputs the same frequency domain channel group as the branching filter; 1. An FM stereo receiving apparatus, comprising: a signal processing circuit that supplies an output signal of a corresponding channel of the receiver to a matrix processing section.
JP1986167576U 1986-10-31 1986-10-31 Expired JPH0419862Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986167576U JPH0419862Y2 (en) 1986-10-31 1986-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986167576U JPH0419862Y2 (en) 1986-10-31 1986-10-31

Publications (2)

Publication Number Publication Date
JPS6372952U true JPS6372952U (en) 1988-05-16
JPH0419862Y2 JPH0419862Y2 (en) 1992-05-07

Family

ID=31099633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986167576U Expired JPH0419862Y2 (en) 1986-10-31 1986-10-31

Country Status (1)

Country Link
JP (1) JPH0419862Y2 (en)

Also Published As

Publication number Publication date
JPH0419862Y2 (en) 1992-05-07

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