JPS637049A - Digital input synchronous circuit - Google Patents

Abstract

PURPOSE:To eliminate unnecessary state transition even variance in time exists between input signals, and to prevent chattering, or noise from the outside from generating, by latching a digital input signal with a clock signal, and waiting the transition of a state until the same state is latched in a constant period. CONSTITUTION:A digital input signal 1 is latched at a first latch circuit 2 at the leading edge of a clock signal 3, then it is changed to outputs A0 and A1. Also, it is latched at a second latch circuit 6 at the next leading edge of the clock signal 3, then it is changed to outputs B0 and B1. A third latch circuit 10 sets a coincidence signal 8, and the output of the AND circuit 9 of the clock signal 3 as the clock signal. Therefore, the output of the third latch circuit is not updated on the way of changing the digital signal, and the output of the third latch is not updated until the time of rising the clock signal 3 after completing the above change. For this reason, a synchronizing output signal transits from a state 1 to a state 4 without passing through a state 3, and simultaneous state transition can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital input synchronization circuit in digital equipment.

[Conventional technology]

A conventional circuit of this type is shown in FIG. In the figure, (l) is the digital input signal, (2) is the latch circuit, +31 is the clock signal for synchronizing the digital input signal +1) with the latch circuit (2), and 14) is the synchronous output signal of the digital input signal fi+. It is.

Next, the operation will be explained.

In the above circuit, H9L L of digital input signal 1)1
When the clock signal (3) rises from the L level to the H level, it is latched by the latch circuit (2) and output as a signal synchronized with the clock signal (31).

For example, the truth table in the case where the number of digital input signals is N-j1 is as shown in FIG.

[Problem that the invention seeks to solve]

The above circuit is effective as a synchronous circuit when each digital input signal fi+ has a meaning independently, but it is not effective when the digital input signal as a whole has a meaning. do not have.

In particular, a problem arises when the digital input signal Ill is a switch input or an input signal from outside the system, and there is a time variation between each signal.

For example, as shown in Figure 2, depending on the level of (DI, DO), (IJ, L) - state 1, (L,) () - state 2
, (H,L) heel-like IBs, (a,u)=state 4
In this case, even if the input side changes from state l to state H, the output side may not be able to make a transition in a short time. Figure 5 f
Even if you think that CD bird and Do) are changed at the same time in bl, there is a transient transition from state 1 to state 8 to state 4.

Normally, a strobe signal that determines when the signal is valid is often created to invalidate such transitions, but
If the digital input signal is from a switch input or from outside the system, it may not always be possible to create a strobe signal.

This invention was made to eliminate all of the above-mentioned problems, and aims to eliminate unnecessary transitions by synchronizing digital input signals that have time variations between each signal. .

[Means for solving problems]

The digital input synchronization circuit according to the present invention is configured to latch a digital input signal using a clock signal, and output an output signal so as to perform a state transition when the same state is latched at -periodic intervals. .

[Effect]

The comparison circuit in this invention acts to determine whether the digital input signal remains in the same state for a certain period of time, and if the state is changing, the latch output of the final stage outputs the entire previous state, and the change ends. When the change is completed, the state after the change is completed is output.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, 1) 1 is a digital input signal, (21
is the first latch circuit S tO is the clock signal, (6) is the second latch circuit which takes the output of the above first latch circuit as input and latches with the clock signal (3), and 17) is the first and second latch circuit. (8) is a coincidence signal output from the comparison circuit (7), (9) is an AND circuit that takes the logical product of the clock signal and the coincidence signal, (1)
0) is the synchronous output signal of the eighth latch circuit (41 is the digital input signal 1) which latches with the output of the AND circuit (9).

Next, the operation will be explained. Second to explain the operation
The figure shows the case where the number of digital input signals is N-8.
Timing chart '2' shows a case where an input is input at the same timing as '1'.

At the rising edge of the clock signal (3), the digital input signal +1) is latched into the first latch circuit [i+21] and becomes the outputs AO and AI. In addition, the above clock signal +3
At the next rising edge of 1, it is latched by the second latch circuit (6) and becomes the output BO, Bl. The above outputs AO, AI and BO, Bl are input to the comparison circuit (7), and if both inputs match, it outputs the entire H level, and if they do not match, it outputs the L level. Therefore, if the digital input signal is in the process of changing, the -match signal (8) is at L level. 8th
The latch circuit (lO) uses the output of the AND circuit (9) of the above-mentioned - match signal (8) and the above-mentioned clock signal +81 as a clock signal, so that during the change of the digital input signal, the output of the eighth latch circuit is not updated, and the clock signal after the change has finished (starting with the rising edge of 31, the 8th
The output of the latch circuit is updated.

From the above, the synchronous output signal transitions from state 1 to state 4 without passing through state M8.

In the above embodiment, if the time difference between the digital input signals is less than or equal to the maximum period, it is possible to change the states simultaneously without reaching an intermediate state.

The above is one specific example, and description has been given of synchronization in the case where the variation is within one clock; however, by changing the clock frequency, the variation in digital input signals that can be synchronized can be changed.

Furthermore, by increasing the number of latch circuit stages and using shift registers, the same effect can be obtained even when there are large variations.

〔Effect of the invention〕

As described above, according to the VC of the present invention, a digital input signal is latched using a clock signal, and the state transition is performed only when the same state is latched for a - period of time. This is also effective in preventing noise even when there are variations in time between input signals, such as input signals from outside the system.

[Brief explanation of drawings]

FIG. 1 is a digital input synchronization circuit diagram according to an embodiment of the present invention, and FIG. 2 is a timing chart of the above embodiment. FIG. 8 is a conventional circuit diagram, FIG. 4 is a truth table of the conventional circuit, and FIG. 4 is a timing chart. In the figure, 1)) is the digital input signal, +21 is the first latch circuit, (3) is the clock signal, (4) is the synchronous output signal, (6) is the second latch circuit, and (7) is the comparison circuit. , (8) is a - matching circuit, (9) is an AND circuit, (1o)
is the eighth latch circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) When multiple digital input signals with time variations between signals are latched into a latch circuit using a clock signal, and a method is provided to confirm that the same state continues for a certain period of time, and the same state continues for a certain period of time or more. A digital input synchronous circuit characterized by allowing state transition. (2) As a method for confirming that the same state continues for a certain period of time or more, a digital input signal is latched with continuous clock pulses, and if the latched signals match, a change in state is allowed. A digital input synchronous circuit according to scope 1.