JPS6366412B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a capacitor, and particularly to a variable capacitor whose capacitance can be changed by externally applied DC bias.

Conventionally, it has been common knowledge that variable capacitors have variable capacitance by mechanical means. In other words, when talking about a variable capacitor,
Those skilled in the art are immediately reminded of capacitors whose capacitance is varied by mechanically varying the amount of overlap between paired electrodes.

The object of the present invention is to provide a novel capacitor whose capacitance can be varied without using such mechanical means.

This invention is based on BaTiO ₃ system, Pb(Zr,Ti)O ₃ system,
This takes advantage of the fact that the dielectric properties of ceramics, such as PbTiO ₃ -based ceramics, are highly dependent on DC bias.

FIG. 1 is a circuit diagram for measuring DC bias characteristics of a capacitor for explaining the principle of the present invention. There are three capacitors C1, C2, C3 connected in series. Among them, capacitor C2 is a sample capacitor whose DC bias characteristics are measured. Sample capacitor C2
A relatively high voltage is applied between both terminals of the variable DC power supply S via a resistor R. An automatic bridge B is connected between both terminals of three capacitors C1, C2, and C3 connected in series. For example, an alternating current of 1 kHz and 1 V is applied from the automatic bridge B.

In measuring the DC bias characteristics of the sample capacitor C2, the voltage from the DC power supply S is sequentially changed and applied to the sample capacitor C2. Capacitor C
1 and C3 have a larger capacity than the sample capacitor C2, and prevent the DC voltage from the DC power supply S from being applied to the automatic bridge B. Furthermore, the resistor R has a higher impedance than the sample capacitor C2, and prevents alternating current from flowing from the automatic bridge B to the direct current power supply S.

When the capacitance of the sample capacitor C2 is changed by applying a DC voltage, this is detected by the automatic bridge B. FIG. 2 is a graph showing the relationship between applied DC voltage and capacitance change rate for a high dielectric constant ceramic material whose dielectric properties are largely dependent on DC bias. BaTiO ₃ series, Pb(Zr,Ti)O ₃ series,
For high-permittivity ceramic materials, such as PbTiO ₃ -based ceramics, whose dielectric properties are highly dependent on DC bias, the dielectric constant decreases significantly when DC bias is applied, and the rate of capacitance change is as shown in Figure 2. has a large value. If you pay attention to this,
The feasibility of creating a variable capacitor by applying a DC bias will become clear. That is, the three capacitors C1, C2, C3 shown in block 1 in FIG.
If these are integrated, one variable capacitor will be obtained. This invention is based on this principle.

FIG. 3 is an equivalent electrical circuit diagram of one embodiment of the present invention. In FIG. 3, capacitors corresponding to those shown in FIG. 1 are designated using similar reference numerals. As is clear from FIG. 3, this variable capacitor has a first external terminal T1 and a second external terminal T1.
2, a third external terminal T3 and a fourth external terminal T4. Of these, the first external terminal T1 and the fourth
The external terminal T4 corresponds to the terminal connected to the automatic bridge B in FIG. 1, and is a terminal from which the variable capacitance is taken out. In other words, it is the original terminal of a conventional variable capacitor. The second external terminal T2 and the third
The external terminal T3 is a terminal to which a DC bias is applied. The capacitance taken out between the first external terminal T1 and the fourth external terminal T4 is obtained from the first capacitor C1, the second capacitor C2, and the third capacitor C3 that are connected with direct current. In this case, the capacitance obtained from the second capacitor C2 is selected to be smaller than each of the capacitances obtained from the first capacitor C1 and the third capacitor C3, and more preferably, it is selected to be extremely small. , among the capacitances connected in series, the capacitances of the first and third capacitors C1 and C3 can be almost ignored;
The capacitance of the second capacitor C2 makes the largest contribution to the capacitance taken out to the external terminals T1 and T4. Therefore, the change in the variable capacitance of the second capacitor C2, which is made variable by the DC bias applied from the second and third external terminals T2 and T3, is almost unchanged from the first and fourth external terminals T1 and T4. can be taken out. In this sense, if a high dielectric constant ceramic material whose dielectric characteristics are highly dependent on DC bias is used as the dielectric material constituting at least the second capacitor C2, a capacitor with a wide variable capacitance range can be obtained. It has been experimentally confirmed that a variable capacitor with a variable capacitance range of nearly one order of magnitude can be obtained by selecting a dielectric material. Note that the dielectric material forming the first capacitor C1 and the third capacitor C3 may be the same as or different from the dielectric material forming the second capacitor C2. because,
Among the first to third capacitors C1 to C3 connected in series, the first and third capacitors C1
The capacitances of C3 and C3 are larger than that of the second capacitor C2, and therefore the impedance defined by (1/ωC) becomes smaller.
Even if the dielectrics constituting the third capacitors C1 and C3 are made of dielectric materials whose dielectric characteristics are highly dependent on DC bias, if we look at the series circuit of the first to third capacitors C1 to C3, as described above, , the capacitance provided by the first and third capacitors C1 and C3 is almost negligible.

An example of the mechanical structure of a capacitor that achieves the circuit of FIG. 3 will be described below.

FIG. 4 is a cross-sectional view of one embodiment of such a mechanical structure. FIG. 4 shows a capacitor having a laminated structure. 5 and 6 are plan views showing internal electrode patterns used in the laminate shown in FIG. 4. FIG.

In the laminate shown in FIG.
1, a second capacitance 12 and a third capacitance 13 are formed. First and third capacitance 11, 13
5 and 6, respectively.
It consists of internal electrodes 16 and 17 formed on ceramic sheets 14 and 15 shown in the figure, respectively.
The internal electrode 16 shown in FIG.
It is formed so as to extend to the left edge as shown in Figure 4. The internal electrode 17 shown in FIG. 6 is formed to extend to the right edge of the ceramic sheet 15. The portions forming the first and third capacitances 11 and 13 are made of the ceramic sheet 1 shown in FIG.
4 and the ceramic sheets 15 shown in FIG. 6 are alternately stacked. Second capacitance 12
The portion forming the electrode is composed of one ceramic sheet or a stack of multiple ceramic sheets without internal electrodes. In this way, the first to third capacitors 11, 12, 1
The dielectric 18 forming 3 is obtained as a single piece by means of a laminate. A first outer conductive film 19, a second outer conductive film 20, a third outer conductive film 21, and a fourth outer conductive film 22 are formed on the end face of the dielectric 18, respectively. The first external conductive film 19 is electrically connected to one of the internal electrodes 16 in the part where the first capacitance 11 is formed, and the second external conductive film 20 is electrically connected to the other internal electrode 16 in the part where the first capacitance 11 is formed. The third external conductive film 21 is electrically connected to one of the internal electrodes 16 in a portion forming the third capacitance 13, and the fourth external conductive film 22 is electrically connected to each internal electrode 17. The portion forming the capacitance 13 is electrically connected to the other internal electrode 17 . Each external conductive film 19, 20, 21, 22 is connected to each external terminal T1, T2, T3,
This corresponds to T4. Therefore, the first and third capacitances 11 and 13 are configured as parallel capacitances formed between a plurality of pairs of internal electrodes 16 and 17, respectively. The second capacitance 12 is formed between a pair of internal electrodes 16a and 17a located at the end and separated by a relatively large interval. From this configuration, the relationship that the second capacitance 12 is smaller than either of the first and third capacitances 11 and 13 can be easily obtained.

In particular, it is necessary that the dielectric material for forming at least the second capacitance 12 be made of a ceramic material whose dielectric properties are highly dependent on DC bias.
Therefore, the ceramic sheets used for laminating the dielectric 18 include the aforementioned BaTiO ₃ type, Pb(Zr,
Those based on Ti)O ₃ or PbTiO ₃ are advantageously used. The same applies to the following examples.

The external conductive films 19, 20, 21, and 22 are formed, for example, by applying and baking silver paste. In order to facilitate this coating process, the following structure is proposed.

FIG. 7 is a perspective view of another embodiment of a mechanical structure implementing the circuit of FIG. 3; Figures 8 to 1
1 is a plan view showing an internal electrode pattern used in the laminate shown in FIG. 7. FIG. Dielectric 1 shown in FIG.
The internal cross-sectional structure of 8 is substantially similar to that shown in FIG. In this embodiment, the configuration in which each internal electrode is drawn out to the end face of the dielectric 18 is improved.

As shown in Figures 8 to 11, respectively,
Each internal electrode 27, 28, 29, 30 formed on the ceramic sheets 23, 24, 25, 26 is
It has four types of patterns. The internal electrode 27 shown in FIG. 8 is formed so as to extend only above the left edge of the ceramic sheet 23. As shown in FIG. The internal electrode 28 shown in FIG. 9 is formed so as to extend only to the upper right edge of the ceramic sheet 24. The internal electrode 29 shown in FIG. 10 is formed so as to extend only below the right edge of the ceramic sheet 25. As shown in FIG. The internal electrode 30 shown in FIG. 11 is formed so as to extend only below the left edge of the ceramic sheet 26. In the portion forming the first capacitance 11, the ceramic sheets 23 of FIG. 8 and the ceramic sheets 24 of FIG. 9 are alternately laminated. In the portion forming the second capacitance 12, ceramic sheets without internal electrodes are laminated as in the previous embodiment. In the portion forming the third capacitor 13, the ceramic sheets 25 shown in FIG. 10 and the ceramic sheets 26 shown in FIG. 11 are alternately laminated. When configured in this way, as shown in FIG. 7, the internal electrodes 27 and 30 are exposed along two rows spaced apart from each other on one end surface of the dielectric 18, and the internal electrodes 27 and 30 are exposed along two rows separated from each other. On the other end surface, internal electrodes 28 and 29 are exposed along two rows spaced apart from each other. First to fourth external conductive films 19, 20, 21, 22 are formed by coating and baking along each row in which exposed portions of internal electrodes 27, 28, 29, 30 are located. Formation of two external conductive films on each end surface of the dielectric 18 is performed on each internal electrode 17.
Because of the manner in which the silver paste is exposed, it is possible to maintain a predetermined distance or more, thereby facilitating the application work of silver paste and the like.

FIG. 12 is a perspective view of yet another embodiment of a mechanical structure that achieves the circuit of FIG. This twelfth
The laminated form of the ceramic sheets in the dielectric 18 shown in the figure is also substantially the same as that shown in FIG. In this embodiment as well, the drawing state of the internal electrodes on each ceramic sheet has been modified. 13 to 16 are plan views showing internal electrode patterns used in the laminate shown in FIG. 12.

As shown in FIGS. 13 to 16, the internal electrodes are formed in four types of patterns. That is, each internal electrode 31, 32, 33, 34 is entirely connected to each ceramic sheet 35, 36, 37, 38.
It is pulled out to the lower edge according to each figure. This drawing is performed partially at specific positions on each lower edge. Each internal electrode 31, 32,
The drawer positions of the ceramic sheets 33 and 34 are sequentially shifted from the left side to the right side in the figure on the respective lower edges of the ceramic sheets 35, 36, 37, and 38. Therefore, on one end surface of the dielectric 18 shown in FIG.
1. Internal electrodes 32, 33, and 34 are exposed. These internal electrodes 31, 32, 3
At the end surface of the dielectric 18 where 3 and 34 are exposed,
first to fourth external conductive films 19, 20, 2 so as to be electrically connected to respective selected internal electrodes;
1 and 22 are formed.

According to the mechanical structure shown in FIG. 12, all the outer conductive films 19, 20, 21, 22 are aligned on the same plane, making direct connection to a printed circuit board (not shown) extremely efficient. Ru. Furthermore, the method for facilitating the application of silver paste or the like for forming the external conductive films 19, 20, 21, and 22 is the same as in the embodiment shown in FIG.

FIG. 17 is a cross-sectional view of yet another embodiment of a mechanical structure that achieves the circuit of FIG. FIG. 18 is a perspective view of the structure of FIG. 17. In this embodiment, the first
The portions forming the third capacitors 11 and 13 are located side by side with each other. This embodiment also consists of a laminate of ceramic sheets with a predetermined internal electrode pattern. FIGS. 19 to 21 are plan views showing internal electrode patterns used in the laminate of this embodiment.

As shown in FIGS. 19 to 21, the internal electrodes are typically formed in three types of patterns.
In the case of FIG. 19, two
Internal electrodes 40 and 41 are formed at intervals from each other. Each internal electrode 40, 41 is drawn out to the lower edge of the ceramic sheet 39 as shown in the figure.
The position of each of the drawers is selected to be offset to the outside of the lower edge of the ceramic sheet 39. In the case of FIG. 20 as well, two internal electrodes 43 and 44 are formed on the ceramic sheet 42 at a distance from each other. Each internal electrode 43, 44 is drawn out at a position relatively inside the lower edge of the ceramic sheet 42 as shown in the figure. The ceramic sheet 45 shown in FIG. 21 has one internal electrode 4 extending over almost the entire surface.
6 is formed.

As shown in FIG. 17, the internal electrode 4 of FIG.
A ceramic sheet 45 having a diameter of 6 is first placed to form the bottom, and one or more ceramic sheets on which no internal electrodes are formed are stacked on top of the ceramic sheet 45, and then the internal electrodes 45 of FIG.
3, 44 and the 19th ceramic sheet 42
Ceramic sheets 39 having internal electrodes 40 and 41 shown in the figure are alternately laminated. In the dielectric body 18 configured in this way, the first capacitance 11 is formed by a plurality of pairs of internal electrodes 40 and internal electrodes 43, and the third capacitance 13 is formed by a plurality of pairs of internal electrodes 41 and internal electrodes 43. It is formed by the electrode 44.
The second capacitance 12 is generated by the capacitance between the lowest internal electrode 43a and the internal electrode 46, and the series connection of the capacitance between the lowest internal electrode 44a and the internal electrode 46. configured.

As shown in FIG. 18, on one end surface of the dielectric 18, an internal electrode 40, an internal electrode 43, an internal electrode 44, etc. And the internal electrodes 41 are exposed, and the internal electrodes 46 are not exposed. Each exposed internal electrode 40, 43, 44, 4
1 in a particular area so as to be electrically connected to the first
to fourth external conductive films 19, 20, 21, and 22 are formed, respectively.

In the embodiment shown in FIG. 17, etc., as in the embodiment shown in FIG.
Coating for forming 0, 21, and 22 becomes easy. In addition, in the embodiment shown in FIG. 17 etc., the dielectric 18 can be made thinner.

FIG. 22 is an equivalent electrical circuit diagram of another embodiment of the invention. According to this circuit diagram, it is understood that a resistor R is added compared to the circuit diagram of FIG. 3 described above. This resistor R corresponds to the resistor R in FIG. This embodiment attempts to provide an integrated variable capacitor that includes a resistor R in addition to block 1 of FIG.

FIG. 23 is a plan view of one embodiment of a mechanical structure that achieves the circuit of FIG. 22. In FIG. 23, the stacked state inside the dielectric 47 can be considered to be the same as that of the dielectric 18 in FIG. 7, for example.
Therefore, two external conductive films are formed on each of the two mutually opposing end surfaces of the dielectric 47. The first external conductive film 48 corresponds to the first external conductive film 19 in FIG. , 22. Of these, the second external conductive film 49 is the first external conductive film in FIG.
This corresponds to a conductor connecting between the capacitor C1 and the second capacitor C2. This second external conductive film 49
is formed extending to the upper surface of the dielectric 47.
A resistor film 52 connected to the second external conductive film 49 is formed on the upper surface of the dielectric 47 by coating and baking. The external terminal conductive film 53 is also formed directly on the upper surface of the dielectric 47 and is electrically connected to the resistor film 52. In such a configuration, the second
To show the correspondence with the circuit diagram in Figure 2, the first external terminal T
1 is connected to the first external conductive film 48, the second external terminal T2 is connected to the external terminal conductive film 53, and the third external terminal T3 is connected to the third external terminal conductive film 53.
The fourth external terminal T4 is connected to the external conductive film 50, the fourth external terminal T4 is connected to the fourth external conductive film 51, and the resistor R is connected to the resistor film 52.
correspond to each.

According to the embodiments shown in FIGS. 22 and 23, when used as a variable capacitor, there is no need to externally attach a resistor element corresponding to the resistor R in FIG. 1, which is extremely advantageous in practice. Note that the resistor film 52 and the external terminal conductive film may be formed on any surface or position of the dielectric 47. Furthermore, forming the resistor film directly on the dielectric material is also possible for the structures shown in FIGS. 4, 12, and 18.

24 to 26 are plan views of still other embodiments of the mechanical structure of the present invention. In FIGS. 24 to 26, each dielectric 54, 55,
Each external conductive film 57, 5 formed on the surface of 56
8 and 59 have terminal leads 60, 61, and
62 is electrically connected. These embodiments are not limited to the so-called chip type that does not have terminal leads;
This shows that the present invention can also be applied to a capacitor having terminal leads. Also, the second
In FIG. 4, each conductive film 57 is formed on each of the four end faces. As can be seen from this example,
The manner in which the internal electrodes are drawn out, that is, the position at which the external conductive film is formed, can be changed as appropriate depending on the application.

As described above, according to the present invention, a novel capacitor whose capacitance is variable by applying a DC bias can be obtained. This capacitor can be expected to have various uses as an alternative to conventional mechanical variable capacitors. For example, mechanical variable capacitors are not suitable for frequently changing their capacitance, and are often used in so-called semi-fixed capacitors. That is, with conventional mechanically variable capacitors, if you want to change the capacitance, you have to go to the trouble of operating the capacitance at the location where it is installed. On the other hand, according to the capacitor of the present invention, since the capacitance is made variable by direct current bias, so-called remote control is possible, and it is extremely suitable for applications where the capacitance needs to be changed frequently. It can also be used as an impedance variable means for a stabilized power source. That is, the capacitance of this capacitor can be changed due to voltage fluctuations, and since the impedance changes according to this capacitance, it can be used as an impedance variable means. In addition, conventionally, in an LC circuit composed of a coil and a capacitor, the resonance characteristics were adjusted by making the inductance component variable; however, instead of this, by making the capacitance variable, the resonance characteristics It also becomes possible to make adjustments. Further, in the capacitor of the present invention, the variable range and rate of change of the capacitance can be easily changed by selecting the material constituting the dielectric material and designing the layer thickness of the capacitance forming portion.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram for measuring DC bias characteristics of a capacitor for explaining the principle of the present invention. FIG. 2 is a graph showing the relationship between applied DC voltage and capacitance change rate for a high dielectric constant ceramic material whose dielectric properties are largely dependent on DC bias. FIG. 3 is an equivalent electrical circuit diagram of one embodiment of the present invention. FIG. 4 is a cross-sectional view of one embodiment of a mechanical structure that achieves the circuit of FIG. 5 and 6 are plan views showing internal electrode patterns used in the laminate shown in FIG. 4. FIG. FIG. 7 is a perspective view of another embodiment of a mechanical structure that achieves the circuit of FIG. 8 to 11 are plan views showing internal electrode patterns used in the laminate shown in FIG. 7. FIG. FIG. 12 is a perspective view of yet another embodiment of a mechanical structure that achieves the circuit of FIG. 13 to 16 are plan views showing internal electrode patterns used in the laminate shown in FIG. 12. FIG. 17 is a cross-sectional view of yet another embodiment of a mechanical structure that achieves the circuit of FIG. FIG. 18 is a perspective view of the structure of FIG. 17. FIGS. 19 to 21 are plan views showing internal electrode patterns used in the laminates shown in FIGS. 17 and 18. FIG. 22 is an equivalent electrical circuit diagram of another embodiment of the invention. FIG. 23 is a plan view of one embodiment of a mechanical structure that achieves the circuit of FIG. 22. 24 to 26 are plan views of still other embodiments of the mechanical structure of the present invention. In the figure, C1, C2, C3 are capacitors,
S is a variable DC power supply, R is a resistor, T1 is a first external terminal, T2 is a second external terminal, T3 is a third external terminal,
T4 is the fourth external terminal, 11 is the first capacitance, 12
is the second capacitance, 13 is the third capacitance, 14,1
5, 23, 24, 25, 26, 35, 36, 3
7, 38, 39, 42, 45 are ceramic sheets, 16, 17, 27, 28, 29, 30, 3
1, 32, 33, 34, 40, 41, 43, 4
4, 46 are internal electrodes, 18, 47, 54, 55,
56 is a dielectric, 19 and 48 are first external conductive films, 2
0, 49 are second external conductive films, 21, 50 are third external conductive films, 22, 51 are fourth external conductive films, 52 are resistor films, 53 are external terminal conductive films, 57, 5
8 and 59 are external conductive films, and 60, 61, and 62 are terminal leads.

Claims (1)

[Scope of Claims] 1. A dielectric made of a high permittivity ceramic material; first, second, third, and fourth external terminals extending to at least the outer surface of the dielectric; 2. first, second, third and fourth conductors electrically connected to third and fourth external terminals, respectively; the first conductor and the second conductor in the dielectric;
a first capacitance formed between the second conductor and the third conductor in the dielectric;
a second capacitance formed between the third conductor and the fourth conductor in the dielectric;
and a third capacitance formed between a conductor and a conductor, wherein the second capacitance is smaller than either of the first and third capacitances, and the dielectric at least a portion providing the second capacitance is made of a material whose dielectric properties are highly dependent on DC bias, the second and third external terminals are terminals to which a DC bias is applied, and the first and third external terminals are terminals to which a DC bias is applied. The fourth external terminal is a capacitor that is used as a terminal to take out the variable capacitance. 2. The capacitor of claim 1, wherein each of the first, second, third and fourth conductors includes a pair of internal electrodes formed in the dielectric. 3. The distance between the pair of internal electrodes forming the first and third capacitances is selected to be smaller than the distance between the pair of internal electrodes forming the second capacitance. Capacitor described in item 2. 4. The capacitor according to claim 2 or 3, wherein a plurality of pairs of internal electrodes forming the first and third capacitances are sequentially stacked and connected in parallel. 5. The method according to claim 3 or 4, wherein one of the paired internal electrodes forming the first and third capacitances also serves as the internal electrode forming the second capacitance. capacitor. 6. The capacitor according to any one of claims 2 to 5, wherein there are two pairs of internal electrodes forming the second capacitance and are connected in series with each other. 7. The internal electrode is exposed on the end surface of the dielectric, and each external terminal includes a conductive film formed on the end surface of the dielectric, and by selecting a pattern for forming the conductive film, each external terminal can be connected to the external terminal. 7. A capacitor according to any one of claims 2 to 6, wherein each of the conductors to be connected is selected. 8. The capacitor according to claim 7, wherein each of the external terminals includes a terminal lead electrically connected to each of the conductive films. 9. The capacitor according to any one of claims 1 to 8, wherein the second or third conductor includes a resistor. 10. The capacitor according to claim 9, wherein the resistor is a resistor film formed on the surface of the dielectric.