JPS6365270B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image information processing device for a facsimile device, and more particularly to a device suitable for application to a two-dimensional sequential processing encoding and decoding system for facsimile data. Generally, in order to improve transmission efficiency by focusing on the redundancy of facsimile data, it is most effective to perform redundancy suppression coding, that is, compression coding. The two-dimensional sequential processing encoding method applied in the present invention will be briefly explained below. This method uses the information of the previous scan line that has already been encoded to encode the current scan line.
Focusing on the fact that it has a dimensional spread and a strong correlation in the vertical and horizontal directions, we use the position of the information change point (white → black or black → white) of each scan line as a reference to calculate the previous scan line or the same scan. There is a change point relative address encoding method that encodes using a relative distance from a change point on a line. Here, we will examine the control procedure for conventional data compression encoding using the CCITT (International Telegraph and Telephone Consultative Committee) G3 standard (modified read system) as an example of this compression encoding method. Figure 1 diagrammatically shows an example of image information, where Figure 1A is the reference scanning line information RSD and Figure 1B is the reference scanning line information RSD.
is encoded scanning line information CSD, the square with diagonal lines in the figure is black pixel information, and the other squares are white pixel information, which is the processing target scan start point of reference scanning line information RSD and encoded scanning line information CSD. are respectively b ₀ and a ₀ , the first pixel changing point in the reference scanning line information RSD is b ₁ , the second pixel changing point is b ₂ , and the first pixel changing point in the encoded scanning line information CSD is a ₁ , Let the two-pixel change point be _a2 . Now, when encoding image information as shown in FIG. 1 using a conventional image information processing device, a pixel change detector is used to detect pixel changes in reference scanning line information RSD and encoded scanning line information CSD. Based on the detection outputs of these detectors, the state of the image information is sequentially determined by a counter etc. that counts the relative distance of the pixel change point (l in Fig. 1) of the reference scanning line information RSD and the coded scanning line information CSD. Encoding is performed while monitoring according to the procedure shown in the flowchart of FIG. That is, the pixel change detector detects the first pixel change point a ₁ in the encoded scanning line information CSD, the first pixel change point b ₁ and the second pixel change point in the reference scanning line information RSD.
When each pixel change point _b2 is detected, if the pixel change point _b2 is detected before the pixel change point _a1 , that is, the second pixel change point in the reference scanning line information RSD
If the pixel change point b ₂ is on the left side of the first pixel change point a ₁ in the encoded scanning line information CSD, encoding is performed as a pass mode, otherwise it is encoded by the above counter. Counting the relative distance l between the first pixel change point a ₁ in the scanning line information CSD and the first pixel change point b ₁ in the reference scanning line information RSD,
It is checked whether the counted value is "3" or less.
As a result, if the above-mentioned count value is "3" or less, encoding is performed in vertical mode, and if the above-mentioned count value is "4" or more, the encoded scanning line information is
After detecting the second pixel change point _a2 in CSD, encoding is performed in horizontal mode. When these encodings are performed, the above processing is repeated by setting the next pixel as the next processing target scan starting point a ₀ or b ₀ respectively. In this method, the sign of the vertical mode is that when the relative distance l between the pixel change points a ₁ and b ₁ is 0 (V ₀ ), the pixel change point a ₁ is on the right side of b ₁ , and when this relative distance l is "1" (V _R1 ) to "3" (V _R3 ),
When the above pixel change point a ₁ is on the left side of b ₁ and this relative distance l is "1" (V _L1 )
A total of 7 types of codes are prepared, each indicating when the value is "3" to "3" (V _L3 ), and the horizontal mode code is from the processing target scanning start point a ₀ to the first pixel change point a in the encoded scanning line information CSD. ₁ and a plurality of codes corresponding to the distances from the first pixel change point _a1 to the second pixel change point _a2 are prepared. Incidentally, in the case of the image information shown in Figure 1, the above pixel change point
b ₂ is on the right side of a ₁ , and the above pixel change point a ₁ is b ₁
Since this relative distance l is "2" on the right side of , it is encoded as a code indicating "V _R2 " in the vertical mode. However, in order to perform two-dimensional sequential data compression encoding, when using such a conventional device, it was necessary to monitor each pixel change point in image information and their relative distances as described above. Therefore, a large-sized device was required, and the control procedure was complicated as shown in FIG. Furthermore, with this conventional device, there is a natural limit to the processing speed for encoding due to the same reasons as mentioned above, and it will not be possible to meet the demands of future facsimile devices that aim to achieve higher transmission speeds than ever before. It's not a thing. This invention has been made in view of the above circumstances, and it is possible to simplify the control procedure and increase the processing speed, especially when performing two-dimensional sequential processing encoding of facsimile data. It is an object of the present invention to provide an image information processing device that can be downsized and also has a decoding function. That is, the present invention sequentially latches a memory in which data corresponding to various changes in image information are stored in advance, read data from the memory, and a change detection signal for the image information, and uses the latch output as an address signal for the memory. A sequential circuit with a latch circuit constitutes an encoding/decoding determining means, and compression encoding and decoding of facsimile data are performed based on the read data of the memory when the image information takes a predetermined change mode. In particular, when performing the above-mentioned two-dimensional sequential processing encoding, the above-mentioned relative pixel change detection function between the encoded scanning line information and reference scanning line information and the pixel change relative distance detection function are also required. This is integrated into the encoding/decoding determining means, and the above objective can be satisfactorily achieved. DESCRIPTION OF THE PREFERRED EMBODIMENTS An image information processing apparatus according to the present invention will be described in detail below with reference to embodiments shown in the accompanying drawings. FIG. 3 shows the configuration of an embodiment of the image information processing apparatus according to the present invention. In this embodiment device, flip-flop 1
1 and 12 are standards for determining the processing target scan starting point of the scanning line information obtained by predetermined image scanning in facsimile communication based on the set command signal SE ₁ or SE ₂ applied from the control processing unit 50. It temporarily stores pixel information,
For example _, for image information as shown in FIG.
2 is the processing target scanning start point b ₀ of the reference scanning line information RSD
It operates to temporarily store the contents of each. Further, exclusive OR circuits 21 and 22 detect changes in pixel information in encoded scanning line information CSD and reference scanning line information RSD, and exclusive OR circuit 21 detects changes in pixel information in encoded scanning line information CSD and reference scanning line information RSD. A signal CC that successively compares the contents of each pixel information of the encoded scanning line information CSD that is added sequentially, and has a logical value of "0" if these contents are equal, and a logical value of "1" if they are different.
operates to output to the latch circuit 31,
The exclusive OR circuit 22 is connected to the flip-flop 12.
The content BR stored in the BR and the content of each pixel information of the reference scanning line information RSD that are sequentially added are successively compared, and as mentioned above, if these contents are equal, the logic value becomes "0", and if they are different, the logic value is It operates to output a signal CR having a value of "1" to the latch circuit 31. Furthermore, the contents stored in the flip-flop 11
Contents stored in BC and flip-flop 12
BR, that is, each processing target scan start point a ₀ in encoded scan line information CSD and reference scan line information RSD
If the contents of and b ₀ are different, the code and b
The decoding process is also somewhat different, and in this embodiment, an exclusive OR circuit 23 detects whether the contents of the processing target scanning start points a ₀ and b ₀ are equal. In other words, exclusive OR circuit 2
3 is the content stored in flip-flop 11
BC and contents stored in flip-flop 12 BR
ROM, which will be described later, sets the logical value of this output signal CP to "1" when the contents are different.
(Read-only memory) Operates to perform so-called page switching of 32 and correct data. The latch circuit 31 and the ROM 32 form a coding/decoding determining means which is the main part of the apparatus of this embodiment, and the exclusive OR circuits 21 and 2
The output signals CC and CR of 2 and the data D read from the ROM 32 are sequentially latched in the latch circuit 31, and the next read data of the ROM 32 is latched based on the contents of the latched signals CC and CR and the data D. The configuration is such that addresses are determined sequentially. Note that the latch circuit 31 is driven and controlled by the control processing section 50, and its latch contents are cleared based on an initialization signal IN that is applied every time one encoding or decoding starts.
The above latch operation is repeated based on the load signal LD applied in response to the scanning of the image information. The ROM 32 also uses the signals CC and CR latched by the latch circuit 31 as address signals.
When the content of the read data D of the ROM 32 satisfies a predetermined condition for being encoded or decoded, the read data D indicates the encoded code or decoded data, and the logic of a predetermined bit f of this output bit is It is assumed that data having a value of, for example, "1" is stored in advance. Therefore, when encoding image information as shown in FIG. 1 using the modified read method described above, (1) the latch circuit 31 corresponding to pixel scanning and
In the process of sequential operation with the ROM 32, when it is detected that the second pixel change point _b2 of the reference scanning line information RSD is to the left of the first pixel change point _a1 of the encoded scanning line information CSD, that is, signal
After the logical value of CR changes from “0” → “1” → “0”, the logical value of signal CC changes from “0” →
When the logic value of the signal CC becomes "1", the output bit f of the ROM 32 changes to the logic value at the time it is accessed by the address signal (output of the latch circuit 31) when the logic value of the signal CC changes from "0" to "1". The value becomes "1", and the data D has contents indicating a "pass mode code". In the above process, until the logical value of the signal CC changes from "0" to "1", the read data D of the ROM 32 is used by the latch circuit 3 as data indicating the transition of the signal CR.
They are sequentially latched to 1 and fed back to the ROM 32 as part of the address signal. (2) The latch circuit 31 corresponding to pixel scanning and
In the process of sequential operation with the ROM 32, encoded scanning line information CSD and reference scanning line information RSD
the respective first pixel change points a ₁ and b ₁ in
When it is detected that _the relative distance _of
The logic value of the signal CR becomes "0" by the time data D is read from the ROM32 three times based on the change in the logic value of CC from "0" to "1".
→ Based on the change from “1” or when the logical value of the signal CR changes from “0” to “1”
The logic value of the signal CC changes from “0” to “1” by the time data D is read from the ROM32 three times.
When the logic value of the signal changed later changes from “0” to “1”, the ROM is accessed by the address signal.
The output bit f of 32 has a logic value "1", and the data D is "the first bit of each of the coded scanning line information CSD and the reference scanning line information RSD".
The content indicates the vertical mode code corresponding to the relative positional relationship between pixel change points a ₁ and b ₁ . In the above process, the ROM is
The read data of 32 is sequentially latched in the latch circuit 31 as data indicating the transition of the signal that changed first, and is sent to the ROM 32 as part of the address signal.
This is similar to the "pass mode" mentioned above. Of course, when the change in the logic value of the signal CC from "0" to "1" and the change in the logic value of the signal CR from "0" to "1" occur at the same time, these logic values change from "0" to "1". '', the output bit f of the ROM 32 becomes a logical value ``1'' and the data D has the content indicating the ``vertical mode code corresponding to _V0' ' described above. (3) The latch circuit 31 corresponding to pixel scanning and
In the process of sequential operation with the ROM 32, encoded scanning line information CSD and reference scanning line information RSD
the respective first pixel change points a ₁ and b ₁ in
When it is detected that _the relative distance _of
Data D is read from the ROM 32 four or more times based on the change in the logic value of CC from "0" to "1", and the logic value of signal CR changes from "0" to "1".
Based on the change to “1” or the logical value of the signal CR changes from “0” to “1”
When data D is read from the ROM 32 four or more times and the logic value of the signal CC changes from "0" to "1", the logic value of the signal CC changes from "1" to "0" after that. The output bit f of the ROM 32 becomes a logical value "1" at the time it is accessed by the address signal, and the data D is "from the processing target scanning start point a ₀ to the first pixel change point a ₁ in the encoded scanning line information CSD. distance and the first
The horizontal mode code corresponding to the distance from the pixel change point _a1 to the second pixel change point _a2 . In addition, even in the above process, until the logic value of the signal CC changes from “1” to “0”,
The read data D of the ROM 32 is sent to the latch circuit 3 as data indicating the transition of the signal CC and the signal CR.
They are sequentially latched to 1 and fed back to the ROM 32 as part of the address signal. There are three types of processing that can be roughly divided into
This is done by the decoding determining means. Incidentally, the processing mode for determining the encoding of the image information shown in FIG. 1 is shown in the following table.

【table】

[Table] Also, the processing mode during decoding in this code/decoding determination means is basically the same as the processing mode for encoding described above, but in this case, especially when the signal CR
The above sequential operation is repeated using the read data D of the ROM 32 as an address signal of the ROM 32, and a predetermined pixel information change is detected from the reference scanning line information RSD, which is the previously decoded information, at the time when predetermined decoding is determined. It operates so that the output bit f of the ROM 32 becomes the logical value "1" at the time when the output is made.
However, switching between the encoding data table and the decoding data table in the ROM 32 is performed according to the logic content of the select signal SS applied from the control processing section 50 to the latch circuit 40. While SS is latched in the latch circuit 40 with a logic value of "0", the encoding data table of the ROM 32 is selected, and the select signal SS has a logic value of "1".
While latched in the latch circuit 40 as
The decoding data table of the ROM 32 is selected. The control processing section 50 performs driving control of the flip-flops 11 and 12, the latch circuit 31, and the latch circuit 40 described above, and also performs drive control of the fourth flip-flop when encoding processing is specified by an appropriate means (not shown). Encoding is executed according to the flowchart shown in the figure, and if decoding processing is specified, decoding is executed according to the flowchart illustrated in FIG. However, FIGS. 4 and 5 show an example of the operation using the modified read method described above. For example, when encoding processing is specified, the control processing section 50 sends a signal IN to the latch circuit 31 and a signal SE ₁ to each of the flip-flops 11 and 12.
After initialization by applying and SE ₂ , a load signal is applied to the latch circuit 31 while advancing the encoded scanning line information CSD and reference scanning line information RSD one bit at a time.
LD is applied to cause the encoding/decoding determining means to perform the above-described sequential operation, and the output bit f of the ROM 32 is sequentially monitored. As a result, when it is detected that the output bit f of the ROM 32 has become the logical value "1", the read data D of the ROM 32 is taken in at this point.
An encoded code corresponding to the contents of the captured data D is formed. Furthermore, the above imported data D
As described above, each represents a specific form in which scanned image information can be encoded. The encoded code thus formed is output from the control processing unit 50 as transmission encoded information TCD, and after being subjected to parallel-to-serial conversion, etc., is transmitted to a predetermined transmitter. Further, when decoding processing is specified, the control processing unit 50 receives the received encoded information RCD transmitted from a predetermined receiving device, decodes the code contents,
Furthermore, as initialization, a signal IN is applied to the latch circuit 31.
In addition, the signal _SE2 is applied to the flip-flop 12, and the preset/reset control signal CE is used to set the memory content BC of the flip-flop 11 to logical value "0" or "1", that is, to set the pixel at which processing of decoded data starts. Initial settings are made to determine whether to use "white pixels" or "black pixels." As a result, the memory content BC of the flip-flop 11 is sent as decoded scanning line information RESD to an image information buffer (not shown), and the processing target scanning starting point is determined to be a "white pixel" or a "black pixel" according to the content of the information RESD. Something will be remembered. Further, the control processing unit 50 performs reference scanning line information following the above initialization.
Latch circuit 31 while advancing RSD one bit at a time.
A load signal LD is applied to the code/decoding determining means to perform the above-described sequential operation, and the output bit f of the ROM 32 is sequentially monitored. It should be noted that during this period, temporary storage of the initially set pixel information is continued for a number corresponding to this repetition period. When it is detected that the output bit f of the ROM 32 has become a logical value "1" as a result of the above monitoring, the control processing section 50 reads the decoded received encoded information RCD.
Based on the code contents of flip-flop 1
Decide how to control 1. For example, when decoding to the image information shown in _FIG . At the time when the logical value becomes "1", that is, when the first pixel change point _b1 in the reference scanning line information RSD is detected, the content of the decoded scanning line information RESD changes to "white pixel" for two pixels thereafter. The flip-flop 11 is controlled as shown. Of course, this control is performed using the preset/reset control signal CE. As a result, the image information buffer (not shown) stores image information from the starting point _a0 of the scanning line information to be decoded to the first pixel change point _a1 , and this stored information is printed out as appropriate. Ru. Of course, the above-described encoding processing operation and decoding processing operation are repeated for each predetermined amount of image information. In this way, in this embodiment, the function for determining encoding/decoding is provided by the latch circuit 31 and the ROM 32.
Since the coding and decoding determination means are integrated into the coding and decoding determining means, not only can the device be made smaller, but also the control procedure for coding and decoding can be greatly simplified. Furthermore, since the sequential operation speed of the encoding/decoding determining means is determined by the access time of the ROM 32 and the latch speed of the latch circuit 31, the highest machine speed can be maintained, and the encoding It is possible to significantly improve processing speed and decoding processing speed. In the above embodiment, flip-flops 11, 12 and exclusive OR circuits 21, 22, 2
3 constitutes the pixel change detection means for the reference pixel, but it goes without saying that any other logic circuit may be used as long as it has an equivalent function. Further, in the above embodiment, for the convenience of application to a two-dimensional sequential processing encoding and decoding system of facsimile data, a flip-flop 12 and exclusive OR circuits 22 and 23 are used as the pixel change detection means for monitoring reference scanning line information RSD. However, if these are eliminated and the content of the data stored in the ROM 32 corresponds to run-length information, this device can be applied to a one-dimensional compression encoding and decoding system for facsimile data. You can also. Moreover, if the pre-stored data is set so that the read data D when the output bit f of the ROM 32 has a logical value of "1" is directly retrieved as an encoded code, the burden on the control processing section 50 can be further reduced. As a result, more favorable effects can be obtained. By the way, in the above embodiment, the encoding and decoding operations were explained when the modified read method was adopted for convenience, but this device
It can be applied to any type of data compression encoding and decoding depending on the content of the data stored in the ROM 32, and it can be used to reduce the size of the device described above for all data compression encoding and decoding systems.
This makes it possible to simplify control procedures and improve processing speed. Of course, a configuration may be adopted in which the storage area of the ROM 32 is expanded and encoded and decoded data corresponding to a plurality of systems are stored in the ROM, and these data are selectively read out. As explained above, according to the image information processing device according to the present invention, the device itself can be downsized, and image information such as facsimile data can be compressed and encoded and decoded at high speed with simple control procedures. can do. In particular, it is of great significance to apply the image information processing apparatus according to the present invention to future facsimile apparatuses that are expected to achieve higher transmission speeds than ever before.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an example of image information in a diagrammatic form. FIG. 2 is a flowchart showing an example of a control procedure for data compression encoding by a conventional image information processing device. FIG. 4 is a block diagram showing the configuration of an embodiment of an information processing device; FIG. 4 is a flowchart showing an example of a control procedure for data compression encoding by the image information processing device according to the present invention;
The figure is a flowchart showing a control procedure for data decoding by the image information processing apparatus according to the present invention. 11, 12...flip flop, 21, 2
2, 23... exclusive OR circuit, 31, 40... latch circuit, 32... ROM, 50... control processing section.

Claims (1)

[Scope of Claims] 1. A latch circuit, which receives a latch signal to the latch circuit as an address signal, reads and outputs data corresponding to the address signal, and uses this output data as part of the latch signal to output the latch signal to the latch circuit. The latch circuit includes a circulating circuit including a memory that feeds back data to
from the first image information to the second image information or from the second image information to the first image information of an image information string consisting of binary image information.
An information change instruction signal indicating the presence or absence of information change to the image information of the image information is sequentially latched corresponding to the transition of one piece of information of the same image information string, and the memory stores one or more types of the image information string. pre-stores one or more pieces of predetermined code information indicating what type of information change mode each predetermined information change mode is, and the address signal does not correspond to any of the predetermined information change modes. When the address signal corresponds to one of the predetermined information change modes, outputting data indicating each transition of the information change instruction signal as the read data, and when the address signal corresponds to one of the predetermined information change modes, the corresponding code information is output as the read data An image information processing device, comprising: a sequential circuit for outputting image information, and compressing and encoding or decoding the image information string based on the predetermined code information output from the memory of the sequential circuit.