JPS6364700A - Amplitude storage circuit - Google Patents

Abstract

PURPOSE:To precisely store a pulse amplitude even if it is irregular by holding an output signal when the level of an input signal is lower than that of the output signal. CONSTITUTION:When the input signal 10 is inputted to a sample/hold circuit 1, storage start signal 13 from the outside becomes '1' when a pulse is led only during minimum necessary time to start sapling. A control signal 14 becomes '1' as well to start sampling. If the input signal 10 drops from the peak point of amplitude to be lower than the output signal 11, a comparison signal 12 from a voltage comparator 2 is inverted to become '0', and a control signal 14 from an OR circuit 3 becomes '0' as well. The circuit 1 stores and outputs the peak value of the amplitude of a pulse signal at its changing time.

Description

Detailed Description of the Invention Technical Field The present invention relates to an amplitude memory circuit, and in particular, the present invention relates to an amplitude memory circuit, and in particular, the amplitude of a pulse signal whose pulse width is unknown and which changes from pulse to pulse, such as when receiving pulse signals from an unspecified number of radars. The present invention relates to an amplitude storage circuit that stores .

Conventionally, this type of amplitude memory circuit targets pulses with various pulse widths, and uses the sample width to set the minimum pulse width among the pulse widths to be received, and uses a sample and hold circuit to calculate the pulse width. The amplitude of the pulse was stored in accordance with this sample width at the timing of the rising edge of . This is because the pulse width of the pulse cannot be known until the pulse is received, so the amplitude of the pulse has to be stored using the smallest pulse width among the pulse widths to be received as the sample width.

In such a conventional amplitude storage circuit, the minimum pulse width among the pulse widths to be received is set as the sample width, and the amplitude of the pulse to be stored is sampled from the rising point of the pulse to this minimum pulse width. When the width to the peak point of the target pulse exceeds the minimum pulse width, the amplitude of the pulse can only be measured halfway from the rise, so there is a drawback that the level of the peak point, which is the true amplitude, cannot be stored.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional ones as described in (1) above, and provides an amplitude memory circuit that can accurately store pulse amplitude even if the pulse width is unspecified. For the purpose of providing.

Structure of the Invention The amplitude storage circuit according to the present invention is an amplitude storage circuit that stores the amplitude of an input signal, and includes a delay means that generates an output signal that changes in accordance with the input signal while being delayed by a predetermined time. , when the level of the input signal becomes lower than the level of the output signal, the delayed output signal of the delay means at that time is held.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one embodiment of the present invention is a sample and hold circuit 1.
, a voltage comparison circuit 2 , and an OR circuit 3 .

The sample and hold circuit 1 has three terminals: an input terminal, an output terminal, and a control signal input terminal, and when the control signal 14 is logic "1", the output signal 11 follows the input signal 10 with a delay. It has a changing function. When the control signal 14 changes to logic rOJ, the output signal 11 at the time of change is held.

The voltage comparator circuit 2 inputs the input side voltage and the output side voltage of the sample hold circuit 1, and outputs a logic rOJ when the input side voltage becomes lower than the output side voltage.

The OR circuit 3 performs the OR of the comparison signal 12 of the voltage comparison circuit 2 and the storage start signal 13 given from the outside, and uses the result as a control signal 14 to send the sample and hold circuit 10.
Output to control signal input terminal.

FIG. 2 is a timing chart of one embodiment of the present invention. The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

When a pulse signal to be stored is input to the sample hold circuit 1 as an input signal 10, at the same time, a storage start signal 13 from the outside is set to logic "1" for the minimum period necessary to start sampling at the rising edge of the pulse. '', the it, II control signal 14 also becomes logic ``1'', and the sample and hold circuit 1 starts sampling the amplitude of this pulse signal.

While the pulse signal is rising, the input signal 10 is always higher than the output signal 11 due to the delay within the sample and hold circuit 1. During this time, the comparison signal 12 of the voltage comparison circuit 2 is logic "1", and the logical sum of the comparison signal 12 and the storage start signal 13, that is, the control signal 14, is logic "1". This control signal @14 causes the output signal 11 of the sample and hold circuit 1 to follow the input signal 10 and change.

When the amplitude of the pulse signal reaches its peak point and begins to fall, the input signal 10 becomes lower than the output signal 11 due to the delay in the sample and hold circuit 1, contrary to the rise. Therefore, at the moment when the input signal 10 starts to fall from its peak, the comparison signal 12 of the voltage comparator circuit 2 is inverted and becomes the logic [Oj], so the control signal 14 of the OR circuit 3 becomes logic "0" and the sample hold The circuit 1 holds the output signal 11 at the time of its change. That is, the peak value of the amplitude of the pulse signal is stored.

In this way, the pulse signal to be stored is input,
When a storage start signal 13 is given from the outside, the voltage difference between the input signal 10 and the output signal 11 of the sample and hold circuit 1 is detected, and the amplitude of the pulse signal is held at the peak point of the amplitude of the pulse signal. By outputting the information, it is possible to easily store an accurate pulse amplitude peak even if the pulse width is unspecified.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described in detail, the delay means for generating an output signal that changes in accordance with the input signal while being delayed by a predetermined time is provided, and the level of the input signal and the level of the output signal are adjusted. By comparing and holding the output signal at this time when the input signal level becomes lower than the output signal level, the pulse amplitude can be accurately memorized even if the pulse width is unspecified. The effect is that it can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart of one embodiment of the present invention. Explanation of symbols of main parts 1... Sample hold circuit 2... Voltage comparison circuit 3... OR circuit 10... Input signal 11... ... Output signal 12 ... Comparison signal 13 ... Memory start signal 14 ... Control signal

Claims (1)

[Claims] The amplitude storage circuit stores the amplitude of an input signal, and includes a delay means for generating an output signal that changes in accordance with the input signal while being delayed by a predetermined time, such that the level of the input signal is higher than that of the output signal. When the level falls below the
An amplitude storage circuit characterized in that the delayed output signal of the delay means at that time is held.