JPS6364362A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce wiring delay, and to increase the speed of the control of currents by forming a plurality of input circuits for control input signals and shortening the wiring length of a control signal conductor and minimizing loading capacity. CONSTITUTION:An output phi1 from a circuit 1A and an output phi2 from a circuit 1B each control the currents of circuit groups 2A, 2B. Two control signal input circuits 1A, 1B are shaped, and arranged on the mutually reverse sides of memory cell arrays 5. Since the memory cell arrays 5 generally take a large occupying area on a chip, the wiring length of the outputs phi1, phi2 can be shortened by isolating the control signal input circuits 1A, 1B. The number of load circuits can also be decreased, and the time constant of the wirings of the outputs phi1, phi2 is diminished by double effects, thus increasing the response speed of the load circuit groups 2A, 2B.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit, and particularly to a chip configuration for reducing delays due to wiring resistance and enabling high-speed operation.

[Conventional technology]

In integrated circuits such as memo IJLSIs and logic LSIs, a method is widely used in which the power consumption of a plurality of circuit blocks within a chip is divided depending on the operation mode. For example, in a memory LSI, there is a memory cell anno.

It consists of peripheral circuits such as input/output circuits, decoder circuits, and sense circuits, but during standby, it is only necessary to hold one report in the memory, and most of the peripheral circuits do not need to operate. Therefore, power consumption during standby can be significantly reduced compared to during operation. . . . Also, even in the case of a small-sized LSI, such as a 4LSI, it is possible to divide the chip into multiple A1 circuit blocks, and depending on the operation mode, it is possible to reduce the power to unnecessary circuit blocks.

A description will be given below using a memory LSI as an example. As mentioned above, the chip select input signal (C8
) or especially in dynamic RAM, the row address strobe input signal (RASJ) is used.

Conventionally, in order to perform single-force control during V operation and standby, a pulse flow/source analysis method has been proposed (Japanese Patent Publication No. 53-321).
91° Figure 2 (a) is a block diagram showing this concept, and (
b) shows its operating waveform. The control input C8 from the outside in the same 9 (al) is converted into a signal φ of an appropriate level by the input circuit 1, and is controlled with the current of the circuit group shown in 2. There are circuits using bipolar transistors, etc. Naturally, depending on the configuration of these controlled circuits, φ
The level of the A word becomes different1, Figure 2 (b)
For example, the waveform of C8,φ is shown. For convenience of explanation, it is assumed here that during standby, C8 is at a high level and φ is at a low level, and during operation, C8 is at a low level and φ is at a high level: rtC.

This φ requires moving a large number of y-controlled circuits, and the wiring becomes long. Therefore, the wiring resistance R1 and the load capacitance C+ become large, and the rising and falling waveforms of φ differ between the solid line and the broken line in FIG. 2(b) at the near end and the far end of the input circuit 1. At this time, the rise time (1
0 to 90%) is frl, the rise time t2□ at the A end is 1. −r〒”+(Z2C, π7 or −.For example, t,, =Ins, C1=5 p)', R+
=500Ω, tr2 is 5.6ns. In this way, since the rise time of φ becomes slower at -A, the response speed of the load circuit 2 connected to the far end becomes slower. Furthermore, since there are a large number of load circuits for φ, ringing and overshoot are likely to occur in the waveform for φ, and the operation of the load circuit 2 may become unstable. The problem of signal delay due to wiring resistance of current control signal input in the conventional technology has been described above, but this problem is not only in the case of 4-current control input signals, but also in other cases such as address input signals. Of course, this is a legal problem.

[Point d while the invention is about to disappear]

The above-mentioned conventional technology does not take into account the wiring delay of the control signal φ and the distortion of the waveform, which poses a problem in increasing the speed of LSI, for example, increasing the operating speed of memory access time.

Is the purpose of this invention the wiring delay and countershape distortion of control signal lines? It is possible to reduce the speed of integrated circuits and increase the speed of integrated circuits.

[Means for solving problems]

The above object can be achieved by providing a number of control input signal input circuits and reducing the wiring length and load capacitance of the control signal line φ. As another means, this can be achieved by arranging only one innovative signal input circuit in close proximity to a group of load circuits that require particularly high speed performance.

[Effect]

By using either of the two methods mentioned above, the resistance and load capacitance of the control signal line φ can be reduced, thereby reducing the wiring delay. Can be made smaller.

〔Example〕

The invention will be explained below using all the non-inventive examples.

Figure 1 shows a chip arrangement showing a first embodiment of the invention. In this figure, C3 indicates the control input signal 2 and its bonding pad. 5 is other add input,
Ponding pad 7 for input/output such as memory output! ? Indicates f. 4 is a memory circuit; 11A and IB are fixed input circuits for processing control input signals; The output φ+ of the circuit IA and the output φ2 of the IB control the flow of the circuit groups 2A and 2B, respectively.

In this way, in the actual case, the control signal input circuit is
.

Fixed IA and IB 21 are arranged on opposite sides of the memory cell array 5. In general, the memory cell array 5 occupies a large direct product on the chip, so by separating it into LA and IB, φ1. The wiring length of φ2 can be shortened. Furthermore, the number of load circuits can be reduced, and due to the double effect, the wiring time constant of φ1φ2 can be reduced, and the response of the load circuit groups 2A and 2B can be made faster.

Next, the effect of the non-embodiment will be described in terms of the difference in delay time from δ when only one circuit is placed at the position of the conventional IB.

Using the direct example of Equation 1 above, in the non-embodiment, the signal wiring length can be reduced to less than 1/2 of the conventional one, and the number of load circuits is A to O, and CI and R+ are each reduced to 1/2 of the original. It's Nide.

In this way, the rise time t7□ at the far end of ζφ is 5,
The improvement is from 6 ns to λ9 ns. The load circuit is φl
, assuming that the response starts at the 50% point of φ2, the delay time until the 2A group starts operating is approximately 1.3
ns (-=, X (5,6-2,9)ns) The speed can be increased. If the two circuit groups include an address buffer circuit that requires particularly high speed, the access time will be reduced to 1.
The speed can be increased by 3 ns.

Note that in this embodiment, the wiring from the bonding pad of C3 to the input circuit IA becomes long. However, the number of wiring connections for 100 input signals does not increase for the following reasons. Of the falling time (10-90%) of the C8 input, the falling time on the bonding pad is tflu The falling time at the input part of the circuit IA is tf2, and the wiring resistance and wiring capacitance from the bonding pad to IA are 2 each. If C2, t12 is expressed as V stone π]〒Z, 2Qπ catty. However, input 11.
is originally as long as about 3 ns, and the number of load circuits is 1.
Czl″i is mostly just the wiring capacitance, and C2 is about 1 pF. Therefore, 几2=500
If we calculate *”tg as Ω, we get 32+ (2,2x0.
5) Since 2=3.2 ns, the fall time is only 0.2 ns worse than that of the bonding pad.

In other words, it can be said that there is almost no increase in delay time. As described above, using this embodiment, the access time is reduced to 1.3ns$.
/ can be reduced. Note that Fig. 41 shows the case where there are two input circuits, LA and IB.

The number can be further increased to increase the speed.

FIG. 3 shows 42 embodiments of the invention. The symbols inside the chip correspond to those in FIG. In this embodiment, control input C8
is received by only one input circuit IA. In this embodiment, this IA is arranged on the skinned side of the bonding pad with respect to the memory cell array 4.

This arrangement of the bonding pads may occur depending on the pin arrangement of the control input signal. 2A at IA output φ1
, 2B gold are commonly driven. In this case, it is effective to include an address buffer circuit that requires especially high-speed DC control in circuit *2A.

Circuit #2B is a circuit that does not require high speed. φ
The load capacity of Tobi is large because it drives 2A and 2B in common. Therefore, compared to the fruit in Figure 1, 4NJ.

Although the delay time of circuit IA increases, the arrangement line delays at the near and far ends of 2A are the same as in FIG. In terms of memory access time, compared to FIG. 1, it is only delayed by the IA delay time increase. Since there is only one input circuit, the DC current during standby can be reduced compared to the example shown in FIG.

Next, a specific example of a current control circuit for a static memory or a dynamic memory with an access time of about 1Qns, which is particularly effective when the uninvented chip structure is applied, will be shown. Note that the present invention relates to the arrangement of the chip control signal input circuit as shown in the embodiments of FIGS. 1 and 3, and the circuit configuration and the circuit configuration of the controlled circuit are limited to the following embodiments. It is not something that will be done.

In FIG. 4, the circuit l is an input circuit for the control input signal C8, and its output φ controls the direct current of the peripheral circuit. The peripheral circuits shown here include circuits 21, 22, and 23 that use three different current control methods. Next, the operations of these circuits will be briefly explained. Circuit 1 has two stages /7'l ρ, -jl )Q ノ・/ /CJ l-Q + ρSin Q /
/<A See →-CiVO8 compound driver)
It is probably a three-tiered structure.

For example, the input signal n of a TTL (transistor-transistor logic) interface is % fAit pressure V c
Increase and shape the φ with a large wave and crease close to c.

Input level of first stage CMOS inverter H'1rAssuming TL interface, high level (2.4V).

Low level (0.8 Vl, low loss and positive current, so current flows constantly. 21 is for controlling the d current of CΔ (OS inverter by inserting n channel MO8 (ΔL+) in series, p channel MO8 ( Mz) is to keep the output constant.As mentioned above, even if the input A1 of 21 is the address input number i at the TTL interface level, by reaching 8 (+ on, 10,000) with φ, The current during standby can be set to zero.

Circuit 22 is the heart current source of the differential amplifier of B/F Parla.

This is achieved by channel 8 (O81M3), and its current is controlled by φ. Also, circuit 23 is Tokuganuma 59-1
52865, the current source of the bipolar differential amplifier is made up of a bipolar transistor Q1 and a resistor kL+, and the Q, , )-\- source is controlled by nMO8M4 and N(6). .Vc++ is the reference voltage generated within the chip.Turn off 4 during standby.

Turn on the MS and set the current of the differential amplifier to 0. During operation, Vcs is set to Q+ by turning on M4 and turning off Ms.
A predetermined KC< is applied to the base of the differential amplifier. In this way, the currents 21, 22, and 23 can be turned on and off during operation and during standby.

The i3ic MO8 driver at the final stage of the input circuit 1 has a high K4 dynamic capability like a frequency generator, and its output φ rises quickly.

In order to take advantage of this high speed, it is necessary to reduce the delay time due to the wiring of φ, and the chip layout of the control signal input circuit shown in FIGS. 1 and 3 is effective. In addition to the circuits 1, 21, 22, and 23 shown in FIG. 4, there are various circuit configurations using bipolar transistors, Δ10s transistors, or both, but these are omitted here.

[Effects of the invention] According to the above-mentioned non-inventions 7, the memo that increases and decreases the current during standby and operation is used in integrated circuits such as LSI, and its IT style 11] is commonly used. By providing a plurality of input circuits or by devising the chip position i, it is possible to speed up the current control. As an effect of this speed increase, for example, the memory access time can be increased by about 1.3 ns compared to the above-mentioned sphere. Therefore, it is highly effective when applied to static memory or dynamic memory with an access time of about 1Qns.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the chip configuration of the first embodiment of the present invention, FIG. 2 is a conventional current control circuit and its waveform diagram, and FIG.
The figure is a plan view of the chip configuration of the second embodiment of the present invention.
The figure is a circuit diagram showing one embodiment of a current control circuit. C8...Go'' input signal, φ, φ1. φ2...in-chip control signal, 1. IA, IB...Control signal input circuit. 2.21, 22.23... Controlled circuit, 4... Memory cell array, 5... Bonding para h" group, tr
＋. 1,--Rise time, 10-90%, tfl, tt2
...Fall time, 10-90%. Neck 7 Figure 1 Shallow) - I-order 2nd ward (around)

Claims (1)

[Claims] 1. A group of input terminals for inputting at least one external signal; at least one input terminal group that operates with the external signal as input;
In an integrated circuit consisting of at least one first circuit group and at least one or more second circuit group that operates in response to the output of the first circuit, a part of the first circuit is connected from the input terminal to a part of the first circuit. The first part of the circuit and the second part of the circuit are arranged such that the total signal wiring length is longer than the signal wiring length from the first part of the circuit to the second part of the circuit. An integrated circuit characterized by having some circuits installed.