JPS6362261A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a semiconductor integrated device from being erroneously operated due to simultaneously outputting operations by inserting a three-state buffer between the output terminal of an inner gate for producing a signal to become the output of the device and an external output terminal of the device. CONSTITUTION:An oscillator 1, a counter 2 and a decoder 3 are controlled in their operating states when a suitable signal is applied to an external control signal input terminal 15. The output of the oscillator 1 is applied as a clock input of the counter 2, and the output of the counter 2 is applied as the input of the decoder 3. The outputs 4, 5, 6, 7 of the decoder 4 are applies as control signal inputs of three-stage buffers 9, 10, 11, 12 to so control the buffers 9, 10, 11, 12 as to become conductive or nonconductive. As a result, a timing that the output signal of a logic circuit 8 is presented at the external output terminals 16, 17, 18, 19 of a semiconductor integrated unit is controlled.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and in particular, to preventing malfunctions of semiconductor integrated devices caused by simultaneous output operations during testing of semiconductor integrated devices using an IC tester. This invention relates to a simultaneous output operation prevention circuit.

[Conventional technology]

When testing semiconductor integrated devices using an IC tester, due to the structure of the IC tester, the load capacity for the output of the semiconductor integrated device is large, so if multiple outputs of the semiconductor integrated device change simultaneously, noise may be generated on the power supply line or ground line. occurs, the semiconductor integrated device malfunctions, and a normal power test cannot be performed.

Conventionally, as a method for preventing malfunctions due to the above-mentioned simultaneous output operations, a delay gate is appropriately inserted between the output of an internal gate in a semiconductor integrated device and the input of an output buffer.
There were methods to prevent multiple outputs from changing at the same time, and methods to specify the number of outputs that could change simultaneously.

[Problem that the invention seeks to solve]

The conventional method of inserting a delay gate between the internal gate and the output buffer described above requires a large number of delay gates when the propagation delay time of the gate cannot be guaranteed accurately, such as in a gate array. Therefore, there is a drawback that the phase difference between the output signals becomes very large. Furthermore, with the method of specifying the number of outputs that can operate simultaneously, as semiconductor integrated devices become more complex and the number of output terminals increases, it becomes increasingly difficult to keep the number of outputs that can operate simultaneously within the specified number. The disadvantage is that it is difficult to

[Means for solving problems]

The simultaneous output operation prevention circuit of the present invention includes an oscillation circuit, a counting circuit, a decoding circuit, and a plurality of three-speed gates whose operating states can be controlled from outside the semiconductor integrated device.

The output terminal of the oscillation circuit is the clock input terminal of the counting circuit, the output terminal of the counting circuit is the input terminal of the decoding circuit, and each output terminal of the decoding circuit has a clock input terminal of the counting circuit. The control signal input terminals of the three-state buffers, which are equal to or less than the number of external output terminals that can operate simultaneously, are connected, and these three-state buffers are connected to the output terminals of internal gates that output signals to be output from the semiconductor integrated device, and It has a structure inserted between the integrated device and the external output terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention.

In the figure, oscillation circuit 1. Counting circuit 2. The decoding circuit 3 is
The operating state is controlled when an appropriate signal is applied to the external control signal input terminal 15. Oscillation circuit 1
The output of the counting circuit 2 is applied to the clock input of the counting circuit 2, and the output of the counting circuit 2 is applied as the decoding circuit 30 input.

Outputs 4, 5, 6, 7, etc. of the decoding circuit 3 are given as control signal inputs to three-state buffers 9, 10, 11, 12, etc., and these three-state buffers 9, 10°1
1.12, etc. are controlled to be in a conductive state or a non-conductive state, and as a result, the output signal of the logic circuit 8 is outputted to the external output terminal 16, 17.1B of the semiconductor integrated device.

Controls the timing of appearance in 19th mag.

The operation of the circuit shown in FIG. 1 will be specifically explained using the time chart shown in FIG.

The output (signal 1) of the oscillation circuit 1 has a sufficiently higher frequency than the basic clock (signal 2) of the semiconductor integrated device, and remains at a low level when the external control signal (signal 3) is at a high level.

Outputs 4, 5, 6.7, etc. (signals 4, 5, 6, etc.) of the decoding circuit 3 are output from all three-state buffers 9, 10, 11, 12, etc. when the external control signal (signal 3) is at a high level. A signal (low level signal in Fig. 2) is output such that the output (signals 7, 8, 9, etc.) becomes high impedance. The counting circuit 2 remains set to the initial value when the external control signal (signal 3) is at a high level;
) is at a low level, and when the oscillation circuit 1 operates, the counting circuit 2 starts counting using the output of the oscillation circuit 1 as a clock. Counting circuit 2 starts counting, and its output is sent to decoding circuit 3.
given to. Based on the output from the counting circuit 2, the decoding circuit 3 generates a signal (low level signal) that makes the three-state buffers 9, 10, 11, 12, etc. conductive from the outputs 4, 5°, 6.7, etc. of the decoding circuit 3. are sequentially output at time intervals in which the outputs of the semiconductor integrated device do not operate simultaneously.

Next, the operation of each of the above-mentioned circuits will be explained over time.

At time O, the basic clock signal of the semiconductor integrated device (signal 2
) changes.

At the same time as the basic clock signal (signal 2) changes, the external control signal (signal 3) applied to the external control signal input terminal 15 in FIG. 1 becomes high level, and the logic inside the semiconductor integrated device in FIG. The high level is maintained until the state of the circuit 8 becomes stable, during which time the oscillation circuit 1 stops operating, and the three-state buffer 9,
Outputs 10, 11, 12, etc. (signals 7, 8, 9, etc.), that is, external output terminals 16, 17, 18 of the semiconductor integrated device in FIG.
゜19 mag maintains a high impedance state.

Next, at time 'r72, when the external control signal (signal 3) is changed from a high level to a low level, the oscillation circuit 1 starts operating and the output clock (signal 1) is applied to the counting circuit 2. The counting circuit 2 receives the output clock (signal 1) of the oscillation circuit 1.
) is counted and its output is given to the decoding circuit 3.

The decoding circuit 3 sequentially changes the outputs 4 and 5.6°7 of the decoding circuit 3 to a high level based on the output of the counting circuit 2 at time intervals in which simultaneous output operations do not occur (signals 4 and 5.6). Three-state buffer9. output signals so that the external outputs 16.17 and 18.19 of the semiconductor integrated device do not change at the same time. . Furthermore, the output 4 of the decoding circuit 3.
The signal 5.6.7 (signal 4°5.6) has a structure in which when it reaches the -axillary level, it remains in that state (high level) until the external control signal (signal 3) becomes low level. , an internal logic circuit 8 is connected to all external output terminals of the semiconductor integrated device.
The external control signal (signal 3) remains high until the signals appear and these signals are observed by the IC tester. After the above operations are completed, the basic clock (signal 2) of the semiconductor integrated device 7! ! ! : Change (time T
) Repeat the above operations.

Further, the above operations are repeated until the test is completed.

FIG. 3 shows a circuit of a specific embodiment according to the present invention. Generally, when a semiconductor integrated device is incorporated into a system, the load capacitance to the output terminal of the semiconductor integrated device is small, and malfunctions due to simultaneous output operations are unlikely to occur. 21, and by leaving this terminal open on the system, the circuit shown in FIG.
is in a conductive state. On the other hand, when testing is performed using the engineering C tester, the external control signal - input terminal 21
Simultaneous output operations of the semiconductor integrated device can be prevented by applying a logical value of 0 to the external control signal input terminal 22, and further applying a signal with a cycle of 172 or less synchronized with the basic clock of the semiconductor integrated device to the external control signal input terminal 22.

〔Effect of the invention〕

As explained above, the present invention can be used when testing a semiconductor integrated device using a test device with a large load capacity such as an IC tester.
This method has the effect of more reliably preventing malfunctions of a semiconductor integrated device due to simultaneous output operations than conventional methods.

Furthermore, since the present invention requires only one three-state buffer to be inserted between the internal logic circuit of the semiconductor integrated device and the external output terminal, the phase difference between the output signals does not increase. Even if the scale of the integrated device increases and the number of output terminals increases, this can be dealt with simply by changing the counting circuit and decoding circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram showing a specific circuit example of the embodiment of the present invention.

Claims (1)

[Claims] Each has one oscillation circuit, one counting circuit, one decoding circuit, and a plurality of three-state buffers, the output of the oscillation circuit becomes a clock input of the counting circuit, the output of the counting circuit becomes an input signal of the decoding circuit, and The state buffers are grouped into groups that are less than the number of external output terminals that can operate simultaneously for the semiconductor integrated device, and all the control signal input terminals of the three-state buffers in the same group are connected to the output terminals of the decoding circuit. The three-state buffer is connected to only one output terminal in the semiconductor integrated device, and the three-state buffer is inserted between the output terminal of a circuit that outputs a signal to be output from the semiconductor integrated device and the external output terminal of the semiconductor integrated device, and Depending on the signal applied to the external control signal input terminal of the device, the oscillation circuit takes an oscillation state or a non-oscillation state, the counting circuit takes an initial value state or a counting state, and the decoding circuit takes the three-state state. A semiconductor integrated device having a function of outputting a signal that makes a buffer non-conductive or decoding a signal from the counting circuit and outputting it to the three-state buffer.