JPS6361506A - Binarization circuit - Google Patents

Abstract

PURPOSE:To reduce the phase error of a binary signal with a simple constitution by generating the difference signal between the output signal of a filter, which allows the fluctuating component of a DC voltage as the low frequency compo nent of an input signal to pass through, and the output signal of a delay means which delays the input signal and taking out a binary signal from this difference signal. CONSTITUTION:An LPF 45 allows only the signal of the low band component of a video signal 21 to pass through. That is, the modulated signal component of the video signal 21 is cut and the fluctuating component of the DC voltage passes through. A delay means 46 delays the video signal 21 by the same delay time as passage of the video signal 21 in the LPF 45. The difference between an output signal 49 of the LPF 45 and an output signal 50 of the delay means 46 is obtained by an operational amplifier 47 as the detecting means to output a difference signal 51. This difference signal 51 is inputted to the non-inverted input terminal of a comparator 48 as the signal generating means and is com pared with a potential OV of the inverted input terminal to output a binary signal 39.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a binarization circuit, and more particularly to a binarization circuit that converts an input signal with fluctuations in a DC voltage component into a binary signal.

[Prior Art] Binarization circuits that convert input signals into binary signals are often used in information processing devices, such as optical information recording and reproducing devices that extract information from optical information recording carriers such as optical files and combo discs. It is being

FIG. 10 is a circuit diagram showing an example of a conventional binarization circuit.

As shown in FIG. 1O, the binarization circuit of this example has a reference voltage source 37, a reference voltage is input from the reference voltage source 37 to an inverting input terminal, and an input signal 38 is input to a non-inverting input terminal. It is composed of a comparator 36.

When an input signal 38 is input to this binary circuit, a binary signal 39 is outputted which is at a high level in a signal range of a voltage higher than the reference voltage value and at a low level in a signal range of a lower voltage.

FIG. 11 is a circuit diagram showing another example of a conventional binarization circuit.

In the binarization circuit of this example, the potential of the inverting input terminal of the comparator 41 is set to OV, and the input signal is applied to the non-inverting input terminal via the HPF (high pass filter) 40. When the component is cut by 11PF40 and input to the non-inverting input terminal, it becomes high level in the positive voltage signal range.

In the negative voltage signal range, a low level binary signal 39 is output.

[Problems to be Solved by the Invention] In the above-mentioned binarization circuit, when an input signal with fluctuations in the DC voltage component as shown in FIG. 12(a) is input,
In the former binarization circuit, 111! ! Since the signal range of the voltage 43 that exceeds the -7ff voltage 44 is not detected, there may be areas that are not detected, or a phase error may occur in the detected binary signal, causing the problem that accurate binary signals cannot be obtained. Ta.

Figure 12(b) is a waveform diagram showing a binary signal, and the part corresponding to the center of the input signal is properly binarized, and the parts on both sides are lower than the reference voltage of the input signal. Since the signal range is reduced due to variations in the DC voltage component, large phase errors occur.

Also, in the latter binarization circuit, although the DC voltage fluctuation of the low frequency component can be removed, when the frequency of the DC voltage fluctuation approaches the frequency of the modulation signal component of the input signal, the HPF cannot remove the DC voltage component. This was difficult and caused similar problems.

An object of the present invention is to provide a binarization circuit that can extract only the modulated signal component of an input signal and output an accurate binary signal with little phase error.

[Means for solving the problem] The above problem consists of a filter that passes the low frequency component of the input signal, a delay means that delays the input signal, and an output signal from the delay means and a filter that passes the low frequency component of the input signal. This problem is solved by the binarization circuit of the present invention, which has a detection means for detecting a difference between the output signal and a signal generation means for generating a binary signal based on the difference signal outputted from the detection means.

[Function] The present invention passes an input signal through a low-pass transmission filter to extract an output signal of a fluctuation component of the DC voltage of the input signal, and on the other hand, the delay means of the delay means has the same delay time as the delay time caused by passing through the low-pass transmission filter. The DC voltage fluctuation component of the input signal is removed by passing the input signal through to extract the output signal, and taking the difference between this output signal and the output signal of the fluctuation component of the DC voltage, and only the modulation signal component is removed. A binary signal is extracted from the .

[Example] Examples of the present invention will be described in detail below.

In the following description, an optical information recording/reproducing apparatus, which is an example of the use of a binarization circuit, will be taken as an example.

FIG. 3 is a schematic plan view showing the recording format of the optical card.

In the figure, a recording area 2 is provided on an optical card l which is an information recording carrier, and the recording area 2 is formed by arranging a plurality of hands 3. Furthermore, the band 3 is formed by arranging a track 4 and a large number of start bits and stop bits, which will be described later, and the track 4 has an information capacity of about several tens to 100 bits. Further, each hand is separated by a reference line (hereinafter referred to as an R line). Note that arrow A is the direction of movement of the optical card 1 during playback.

FIG. 4 is a schematic diagram of the optical cart regeneration device.

In the same figure, the optical card l is rotated by the rotation mechanism 6 to
It is movable in the direction tm. Information written on the optical card 1 is read and reproduced track by track by the optical head 11. First, light from a light source 7 such as an LED is focused by a lens system 8 and illuminates a certain track 4 on which information is recorded. The image of the illuminated track 4 is formed on the sensor array 10 by the imaging optical system 9, and an electric signal corresponding to the information recorded on the track 4 is transmitted to the sensor array 1.
Output from 0. When the reading of the track 4 is completed, the optical card 1 is moved in the direction of arrow A, or the optical head 11 is moved in the direction of arrangement of the bands 3 (direction of arrow C), and the information of the primary track is read in the same way.

FIG. 5 is a partially enlarged schematic diagram of the recording format of the optical card shown in FIG. 3. However, the shaded area 13a in the figure indicates information "l".

In the figure, the information track 14 is separated from adjacent information tracks in the direction in which the bits of the information track 14 are arranged by a division area 12. Further, a plurality of tracks each consisting of an information track 14 and a separation area 12 are arranged to form a band 3. The hands 3 are arranged in a plurality of rows, and the rows of separation regions 12 within the band 3 serve as R lines for separating adjacent information tracks.

Information on the R line is recorded with a length shorter than the track width of other data areas.

The ratio of the track width of the data area to the information recording width of the R line is about 1 + 1/2.

The data stored in each unit data area 13 is MFM
(Modified Frequency Module
ation) Signals recorded by the 0 eaves modulation method that are modulated and recorded include T, 1.5 T, 2T
Only a signal with a length of is included, where ■ is the minimum inversion interval of the signal, and corresponds to 1 bit in the recording format shown in FIG. That is, the information recorded on the information track 14 does not include reversal intervals of four or more.

Therefore, an area having an inversion interval of 4T is used as a separation area 12 for separating information tracks. for example,
A separation signal of '011110' is recorded in the reading direction or arrangement direction of the information track. Of course, this is not limited to this, but any method can be used to record the separation signal in such a way that it can be distinguished when read. Bye.

Further, the information track 14 has 16 unit data areas 13.
It has a total of 80 bits.

As described above, since the separated region 12 contains consecutive identical codes that do not appear in the information track 14, it is certain that the R line is detected.

Next, a method for reproducing the information recording carrier will be explained.

Here, an optical card is used as an information recording carrier having the recording format shown in FIG. 5, and a reproducing apparatus shown in FIG. 4 is used as a device for reading information from the optical cart. Further, as shown in FIG. 6, the optical magnification is selected here so that one bit 15 in the recording area of the optical card is imaged onto four cells 16 of the sensor array IO. For example, the size of 1 bit 15 on an optical card is l
O4m, the size of the cell 16 of the sensor array 10 is 15
If the number of pixels is m, then the imaging optical system 9 should have a magnification of 4 x 15 / l O = 6 (times).

No. 711W is an explanatory diagram showing a method for reproducing an information recording carrier.

In the figure, in the recording area on the optical card, band 3 and
Bands 3a and 3b adjacent to band 3 and information tracks 14.14a for each band.

14b and separation areas 12, 12a, and 12b for separating each information track are formed in the format shown in FIG. Here, one band track is formed of a total of 86 bits, including a separation area (6 bits) and an information track (80 bits). Therefore, the hand track consists of 344 cells 16 on the sensor array 10.
imaged on top.

Therefore, here, a CCD having 512 cells 16 is used.
is used as the sensor array 10, and information tracks 14a3 and L4 adjacent to the information track 14 to be read are used as the sensor array 10.
The reading area 17 is set so that a part of the area b is also imaged on the sensor array 10.

From the time when the separation area 12 is detected, the information recorded on the information track 14 is reproduced using the extracted clock, and the information reproduction operation is stopped when the separation area 12b is detected.

FIG. 8 is a block diagram of an optical card reproducing apparatus that implements the above reproducing method.

In the figure, a sensor array lO having a reading area 17 receives a driving clock 1 from a sensor array driver 18.
The output signal 20 is also amplified by the driver 18 and sent to the binarization circuit 2 as a video signal 21.
Enter into 2. The video signal binarized by the binarization circuit 22 is sent to a clock regeneration circuit 24 as an NRZT signal 23.
The signals are output to the MFM demodulation circuit 26 and the R line detection circuit 28, respectively.

The clock regeneration circuit 24 takes out the clock signal 25 from the NRZI signal 23 and outputs it to the MFM return path circuit 26 .

The MFM demodulation circuit 26 inputs the clock signal 25 and the NRZr signal 23 and outputs the NRZi signal 27 as a demodulated signal.
7. On the other hand, the R line detection circuit 28 is a frequency divider circuit 2
Inputting the clock signal 30 obtained by frequency-dividing the drive clock 19 from 9 and the NRZI signal 23 from the binarization circuit 22,
The R line detection signal 31 is output to the MFM demodulation circuit 26. The MFM demodulation circuit 26 outputs an NRZ signal 27 in accordance with the R line detection signal 31.

The ninth section is a block diagram of the R line detection circuit 28. In the figure, the NRZI signal 23 is input to the direct input terminal of the shift register 32, and the clock signal 30 whose frequency has been divided by four is input to the clock input terminal. In addition, the 6-bit parallel output terminal of the shift register 32 is “011
110'' are respectively connected to input terminals of a match circuit 33.A match signal of the match circuit 33 is outputted as a line detection signal 31 to the MpuWIi circuit 26.

The concrete operation of the reproducing device having such a configuration will be explained with reference to FIGS. 5 and 7.

When the sensor array IO scans the reading area 17 in the direction of arrow B using the drive clock 19, first the NRZI signal 2
3 is a signal for reading information on a part of the adjacent information tractor 14a. As mentioned above, since the 1M continuous upturn interval is only T, 1.5T, and 2T, this signal is PL
A clock reproducing circuit 24 using an L circuit or the like can extract the minimum inversion interval T and reproduce the clock signal 25. Using this clock signal 25, the NRZ 1 signal 23 is demodulated into an NRZ signal 27 by the MFM demodulation circuit 26. However, the MFM demodulation circuit 26 does not operate unless the first R line detection signal 31 is input. That is, R
The shift register 32 of the line detection circuit 28 is sequentially inputted with each bit signal in the reading area F, and is always filled with six bits worth of signals. Therefore, the R line detection signal 31 is not outputted unless the content stored in the shift register 32 matches the recorded content in the separation area 12 or 12b, that is, 011110''.

When the 6-bit information of the first separation area 12 is stored in the shift register 32, the matching circuit 33 outputs the R line detection signal 31, and the MFM demodulation circuit 26 starts the demodulation operation. Therefore, the NRZ signal 27 corresponding to the information on the information track 14 to be read is output as a reproduction signal.

Then, the information of the next separation area 12b or the shift register 3
2, the matching circuit 33 outputs the R line detection signal 31, and the MFM demodulation circuit 26 stops outputting the reproduced signal.

In this way, information reproduction of the information track 14 to be read is performed by the self-clock. below,
Similarly, by moving the optical cart in the six directions of the arrows or moving the optical head 11 mounted with the sensor array lO''It in the direction of the arrow C, a desired information trough is selected as an object to be read, and the information is reproduced.

Next, the binarization circuit of the present invention used in the above-mentioned optical card reproducing device will be explained.

FIG. 1 shows an embodiment of the binarization circuit of the present invention.

In the same figure, a video signal 21 which is an input signal is LPF
(Low pass filter) 45 and delay means 46.

The LPF 45 passes only low-frequency component signals of the video signal 21. That is, the modulation signal component of the video signal 21 is cut, and the DC voltage fluctuation component is passed.

As the LPF 45, a general Barterworth type circuit, a Chebyshev type circuit, etc. is used, but a circuit with excellent attenuation characteristics from the cutoff frequency is preferable.The delay means 46 is a circuit that occurs when the video signal 21 is passed through the LPF 45. The video signal 21 is delayed by the same amount of time as the delay time. As the delay means 46, a CCD delay element, an LC
A distributed constant type delay circuit or the like can be used.

Output signal 49 of LPF 45 and output signal 5 of delay means 46
The difference between 0 and 0 is determined by an operational amplifier 47 serving as a detection means, and a difference signal 51 is output. This difference signal 51 is input to a non-inverting input terminal of a comparator 48, which is a signal generating means, and is compared with the potential Ov of the inverting input terminal, and a binary signal 39 is output.

The operation of the binarization circuit will be explained below.

FIG. 2 (a) to (d) are waveform diagrams of output signals of each constituent means of the binarization circuit.

FIG. 2(a) is a waveform diagram of the video signal 21 shown in FIG. 8, and the video signal 21 has a DC voltage component and an AC voltage component which is a modulation signal corresponding to the intensity of light incident on the sensor array 10. The result is a superimposed waveform. In the figure, the part where the voltage V of the video signal 21 is lower is the sensor array l.
The amount of light incident on O is large. Therefore, the peak on the negative side of the AC voltage component indicates a high reflectance portion of the optical card, and the peak on the positive side indicates a low reflectance portion. That is, the unevenness of the AC voltage component indicates the content of recorded information.

Note that the video signal 21 is an information pattern in an information track,
Sensitivity unevenness between each element of the sensor array 10, illumination optical system 9
The DC voltage component fluctuates due to uneven lighting, etc.

When this video signal 21 is input to the LPF 45, the output DC voltage changes! The output signal 49 of the h component is shown in FIG.
), a delay of Δt occurs with respect to the video signal 21. The video signal 21 is delayed by the delay means 46 by the same amount of time as the d delay time Δt of the output signal 49, so that the phase of the output signal 50 is the same as that of the output signal 49.

Output signal 49 of LPF 45 and output signal 5 of delay means 46
0 to the operational amplifier 47, the difference signal 51 has the DC voltage fluctuation component removed and becomes only the AC voltage component, as shown in FIG. 2(c). That is, phase errors caused by fluctuation components of the DC voltage are removed.

Since the binary signal 39 outputted by the comparator 48 is generated using the above-mentioned difference signal 51, as shown in FIG.
As shown in the figure, the output signal has a small phase error.

Since the binary signal 39 has no phase error and the entire area illuminated by the illumination optical system can be used effectively, the entire area of the information track imaged on the sensor array 10 can be used as an effective recording area. I can do something. As a result, the optical system design of the illumination optical system and the imaging optical system becomes easier, and the alignment of the optical head and the information track becomes easier. Since there is little chance of phase errors occurring in the binary signal, it also has the effect of reducing the probability of readout errors being extremely low.

[Effects of the Invention] As explained above in detail, according to the binarization circuit of the present invention, the low frequency component of the input signal, y! , generating a difference signal between an output signal of a filter that passes a voltage fluctuation component and an output signal of a delay means that delays the input signal;
By extracting a binary signal from this difference signal, it is possible to reduce the phase error of the binary signal with a simple configuration and obtain an accurate binary signal with fewer reading errors due to fluctuations in the DC voltage component of the input signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining the binarization circuit of the present invention. FIG. 2 is a waveform diagram of output signals from each constituent means of the binarization circuit. FIG. 3 is a schematic plan view showing the recording format of the optical card. FIG. 4 is a schematic diagram of the optical card reproducing device. FIG. 5 is a partially enlarged schematic diagram of the recording format of the optical card. FIG. 6 is an explanatory diagram of the optical magnification of the optical head. FIG. 7 is an explanatory diagram showing a method for reproducing an optical card. FIG. 8 is a block diagram of an optical cart reproducing apparatus that implements the optical card reproducing method. FIG. 9 is a block diagram of the R line detection circuit. FIG. 1O is a circuit diagram showing an example of a conventional binarization circuit. :Bll[] is a circuit diagram showing another example of the conventional binarization circuit. FIG. 12 is a waveform diagram illustrating the operation of a conventional binarization circuit. 38...Video signal 39...Binary signal 45...-LPF 46...Delay means 47...Arithmetic circuit 48...Comparator 49.50...Output signal 51...Difference signal Agent Patent Attorney Seki Yamashita Figure 1 Figure 2 Figure 24 Koi Irogo Figure 6 U Mouth Figure 9 Figure Yellow is also available in 4 prefectures

Claims (1)

[Claims] a filter that passes a low frequency component of an input signal; a delay means that delays the input signal; a detection means that detects a difference between an output signal from the delay means and an output signal from the filter; A binarization circuit comprising signal generation means for generating a binary signal from the output difference signal.