JPS6361151U - - Google Patents
Info
- Publication number
- JPS6361151U JPS6361151U JP1986155092U JP15509286U JPS6361151U JP S6361151 U JPS6361151 U JP S6361151U JP 1986155092 U JP1986155092 U JP 1986155092U JP 15509286 U JP15509286 U JP 15509286U JP S6361151 U JPS6361151 U JP S6361151U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- bare chip
- hybrid integrated
- circuit board
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986155092U JPS6361151U (enExample) | 1986-10-09 | 1986-10-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986155092U JPS6361151U (enExample) | 1986-10-09 | 1986-10-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6361151U true JPS6361151U (enExample) | 1988-04-22 |
Family
ID=31075484
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986155092U Pending JPS6361151U (enExample) | 1986-10-09 | 1986-10-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6361151U (enExample) |
-
1986
- 1986-10-09 JP JP1986155092U patent/JPS6361151U/ja active Pending