JPS6360575B2 - - Google Patents

Info

Publication number
JPS6360575B2
JPS6360575B2 JP17476284A JP17476284A JPS6360575B2 JP S6360575 B2 JPS6360575 B2 JP S6360575B2 JP 17476284 A JP17476284 A JP 17476284A JP 17476284 A JP17476284 A JP 17476284A JP S6360575 B2 JPS6360575 B2 JP S6360575B2
Authority
JP
Japan
Prior art keywords
signal
circuit
feeder
current transformer
feeder current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP17476284A
Other languages
Japanese (ja)
Other versions
JPS6153840A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP17476284A priority Critical patent/JPS6153840A/en
Publication of JPS6153840A publication Critical patent/JPS6153840A/en
Publication of JPS6360575B2 publication Critical patent/JPS6360575B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
    • H04B3/54Systems for transmission via power distribution lines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B2203/00Indexing scheme relating to line transmission systems
    • H04B2203/54Aspects of powerline communications not already covered by H04B3/54 and its subgroups
    • H04B2203/5462Systems for power line communications
    • H04B2203/5466Systems for power line communications using three phases conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は配電線搬送受信方式、詳しくは複数
のフイーダを有する高圧配電線を利用して、負荷
側から電源端へ(以下、上り方向と呼ぶ)伝送す
る信号の受信方式に関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention utilizes a distribution line transmission/reception system, specifically, a high-voltage distribution line having multiple feeders, from the load side to the power source end (hereinafter referred to as the upstream direction). ) This relates to the receiving method of the transmitted signal.

〔従来技術〕[Prior art]

一般に、高圧配電線の金属回路を利用して上り
方向へ信号伝送する場合には、電源端が最もイン
ピーダンスが低いことから、搬送信号として電流
信号を用いている。
Generally, when transmitting a signal in the upward direction using a metal circuit of a high-voltage power distribution line, a current signal is used as a carrier signal because the power supply end has the lowest impedance.

第1図に、上り方向の配電線搬送受信方式の概
念図を示す。同図において、1は配電用主変圧
器、2a〜2cはフイーダしや断器、3は区分用
開閉器、4は連系用開閉器、5は高圧配電線、6
a〜6cはフイーダ変流器、7は配電線搬送受信
装置(以下、受信装置と呼ぶ)、8a〜8cは配
電線搬送送信装置(以下、送信装置と呼ぶ)であ
る。
FIG. 1 shows a conceptual diagram of an upstream distribution line carrier reception system. In the figure, 1 is a main distribution transformer, 2a to 2c are feeder switches, 3 is a division switch, 4 is a interconnection switch, 5 is a high-voltage distribution line, and 6
Numerals a to 6c are feeder current transformers, 7 is a distribution line carrier receiving device (hereinafter referred to as a receiving device), and 8a to 8c are distribution line carrier transmitting devices (hereinafter referred to as a transmitting device).

第1図において、配電系統が正常な状態、すな
わち事故や系統変更がなく、区分用開閉器3がす
べて閉状態で、連系用開閉器4がすべて開状態の
場合には、送信装置8a〜8cが既知のリツプル
コントロール方式等の搬送手段により伝送された
ポーリング信号を受けて送信する、あるいは、あ
らかじめ決められた順序でもつて自動的に送信す
る搬送信号はそれぞれ所定のフイーダ変流器6a
〜6cを介して受信装置7へ取り込まれて受信さ
れる。すなわち、たとえば送信装置8aからの信
号はフイーダ変流器6aを介して受信される。
In FIG. 1, when the power distribution system is in a normal state, that is, there is no accident or system change, and all divisional switches 3 are closed and all interconnection switches 4 are open, transmitting devices 8a to 8c receives and transmits a polling signal transmitted by a known ripple control type carrier means, or transmits a carrier signal automatically in a predetermined order, respectively, to a predetermined feeder current transformer 6a.
~6c, and is taken into the receiving device 7 and received. That is, for example, a signal from the transmitting device 8a is received via the feeder current transformer 6a.

しかしながら、事故が発生したり、工事が行な
われる場合には、当該配電区間を系統から切り離
すために、開閉器操作により系統変更が行われ、
それにともなつて信号伝送経路も変更される。こ
のため、送信装置8a〜8cと受信するフイーダ
変流器6a〜6cは一義的に固定化できなく、し
たがつて受信装置7としては、いずれのフイーダ
変流器6a〜6cからの到来信号も受信できる構
成であることが要求される。
However, in the event of an accident or construction work being carried out, the system will be changed by operating a switch in order to disconnect the relevant distribution section from the system.
Along with this, the signal transmission path is also changed. For this reason, the transmitting devices 8a to 8c and the receiving feeder current transformers 6a to 6c cannot be fixed uniquely, and therefore the receiving device 7 cannot accept the incoming signals from any of the feeder current transformers 6a to 6c. It is required that the configuration is capable of receiving.

以上のような背景にあつて、従来は第2図に示
すような回路構成の受信装置と第3図に示すよう
な符号構成の搬送信号でもつて配電線搬送を行な
つていた。第3図で、FDWはフイーダ検出ワー
ド、SWは同期ワード、AWはアドレスワード、
DWはデータワードである。
In the background described above, conventionally, distribution line transmission has been carried out using a receiver having a circuit configuration as shown in FIG. 2 and a carrier signal having a code configuration as shown in FIG. In Figure 3, FDW is the feeder detection word, SW is the synchronization word, AW is the address word,
DW is a data word.

さて、第2図において、9はフイーダ変流器6
a〜6cをサイクリツクに切替えるスキヤニング
回路、10は商用周波やその高調波などの雑音成
分を取り除き、信号周波成分のみ通過させるフイ
ルタ、11は受信信号を復調する復調回路、12
は信号の同期ワードSWの立下りを検出する同期
検出回路、13は同期検出回路12の出力を受け
て復調のタイミングを制御するクロツク回路、1
4はマイクロプロセツサ等で構成されて復調回路
11で復調されたデータを処理するデータ処理回
路、15は信号が到来したことを検出する信号レ
ベル判別回路、16はスキヤニング回路9を制御
する制御回路である。
Now, in Fig. 2, 9 is the feeder current transformer 6.
10 is a filter that removes noise components such as commercial frequencies and their harmonics and passes only signal frequency components; 11 is a demodulation circuit that demodulates the received signal; 12
1 is a synchronization detection circuit that detects the fall of the synchronization word SW of the signal; 13 is a clock circuit that receives the output of the synchronization detection circuit 12 and controls the timing of demodulation;
4 is a data processing circuit that is composed of a microprocessor or the like and processes the data demodulated by the demodulation circuit 11; 15 is a signal level discrimination circuit that detects the arrival of a signal; 16 is a control circuit that controls the scanning circuit 9; It is.

第4図はスキヤニング回路9がフイーダ変流器
6a〜6cをサイクリツクに切替えるタイミング
の一例を示したタイムチヤートで、同図Aはフイ
ーダ変流器6aに到来した信号、同図Bはフイー
ダ変流器6aを選択するタイムチヤート、同図C
はフイーダ変流器6bを選択するタイムチヤー
ト、同図Dはフイーダ変流器6cを選択するタイ
ムチヤートである。T1は信号内のフイーダ検出
ワードFDWの時間長、T2はスキヤニング回路9
がフイーダ変流器6a〜6cを順次切替える切替
時間、T3はスキヤニングの1サイクル時間長で
ある。
FIG. 4 is a time chart showing an example of the timing at which the scanning circuit 9 cyclically switches the feeder current transformers 6a to 6c. FIG. 4A shows the signal arriving at the feeder current transformer 6a, and FIG. Time chart for selecting device 6a, same figure C
is a time chart for selecting the feeder current transformer 6b, and D is a time chart for selecting the feeder current transformer 6c. T 1 is the time length of the feeder detection word FDW in the signal, T 2 is the scanning circuit 9
is the switching time for sequentially switching the feeder current transformers 6a to 6c, and T3 is the length of one cycle of scanning.

つぎに動作について説明する。スキヤニング回
路9は、信号が到来していない状態では、T2
間隔でもつて順次フイーダ変流器6a〜6cをス
キヤニングしている。そしてたとえば第4図に示
すように、t1の時点でフイーダ変流器6aに信号
が到来すると、フイーダ変流器6aのスキヤニン
グ時点t2で、フイルタ10を通過した信号は信号
レベル判別回路15へ入力され、信号の到来が検
出されて、制御回路16を介してスキヤニング回
路9は当該フイーダ変流器6aにロツクされる。
すると、信号はフイルタ10を通過して復調回路
11と同期検出回路12へ入力される。同期検出
回路12では、信号の同期ワードSWの立下りの
タイミングを検出してクロツク回路13から復調
回路11へ復調のタイミングクロツク信号が入力
される。復調回路11で復調されたアドレスとデ
ータはデータ処理回路14で所定の処理が行なわ
れて受信は完了する。
Next, the operation will be explained. The scanning circuit 9 sequentially scans the feeder current transformers 6a to 6c at intervals of T2 when no signal is received. For example, as shown in FIG. 4, when a signal arrives at the feeder current transformer 6a at time t1 , at the scanning time t2 of the feeder current transformer 6a, the signal that has passed through the filter 10 is sent to the signal level discrimination circuit 15. The arrival of the signal is detected, and the scanning circuit 9 is locked to the feeder current transformer 6a via the control circuit 16.
Then, the signal passes through the filter 10 and is input to the demodulation circuit 11 and the synchronization detection circuit 12. The synchronization detection circuit 12 detects the fall timing of the synchronization word SW of the signal, and a demodulation timing clock signal is input from the clock circuit 13 to the demodulation circuit 11. The address and data demodulated by the demodulation circuit 11 are subjected to predetermined processing in the data processing circuit 14, and reception is completed.

信号の受信が完了すると、すなわち信号の到来
が終了すると(t3の時点)、信号レベル判別回路
15から出力がなくなり、制御回路16の指令に
よりスキヤニング回路9はつぎのフイーダ変流器
6bの選択から通常のスキヤニング動作に復帰し
(t4の時点)、つぎの受信に備える。
When the reception of the signal is completed, that is, when the arrival of the signal ends (at time t3 ), the output from the signal level discrimination circuit 15 disappears, and the scanning circuit 9 selects the next feeder current transformer 6b according to a command from the control circuit 16. Returns to normal scanning operation (at time t 4 ) and prepares for the next reception.

ここで、受信するフイーダ変流器6a〜6bの
正常な選択を行なうために必要な信号のフイーダ
検出ワードFDWの時間長T1と切替間隔T2および
スキヤニングサイクルT3の関係はT1>T3=3×
T2なる関係が成立すればよい。
Here, the relationship between the time length T 1 of the feeder detection word FDW of the signal necessary for normal selection of the receiving feeder current transformers 6a to 6b, the switching interval T 2 and the scanning cycle T 3 is T 1 > T3 =3×
It suffices if the relationship T 2 holds true.

従来の受信装置は以上のように構成されている
ので、それぞれの送信装置8a〜8cから搬送信
号が重さならないように順次送信されてくる場合
には、すべて受信可能であるが、場合によつては
複数個の送信装置8a〜8cから複数のフイーダ
を経由して同時に送信されてくる場合もあり、こ
の場合にはフイーダのスキヤニングにより最初に
捕獲したフイーダの信号のみの受信となり、他の
フイーダの信号は無視されることになる。
Since the conventional receiving device is configured as described above, if the carrier signals are sequentially transmitted from each of the transmitting devices 8a to 8c so as not to overlap, they can all be received. In some cases, signals are simultaneously transmitted from multiple transmitting devices 8a to 8c via multiple feeders, and in this case, by scanning the feeder, only the signal of the first captured feeder is received, and the signals of other feeders are transmitted simultaneously. signals will be ignored.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除
去するためになされたもので、信号の到来するフ
イーダを検出する回路と、受信する回路を分けて
構成することにより、複数のフイーダから同時に
複数の信号が到来した場合には、1つのフイーダ
の信号は正常受信し、その他の信号到来フイーダ
は、信号が到来したことのみ検出して、たとえば
後で当該フイーダに接続されている送信装置へ一
斉呼出しを行なう等の手段により、送信した送信
装置を捕獲できる配電線搬送受信方式を提供する
ことを目的としている。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by configuring a circuit for detecting the feeder from which the signal arrives and a circuit for receiving the signal separately, it is possible to simultaneously receive multiple signals from multiple feeders. When a signal arrives, one feeder receives the signal normally, and the other feeders that receive the signal only detect the arrival of the signal and, for example, later call all the transmitting devices connected to that feeder. It is an object of the present invention to provide a distribution line transmission/reception system that can capture a transmitting device by such means as performing the following steps.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図面に基づいて説
明する。
Hereinafter, one embodiment of the present invention will be described based on the drawings.

第5図はこの発明に係る配電線搬送受信方式に
適用した受信装置の一例を示し、第3図と同一部
所には同一符号を付して説明を省略する。同図に
おいて、10aおよび10bは信号周波成分のみ
通過させるフイルタ、17はフイーダ変流器6a
〜6cを選択する選択回路、18はリツプルコン
トロール方式等の送信部である。
FIG. 5 shows an example of a receiving device applied to the distribution line carrier receiving system according to the present invention, and the same parts as those in FIG. In the figure, 10a and 10b are filters that pass only signal frequency components, and 17 is a feeder current transformer 6a.
.about.6c, and 18 is a transmitter using a ripple control method or the like.

第6図はスキヤニング回路9および選択回路1
7が到来信号との関連においてフイーダ変流器6
a〜6cを選択するタイミングの一例を示したタ
イムチヤートで、同図Aはフイーダ変流器6aに
到来した信号、同図Bはフイーダ変流器6bに到
来した信号、同図Cはスキヤニング回路9がフイ
ーダ変流器6aを選択するタイムチヤート、同図
Dは同様にフイーダ変流器6bを選択するタイム
チヤート、同図Eは同様にフイーダ変流器6cを
選択するタイムチヤート、同図Fは選択回路17
がフイーダ変流器6aを選択するタイムチヤート
である。T4は信号長、T5は選択回路17が受信
するためにフイーダ変流器6aを選択して接続し
ている時間である。
Figure 6 shows scanning circuit 9 and selection circuit 1.
7 is the feeder current transformer 6 in relation to the incoming signal.
This is a time chart showing an example of the timing for selecting a to 6c, in which A shows the signal arriving at the feeder current transformer 6a, B shows the signal arriving at the feeder current transformer 6b, and C shows the scanning circuit. 9 is a time chart for selecting the feeder current transformer 6a, D is a time chart for selecting the feeder current transformer 6b, E is a time chart for selecting the feeder current transformer 6c, and F is a time chart for selecting the feeder current transformer 6c. is the selection circuit 17
is a time chart for selecting the feeder current transformer 6a. T 4 is the signal length, and T 5 is the time during which the selection circuit 17 selects and connects the feeder current transformer 6a for reception.

つぎに動作について説明する。スキヤニング回
路9は信号の到来を見逃すことのないようにT2
の間隔でもつて順次フイーダ変流器6a〜6cを
スキヤニングしている。そして、たとえば第6図
に示すように、t1の時点でフイーダ変流器6aに
信号が到来すると、フイーダ変流器6aのスキヤ
ニング時点t2で、フイルタ10を通過した信号は
信号レベル判別回路15へ入力され、ここで信号
の到来が検出されて、制御回路16へ出力され
る。制御回路16はこの出力信号を受けて信号の
到来がフイーダ変流器6aであることを判断し、
選択回路17へ、フイーダ変流器6aを選択して
接続するように指令する(t6の時点)。すると、
信号は従来の受信回路と同様に、同期検出回路1
2、クロツク回路13、復調回路11およびデー
タ処理回路14により正常に受信される。選択回
路17によりフイーダ変流器6aへ接続されて、
所定の時間T5が経過すると、制御回路16から
選択回路17へ切り離し指令が出力されて、フイ
ーダ変流器6aは切り離される(t7の時点)。
Next, the operation will be explained. The scanning circuit 9 is connected to T 2 so as not to miss the arrival of the signal.
The feeder current transformers 6a to 6c are sequentially scanned at intervals of . For example, as shown in FIG. 6, when a signal arrives at the feeder current transformer 6a at time t1 , at the scanning time t2 of the feeder current transformer 6a, the signal that has passed through the filter 10 is sent to the signal level discrimination circuit. The signal is input to the control circuit 15, where the arrival of the signal is detected and output to the control circuit 16. The control circuit 16 receives this output signal and determines that the signal is coming from the feeder current transformer 6a,
A command is given to the selection circuit 17 to select and connect the feeder current transformer 6a (at time t6 ). Then,
The signal is sent to the synchronization detection circuit 1 as in the conventional receiving circuit.
2. Normally received by the clock circuit 13, demodulation circuit 11 and data processing circuit 14. connected to the feeder current transformer 6a by the selection circuit 17;
When the predetermined time T5 has elapsed, a disconnection command is output from the control circuit 16 to the selection circuit 17, and the feeder current transformer 6a is disconnected (at time t7 ).

一方、スキヤニング回路9は受信中のフイーダ
変流器6aを除いた残りのフイーダ変流器6b,
6cに対しT3のサイクルでスキヤニングの動作
を継続し、信号の到来を待ち受ける。フイーダ変
流器6aのスキヤニング動作は選択回路17が解
放後、t4の時点から再開される。
On the other hand, the scanning circuit 9 is connected to the remaining feeder current transformers 6b, excluding the feeder current transformer 6a that is receiving data.
The scanning operation is continued in the cycle T3 for 6c , and the arrival of a signal is waited for. The scanning operation of the feeder current transformer 6a is resumed from time t4 after the selection circuit 17 is released.

フイーダ変流器6aに到来した信号を受信中の
t5の時点にフイーダ変流器6bに到来した信号
は、t8の時点でフイルタ10a、信号レベル判別
回路15を介して検出されるが、選択回路17以
降、データ処理回路14までの受信回路がフイー
ダ変流器6aの到来信号を受信中であることを、
制御回路16が判断し、フイーダ変流器6bから
も信号が到来したことを記憶する。そして、フイ
ーダ変流器6aからの到来信号の受信が完了した
t7の時点で、制御回路16は、送信部18へ指令
して、フイーダ変流器6bへ連系された送信装置
群へ再送信指令信号を送る等の手段でもつて当該
送信装置からの再送信を受け、正常受信を完了さ
せる。
While receiving the signal arriving at the feeder current transformer 6a
The signal that arrives at the feeder current transformer 6b at time t5 is detected via the filter 10a and the signal level discrimination circuit 15 at time t8 , but the signal that arrives at the feeder current transformer 6b at time t8 is detected by the receiving circuits from the selection circuit 17 to the data processing circuit 14. is receiving the incoming signal of the feeder current transformer 6a.
The control circuit 16 makes a judgment and stores that the signal has also arrived from the feeder current transformer 6b. Then, the reception of the incoming signal from the feeder current transformer 6a is completed.
At time t7 , the control circuit 16 instructs the transmitter 18 to stop the retransmission from the transmitter by sending a retransmission command signal to the transmitter group connected to the feeder current transformer 6b. Receive the transmission and complete normal reception.

なお、上記実施例では高圧配電線が3フイーダ
の場合について示したが、一般的にフイーダ数が
nの場合には、信号のフイーダ検出ワードFDW
の時間長T1とスキヤニング回路9の切替間隔T2
およびスキヤニングサイクルT3の間にT1>T3
n×T2なる関係を満足させさえすれば、上記実
施例と同様の回路構成でもつて、高圧配電線に散
在する複数の送信装置から複数のフイーダを介
し、時間的にラツプして到来した複数の信号のう
ち、1つは正常受信し、その他の信号については
到来フイーダを捕獲することができ、したがつ
て、いかなる配電系統においてもこの発明は適用
できる。
Although the above embodiment shows the case where the high voltage distribution line has three feeders, generally when the number of feeders is n, the feeder detection word FDW of the signal is
time length T 1 and switching interval T 2 of the scanning circuit 9
and during scanning cycle T 3 T 1 > T 3 =
As long as the relationship n x T 2 is satisfied, even if the circuit configuration is the same as that of the above embodiment, multiple transmitters that arrive from multiple transmitters scattered on the high-voltage distribution line via multiple feeders and that are wrapped in time can be used. One of the signals is normally received, and the other signals can be captured by the incoming feeder. Therefore, the present invention can be applied to any power distribution system.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、信号の到来
するフイーダを検出する回路と受信する回路を合
せ持つ構成としたので、信号の到来をもれなく捕
獲することができる効果がある。
As described above, according to the present invention, since the structure has both a circuit for detecting the feeder where the signal arrives and a circuit for receiving the signal, it is possible to capture the arrival of the signal without exception.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は高圧配電線の負荷側から電源側へ信号
伝送する配電線搬送受信方式を示す概念図、第2
図は従来の配電線搬送受信方式に適用されている
受信装置を示すブロツク構成図、第3図は配電線
搬送受信信号の符号構成を示す図、第4図は従来
の受信動作例を示すタイムチヤート、第5図はこ
の発明に係る配電線搬送受信方式の受信装置の一
例を示すブロツク構成図、第6図はこの発明の受
信動作例を示すタイムチヤートである。 1……配電用主変圧器、2a〜2c……フイー
ダしや断器、3……区分用開閉器、4……連系用
開閉器、5……高圧配電線、6a〜6c……フイ
ーダ変流器、7……配電線搬送受信装置、8a〜
8c……配電線搬送送信装置、9……スキヤニン
グ回路、10……フイルタ、11……復調回路、
12……同期検出回路、13……クロツク回路、
14……データ処理回路、15……信号レベル判
別回路、16……制御回路、17……選択回路、
18……送信部。なお、図中、同一符号は同一も
しくは相当部分を示す。
Figure 1 is a conceptual diagram showing the distribution line carrier/receiver system that transmits signals from the load side of the high-voltage distribution line to the power supply side.
The figure is a block configuration diagram showing a receiving device applied to a conventional distribution line carrier reception system, Figure 3 is a diagram showing the code structure of a distribution line carrier reception signal, and Figure 4 is a timing diagram showing an example of a conventional reception operation. FIG. 5 is a block diagram showing an example of a receiving apparatus using a distribution line carrier receiving system according to the present invention, and FIG. 6 is a time chart showing an example of the receiving operation of the present invention. 1... Distribution main transformer, 2a to 2c... Feeder switch, 3... Division switch, 4... Grid connection switch, 5... High voltage distribution line, 6a to 6c... Feeder Current transformer, 7... Distribution line carrier/receiver, 8a~
8c... Distribution line carrier transmitter, 9... Scanning circuit, 10... Filter, 11... Demodulation circuit,
12...Synchronization detection circuit, 13...Clock circuit,
14...Data processing circuit, 15...Signal level discrimination circuit, 16...Control circuit, 17...Selection circuit,
18... Transmission section. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 複数のフイーダを有する高圧配電線の金属回
路を伝送路として、負荷側から電源端へ電流信号
を伝送する配電線搬送受信方式において、搬送信
号の到来フイーダをスキヤニング方式を用いて自
動的に検出する手段と、該検出信号を受けて受信
フイーダを選択し、受信する手段とを設けたこと
を特徴とする配電線搬送受信方式。
1. In a distribution line carrier/receiver system that transmits current signals from the load side to the power source end using the metal circuit of a high-voltage distribution line with multiple feeders as a transmission path, the feeder at which the carrier signal arrives is automatically detected using a scanning method. 1. A distribution line carrier reception system, comprising means for receiving the detection signal, selecting a receiving feeder, and receiving the detection signal.
JP17476284A 1984-08-22 1984-08-22 Distribution line carrier reception system Granted JPS6153840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17476284A JPS6153840A (en) 1984-08-22 1984-08-22 Distribution line carrier reception system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17476284A JPS6153840A (en) 1984-08-22 1984-08-22 Distribution line carrier reception system

Publications (2)

Publication Number Publication Date
JPS6153840A JPS6153840A (en) 1986-03-17
JPS6360575B2 true JPS6360575B2 (en) 1988-11-24

Family

ID=15984225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17476284A Granted JPS6153840A (en) 1984-08-22 1984-08-22 Distribution line carrier reception system

Country Status (1)

Country Link
JP (1) JPS6153840A (en)

Also Published As

Publication number Publication date
JPS6153840A (en) 1986-03-17

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