JPS635956B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mask signal generation circuit for an image processing apparatus.

In an image processing device that analyzes geometric features of an image from an image signal obtained by raster scanning an image of an object to be processed, the raster scanning area and the area from which features should be extracted do not match. There is. At this time, unnecessary (undesirable) image signals are input to feature extraction, so good image processing results cannot be expected.

For example, when processing a microscopic image of a specimen filled in a circular container, the raster scanning screen is rectangular, so in order to obtain an image signal of the specimen inside the container, the entire container must be included in the rectangular raster. There must be. This inevitably results in input of undesirable images such as the edge of the container or an image of the container itself. This causes poor image processing results.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit that generates a mask signal that inhibits extraction of features in regions other than those in which features should be extracted within one scanning region.

According to the present invention, there is provided a binarization circuit that binarizes an image signal from an imaging device that outputs a two-dimensional image signal through a plurality of scans with sequentially different scanning positions, using a predetermined threshold; When one scanning time is H, the output of the binarization circuit is nH− _Δ1 (where n: an integer,
Δ ₁ : The first one that gives a delay of Δ ₁ <H) at any time
a second delay circuit that provides a delay of nH+Δ ₂ (where Δ ₂ is Δ ₂ <H−Δ ₁ at any given time) to the output of the binarization circuit; A mask signal generation circuit for an image processing apparatus is provided, including an AND circuit that generates an AND output of delay circuit outputs as a mask signal for the image signal.

If the threshold value of this binarization circuit is set to a value that can separate the image signal into an undesirable image signal and an image signal to be processed, the logical product of the outputs of the first and second delay circuits can be set. The output is obtained by removing both edges of the binarized output in accordance with the image signal to be processed. In other words, the logical product output is a good image to be processed among the images, which is further binarized so as not to include edge portions. Therefore, by connecting an inhibition circuit that uses this AND output as a mask signal to the circuit that transmits image signals from the imaging device to the image processing circuit, only good image signals can be sent to the image processing circuit. can be transmitted.

Hereinafter, the present invention will be explained based on examples. First, a case will be described in which the raster scanning area and the feature extraction area are different. In Fig. 1, a microtest plate 1 has a plurality of wells 1a (60 wells) for filling liquid specimens in lymphocyte cytotoxicity tests, etc.
has. This well 1a is formed into a conical shape with a circular bottom surface. As shown in FIG. 2, the wells 1a are filled with a liquid specimen 2, and each well 1a is covered with a cover glass 3. Object 2a settled at the bottom of well 1a
are, for example, lymphocytes extracted from blood for a lymphocyte cytotoxicity test.

A microscopic image of this well 1a observed from the bottom side shows the edge 1 of the well 1a as shown in FIG.
Lymphocytes 2a are observed within the boundary a' (at this time, the focus of the microscope is adjusted to the bottom of the well). Here, it must be noted that there is a difference in density level between the image of the inside of the well (ie, the sample) and the image of the well itself. In other words, if you raster scan this microscope image and measure the image signal obtained from the scanning line at the position indicated by the line segment Differences can be seen in the signal levels of the samples inside the wells.

When this image signal is taken out in time series, as shown in Fig. 4, as the scanning progresses, a signal region S ₁ of a level corresponding to the outside of the well, a signal region S 2 of a level corresponding to the well edge, and a signal region S ₂ of a level corresponding to the inside of the well appear as the scanning progresses. Signal region S ₃ appears, followed by well edge,
Signal area S ₂ ′ at the level corresponding to the outside of the well,
S ₁ ′ appears.

FIG. 5 shows a circuit for forming a mask signal for extracting a signal inside a well from the image signal as described above, and FIG. 6 shows a timing chart. In the figure, an imaging device 11 is, for example, a progressive scanning type TV camera, and outputs the image signal A shown in FIG. 4 in time series by raster scanning the microscope image. The binarization circuit 12 is a threshold value
The image signal A is binarized by T ₁ and a binarized output B is output. This threshold value T ₁ is set so that an image signal at a level corresponding to the outside of the well is set to a logic value of "0", and an image signal at a level higher than that is set to a logic value of "1". The digital delay circuit 13 outputs a delay output C that gives an image signal A a delay of (1H - Δ ₁ ) when one scanning time of the imaging device 11 is (1H), and the digital delay circuit 14
outputs a delayed output D which is a delay of (1H+Δ ₂ ) given to the image signal A. Here, the times Δ ₁ and Δ ₂ are arbitrary times, and may be determined to be equal or different from each other as necessary. The AND gate circuit 15 inputs the delayed outputs C and D and outputs a mask signal E. This mask signal is an output in which the rise time of the binary output B is delayed by Δ ₂ and the fall time is advanced by Δ ₁ . In other words,
The mask signal E is an output signal obtained by removing the time period during which the binarized output B is "1" by Δ ₁ and Δ ₂ from both sides in time series.

On the other hand, the image signal A from the imaging device 11 is branched and processed by the analog delay circuit 17 for one scanning period.
A delay of only 1H is given. Mask signal E
A delayed image signal from a delay circuit 17 is applied to the inhibition circuit 16 to which is applied as a control input. Then, the prohibition circuit 16 allows the delayed image signal to pass to the image processing circuit 18 only when the mask signal E is "1", and prohibits the delay image signal from passing at other times.

Here, since the time during which the mask signal E is "1" is reduced by Δ ₁ and Δ ₂ minutes shorter than that of the binarized output B, the inhibition circuit 16 causes the image processing circuit 18 to The image signal that is prohibited from passing is the third
As shown by the dashed line in the figure, it can be applied to the inside of the well. In other words, image processing circuit 1
The image signals input to 8 are limited to those from further inside the well edge. This is Δ ₁ ,
It can be freely selected depending on the setting of _Δ2 . Therefore, image signals outside the well and at the well edge are not input to the processing circuit.

In this embodiment, the mask signal formed from the image signal obtained by scanning the line segment xy becomes the mask signal for the image signal obtained by the same scanning, and so-called real-time masking is performed. It's on. However, in FIG. 5, the image signal A may be directly applied to the inhibition circuit 16 without going through the delay circuit 17. At this time, since there is almost no change in the image pattern for two vertically adjacent scanning lines in the raster scan, it can be used as a mask signal for an image signal delayed by one scan from the image signal A.

Incidentally, the delay circuits 13 and 14 can be easily constructed using shift registers. Further, the delay times of the delay circuits 13, 14, and 17 can be set to nH (n: an integer), where n is made equal.

However, in the above explanation, the video signal caused by lymphocytes was ignored for simplicity, but changes in the video signal caused by lymphocytes are binarized and can be prevented from affecting the mask signal. This will be explained later.

Next, another embodiment of the present invention will be described. This embodiment attempts to eliminate the adverse effects caused by the presence of air bubbles 4 in the wells in FIG.

Conventionally, a cover glass was required to optically flatten the surface of the liquid sample in the well and ensure correct microscopy. The image deteriorates and good results cannot be expected from image processing in such areas. Therefore, we take advantage of the fact that in the image signal obtained by scanning a well, there is a difference in density level between the inside and outside of the well, or the area in good condition inside the well and the area affected by the presence of air bubbles. In this way, a mask signal is obtained that can prohibit image processing for these undesirable areas.

Fig. 7 shows an example of an image of a well containing lymphocytes to be measured and undesirable air bubbles, and Fig. 8 shows an image signal obtained from the scanning line at the position indicated by xy in Fig. 7. It shows. As shown here, the outside of the well is usually darker than the inside of the well, and the bubble is brighter in the center and darker around it. The measurement target using a microtest plate is usually a microscopic cell such as a lymphocyte, and the change in the image signal due to this occurs in a shorter time than that caused by an air bubble or the like.

Embodiments of the present invention will be described below. FIG. 9 shows an embodiment of the present invention. The circuit in the figure includes an imaging device 21 and binarization circuits 22 and 23 based on different threshold values T ₁ and T ₂ , respectively. This threshold value T ₁ is set at a level that allows detection of the well body, but may also detect processing targets (lymphocytes) at the same time. Further, the threshold value T ₂ is set to a level at which bubbles can be detected. The circuit shown is further triggered by an inverter 24, an AND gate 25, and a negative edge. Monostable multivibrator 2
6. Delay circuit 2 that delays the signal for a time slightly longer than the propagation delay time of the monostable multivibrator 26
7. OR gate 28, 1 scanning time each (1H)
It includes delay circuits 29 and 30, an AND gate 31, and an image processing circuit 32 similar to those described above, which provide a delay time that is earlier or earlier by Δ. It is assumed that the prohibition circuit is included in the image processing circuit 32.

The following explanation will be given by taking the image signal of FIG. 8 as an example and referring to the timing chart of FIG. 10.

The image signal A obtained from the imaging device 21 is binarized using two different thresholds T ₁ and T ₂ , respectively.
0 becomes binary signals C and B. Signal B becomes logic "0" in the bubble region, and signal C becomes logic "0" outside the well. A binary signal D is obtained by logically multiplying these signals using an AND gate 25. The signal D becomes logic "0" depending on the measurement target (lymphocytes). Therefore, the "0" caused by the object is erased by taking advantage of the fact that the object is smaller than the bubble. In this embodiment, this is done using a monostable multi 26, a delay circuit 27, and an OR gate 28. The pulse duration of the monostable multi 26 is made sufficiently longer than the time during which changes occur due to the measurement target (lymphocytes). As a result, a binary signal G with minute changes eliminated is obtained. However, as it is, the binary signal G has a long trailing edge due to the above erasing operation, making it unsuitable for use as a mask signal. Therefore, the delay circuits 29 and 30 are used to remove both edges of the signal. This can be done by using the delay circuits 29 and 30 as described above to provide delays by Δ and Δ', respectively, from the time required for one scanning time (1H). A desired mask signal J can be obtained by ANDing the two delay circuit outputs H and I using an AND gate 31. This mask signal J
is a time-series view of the logic “1” region of the binary signal (OR output) G, and delays the rise time by Δ′,
It is also an output whose fall time is advanced by Δ.
Therefore, the image signal corresponding to the image within the area indicated by the dashed line in FIG. 7 is input to the image processing circuit. This mask signal J is obtained one scanning time later than the image signal A, but since the positions of inappropriate areas are almost the same for two upper and lower adjacent scanning lines in raster scanning, this mask signal J
It can be said that there is nothing wrong with using this as a mask signal for an image signal delayed by one scan from image signal A. The mask signal J thus obtained is applied to the image processing circuit 32 and used to prohibit measurement in inappropriate areas.

FIG. 11 shows another embodiment that does the same thing as the embodiment of FIG. 9, and FIG. 12 shows its timing chart. By passing the image signal A from the imaging device 11 through the low-pass filter 51,
The wave signal A′ is obtained by eliminating minute change components corresponding to lymphocytes. This wave signal A' becomes a binarized signal ab which is binarized by a binarization circuit 52 having a threshold value T ₁ and a binarization circuit 53 having a threshold value T ₂ . The binarized signal a includes a "0" signal corresponding to the bubble in the wave signal A', and the binarized signal b includes a "1" signal corresponding to the well region 1a of the filtered signal A'.
Contains signals. The delay circuit 54 converts the binary signal a into
The delay circuit 55 generates a delayed output C which is delayed by 1H- _Δ1 , and a delayed output d which is delayed by 1H+ _Δ2 to the binary signal a. An AND gate 56 generates an AND output e of these delayed outputs c and d. This AND output e serves to erase the image signal within the bubble by removing both sides of the logic "0" of the binarized output a. Furthermore, the delay circuit 57 has two
Delayed output f that gives value signal b a delay of 1H− _Δ3
The delay circuit 58 generates a delayed output g, which is the binary signal b delayed by 1H+ _Δ4 . The AND gate 59 generates an AND output h of these delayed outputs f and g. This AND output h serves to remove both ends of the logic "1" of the binarized output b and extract only the image signal inside the well.

The AND gate 60 outputs the AND output i of the AND outputs e and h as a mask signal.

FIG. 13 shows another example of the embodiment shown in FIG. It is converted into a value and inputted as output K to an AND gate (inhibition circuit) 37. On the other hand, outputs H and I are input to this AND gate 37.
Therefore, output K is input to the image processing circuit only when outputs H and I both become "1".

As described above, according to the present invention, if a binary signal for an area unsuitable for measurement is obtained, a mask signal for that area can be created, so that when performing image measurement, a prohibition is imposed on an area unsuitable for measurement. This can improve reliability, especially for automatic measurements. It is particularly effective for microscopic specimens, lymphocytes, etc. observed in the wells of microtest plates, and eliminates the negative effects on measurements caused by air bubbles that occur between the liquid specimen in the wells and the cover glass. However, it is also possible to suppress noise generation outside the well and improve the reliability of measurement.

[Brief explanation of the drawing]

FIG. 1 is a top view of a microtest plate for filling liquid specimens used in lymphocyte cytotoxicity tests, etc., FIG. 2 is an enlarged partial sectional view of the microtest plate, and FIG. 3 is a top view of the microtest plate. Figure 4 shows a microscopic image of the bottom surface of the well; Figure 4 is a diagram showing an image signal obtained from the scanning line at the position indicated by the line segment xy in Figure 3; Figure 5
The figure shows a block diagram of a circuit for forming a mask signal for extracting a signal inside a well from the image signal of FIG. 4 according to an embodiment of the present invention, and FIG. 6 shows a timing chart of signals of the circuit of FIG. 5. Figure 7 shows a microscopic image of the bottom of a well where lymphocytes to be measured and undesirable air bubbles are present.
This figure shows an image signal obtained from the scanning line at the position indicated by the line segment xy in FIG. 7, and FIG. 9 shows an image signal obtained from the image signal in FIG. FIG. 10 is a block diagram of a circuit that forms a mask signal for extracting the signal of FIG. A block diagram of a circuit of still another embodiment of the present invention, FIG. 12 is similar to FIG. 11.
A diagram showing a timing chart of the signals of the circuit in Figure,
FIG. 13 is a block diagram of a circuit for forming a mask signal for extracting a signal inside a well according to still another embodiment of the present invention. Explanation of codes of main parts, binarization circuit...12,
First delay circuit...13, second delay circuit...1
4. AND circuit...15.

Claims (1)

[Scope of Claims] 1. A binarization circuit that binarizes an image signal from an imaging device that outputs a two-dimensional image signal through a plurality of scans at sequentially different scanning positions using a predetermined threshold; When one scanning time of the scanning is set to H, the output of the binarization circuit is nH− _Δ1 (where n: an integer,
Δ ₁ : The first one that gives a delay of Δ ₁ <H) at any time
a second delay circuit that provides a delay of nH+Δ ₂ (where Δ ₂ is Δ ₂ <H−Δ ₁ at any given time) to the output of the binarization circuit; 1. A mask signal generation circuit for an image processing apparatus, comprising: an AND circuit that generates an AND output of delay circuit outputs as a mask signal for the image signal.