JPS6359476B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic timepiece equipped with a display modulation circuit that changes the size of numbers or characters displayed on a dot matrix display device. In recent years, with the advancement of electronic watches, they have come to be equipped with a wide variety of functions. As devices become more multi-functional, displays that correspond to each function are required.For example, in the case of a battery life detection function, the entire displayed digits of the time display may be simply flashed, or only the colon mark may be flashed. Displays have been used to notify battery life, and other display methods have been used in which the selected digit simply flashes when the normal time or alarm time is being corrected or set. However, as mentioned above, although a simple flashing display had a warning effect (appealing effect) to the user, electronic watches that display multiple functions each display a flashing display, which is very confusing. In addition, the display was difficult to read because it turned on and off in short intervals as a warning, and could not be said to be a sufficient display method. An object of the present invention is to improve the above-mentioned drawbacks by inputting a clock signal from a clock circuit and displaying a dot matrix display device using a detection signal from a state detection circuit that detects the internal state of the clock. An object of the present invention is to provide an electronic timepiece using a new display method provided with a display modulation circuit for changing the size of numbers or characters. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit block diagram of the first embodiment of the electronic timepiece of the present invention, and FIG. FIG. 3 is a circuit block diagram of the second embodiment of the electronic timepiece of the present invention, and FIG. 4 A to D are dot matrix displays in FIG. FIG. 3 is a plan view showing each display state displayed on the device. 1 is a crystal oscillation circuit that uses a crystal oscillator as a time reference; 2 is a frequency divider circuit that divides the frequency by receiving the oscillation signal from the oscillation circuit 1 as input; This is a timekeeping circuit that receives a signal as input and performs timekeeping operation. 4 is a display modulation circuit, which is composed of a normal decoder circuit 4a, a modulation decoder circuit 4b, a switching circuit 4c, and a driver circuit 4d;
The normal decoder circuit 4a and the modulation decoder circuit 4b both receive the clock signal from the clock circuit 3 for decoding operation, and the normal decoder 4a outputs a decode signal _D1 for displaying the normal time.
is output, and the modulation decoder circuit 4b outputs a decode signal _D2 for displaying a time that is modulated to a smaller number than the number normally displayed. The switching circuit 4c receives decoded signals D ₁ and D ₂ from the normal decoding circuit 4a and the modulation decoding circuit 4b, and detects the internal state of the watch, that is, the voltage state of the battery in this embodiment. Detection signal from voltage detection circuit 6 that detects
It is controlled by a control signal CP from an AND gate 7, which will be described later, operated by BD, and selectively outputs the decode signal D ₁ or D ₂ to supply the signal to the driver circuit 4d. Reference numeral 5 denotes a dot matrix display device, which displays the time in accordance with the signal from the display modulation circuit 4. 7 is an AND gate, and the AND gate 7
One input terminal of is connected to the output terminal of the frequency dividing circuit 2, the other input terminal is connected to the output terminal of the voltage detection circuit 6, and the output terminal of the AND gate 7 is connected to the output terminal of the switching circuit 4c. control terminal C
Since the detection signal BD is at "L" level when the voltage detection circuit 6 is not operating, the control signal CP from the AND gate 7 is outputted as a "L" level signal, and the voltage detection circuit 6 is connected to The normal decoder circuit 4 is connected from the switching circuit 4c of the display modulation circuit 4.
It is controlled to output the decoded signal _D1 of a. Also, the voltage detection circuit 6 operates and the detection signal BD
At the time when becomes an "H" level signal, the frequency divided signal (1 Hz) from the frequency dividing circuit 2 is output from the AND gate 7, and the signals from the switching circuit 4c, the normal decoder circuit 4a, and the modulation decoder circuit 4b are output. Control is performed so that decode signals D ₁ and D ₂ are output alternately. Next, the operation in the above configuration will be explained. When the battery voltage is sufficient, the voltage detection circuit 6 is not operating, and the detection signal BD is at the "L" level, the control signal CP output from the AND gate 7 is at the "L" level. Since the switching circuit 4c of the display modulation circuit 4 is controlled to select the decode signal _D1 from the normal decoder circuit 4a, the frequency dividing circuit 2 operates with the oscillation signal from the oscillation circuit 1 as input. , the clock circuit 3 performs a clock operation based on the frequency division signal (1Hz) from the frequency divider circuit 2, and the normal decoder circuit 4a of the display modulation circuit 4 performs a decoding operation based on the clock signal from the clock circuit 3. The time is displayed on the dot matrix display device 5 in a display format as shown in FIG. 2A via the switching circuit _4c and the driver circuit 4d using the decode signal D1 outputted from the decoder circuit 4a. Next, when the battery voltage decreases and the voltage detection circuit 6 operates and the detection signal BD becomes an "H" level signal, the AND gate 7 is opened and the frequency division signal (1Hz) from the frequency division circuit 2 is output. is output as the control signal CP. Therefore, the switching circuit 4 in the display modulation circuit 4
c is controlled so that the decoded signals _D1 and _D2 from the normal decoder circuit 4a and the modulation decoder circuit 4b are switched and outputted alternately, so that the dot matrix display device 5 displays the signals shown in FIG. 2A. The time display is alternately displayed as shown in Figure 2 (b), and the time display is displayed in a format in which all digits are displayed with smaller numbers than the normal time display numbers, to notify that the battery voltage has decreased. Unlike conventional models that display battery life by flashing, the time display changes alternately from small numbers to large numbers, making the time contents much easier to read. At a certain point, the number changes from a small number to a large number, which has an alarm effect as a battery life indicator, which is one of the alarm functions. Next, reference examples of the present invention will be explained. In FIG. 3, 8 is a crystal oscillator circuit, and 9 is a frequency divider circuit which divides the frequency of the oscillation signal from the oscillation circuit 8 as input and outputs a frequency-divided signal of 1 Hz. 10
is a timekeeping circuit, which is composed of switching circuits 11, 13, and 15, a seconds counter 12, a minute counter 14, and an hour counter 16;
1, the input terminal A is connected to the output terminal of the frequency dividing circuit 9, the input terminal B is connected to the switch terminal of the time correction switch _S1 , and the control terminal C is the output terminal of the correction digit selection circuit 17, which will be described later. connected with L ₁ ,
Signal C ₁ from output terminal L ₁ of correction digit selection circuit 17
selectively outputs the signal from the frequency dividing circuit 9 or the signal SP ₁ from the time adjustment switch S ₁ to the output terminal Q.
Output from The second counter 12 receives the signal from the switching circuit 11, performs a timekeeping operation, and generates second clock information.
Output a 60 second signal from K ₁ and output terminal KS. The input terminal A of the switching circuit 13 is connected to the output terminal KS of the second counter 12, the input terminal B is connected to the switch terminal of the time adjustment switch _S1 , and the control terminal C is used for selecting a correction digit, which will be described later. It is connected to the output terminal _L2 of the circuit 17. Then, the signal C 2 from the output terminal L ₂ of the correction digit selection circuit 17 causes the signal C ₂ to be output from the seconds counter 12 .
60 second signal or signal from time adjustment switch S ₁
Selectively output SP ₁ to output terminal Q. The minute counter 14 receives the signal from the switching circuit 13 and performs a time counting operation to obtain minute clock information.
A 60 minute signal is output from K ₂ and output terminal KM.
The input terminal A of the switching circuit 15 is connected to the output terminal KM of the minute counter 14, and the input terminal B
is connected to the switch terminal of the time adjustment switch _S1 , and the control terminal C is connected to the output terminal _L3 of the correction digit selection circuit 17, which will be described later, and receives the signal C3 from the output terminal _L3 of the correction digit selection circuit 17. Accordingly, either the signal from the minute counter 14 or _the signal _SP1 from the time adjustment switch S1 is selectively output to the output terminal Q. The clock time counter 16 receives the signal from the switching circuit 15, performs a time measurement operation, and generates clock time information.
Output K ₃ . _S2 is a correction digit selection switch, and 17 is a level shifter that constitutes a state detection circuit for setting the internal state of the watch, that is, setting the logic level of selection signals _C1 to _C3 , which will be described later, by external operation. The correction digit selection circuit 17 is a correction digit selection circuit.
This is used to select the correction digit when adjusting the time. The level shifter constituting the correction digit selection circuit 17 receives the switch signal SP _{2 by pressing the correction digit selection switch S 2} and inputs the switch signal SP ₂ from each output terminal L ₀ , L ₁ , L ₂ , L ₃ as shown in Table 1. Each selection signal C ₀ , C ₁ , C ₂ ,
Outputs C ₃ .

[Table] Reference numeral 18 denotes a display modulation circuit, which has the same configuration and operation as the display modulation circuit ₄ explained in FIG. Operating normal decoder circuit 18a and modulation decoder circuit 18b
and a switching circuit 18c which receives each decoded signal from the normal decoder circuit 18a and the modulation decoder circuit 18b and is connected to the output terminal _L1 of the correction digit selection circuit 17 and the control terminal C,
It is composed of a driver circuit 18d which receives a signal from the switching circuit 18c and outputs a driver signal _DP1 , and the switching circuit 18c receives a selection signal C output from an output terminal _L1 of the correction digit selection circuit 17. ₁ outputs a decode signal from the normal decoder circuit 18a when the signal is at the "L" level, and
When the correction digit selection signal _C1 is at the "H" level, the modulation decoder circuit 18b is controlled to output a decoded signal. Furthermore, there are display modulation circuits 19 and 20 having the same circuit configuration as the display modulation circuit 18, and the display modulation circuit 19 receives the minute and time information of the minute and time counter 14.
With K ₂ as input, the switching circuit 19c selectively outputs the decoded signal from the normal decoder circuit 19a or the modulation decoder circuit 19b in response to the selection signal C ₂ output from the output terminal L ₂ of the correction digit selection circuit 17. Then, a driver signal DP ₂ is outputted via the driver circuit 19d. The display modulation circuit 20 inputs the clock time information _K3 from the clock time counter 16, and changes the switching circuit 20c to the normal decoder circuit 20a by the selection signal _C3 output from the output terminal _L3 of the correction digit selection circuit 17. Alternatively, the driver circuit 20d selectively outputs the decoded signal from the modulation decoder circuit 20b.
Output the driver signal DP ₃ via. 21 is a dot matrix display device which receives driver signals DP ₁ , DP ₂ , DP ₃ output from the display modulation circuits 18 , 19 , 20 and displays time. Next, the operation in the above configuration will be explained. In the normal time display state, that is, in the non-correction state, the frequency divider circuit 9 receives the oscillation signal from the oscillation circuit 8, performs a frequency dividing operation, and outputs a frequency divided signal. The frequency division signal from the frequency dividing circuit 9 is input to the timekeeping circuit 10, but at this time, the correction digit selection circuit 17 inputs the selection signals C ₁ and C because the correction digit selection switch S ₂ is not operated. ₂ and _C3 are all "L" level signals, therefore, the switching circuits 11, 13, and 15 of the clock circuit 10 are controlled to output the signals input to the input terminal A, respectively, and The frequency division signal from the frequency circuit 9 is sent to the switching circuit 1.
1 to the seconds counter 12 for timekeeping operation.
The 60 second signal is supplied to the minute counter 14 through the switching circuit 13 to perform a timekeeping operation, and the 60 minute signal from the minute counter 14 is supplied to the switching circuit 15.
The clock information K ₁ , K ₂ , K ₃ is outputted from the second counter 12, minute counter 14, and clock counter 16, respectively. At this time, the selection signals C ₁ , C ₂ , and C ₃ outputted from the correction digit selection circuit 17 are all “L” level signals and are in a non-correction state, so that the display modulation circuit 18 , 19, 20 are controlled to output decode signals from the normal decoder circuits 18a, 19a, 20a, respectively.
Driver signal via 8d, 19d, 20d
DP ₁ , DP ₂ , and DP ₃ are output, and the time is displayed on the dot matrix display device 21 as shown in FIG. 4A. Next, when the correction digit selection switch _S2 is pressed once, the level shifter constituting the correction digit selection circuit 17 operates, and an "H" level selection signal _C1 is output from the output terminal _L1 . When the selection signal _C1 becomes an "H" level signal, the switching circuit 11 of the timekeeping circuit 10 supplies the switch signal _SP1 from the time adjustment switch _S1 inputted to the input terminal B to the second time counter 12. At the same time, the switching circuit 18c of the display modulation circuit 18 is also controlled to supply the decoded signal of the modulation decoder circuit 18b inputted to the input terminal B to the driver circuit 18d. As shown in the figure, the number in the second digit of the time displayed on the dot matrix display device 21 is made larger than the normally displayed number to notify that the second can be corrected. In this state, when the time adjustment switch _S1 is operated, the switch signal _SP1 is transmitted to the switching circuit 1.
1 to the seconds counter 12, and the second digit is corrected. Next, from this state, the correction digit selection switch _S2
When is pressed once more, the "H" level selection signal _C2 is outputted from the output terminal _L2 of the correction digit selection circuit 17, and the switching circuit 13 of the timekeeping circuit 10 outputs the selection signal C2 inputted to the input terminal B. A modulation decoder circuit which is brought into a minute digit selection state so that the switch signal SP ₁ of the time adjustment switch S ₁ can be supplied to the minute counter 14, and the switching circuit 19c of the display modulation circuit 19 is also input to the input terminal B. The decode signal 19b is controlled to be supplied to the driver circuit 19d, and the driver signal DP ₂ outputted through the driver circuit 19d causes the dot matrix display device 21 to normally display minute digits as shown in FIG. 4C. The number will be displayed as a larger number than the current number, indicating that the minute can be adjusted. Next, when the correction digit selection switch S ₂ is pressed once more, a selection signal C ₃ of "H" level is output from the output terminal L ₃ of the correction digit selection circuit 17, and the switching circuit 15 of the timekeeping circuit 10 is input. The switch signal SP ₁ of the time correction switch S ₁ inputted to the terminal B is brought into the hour digit selection state so that it can be supplied to the clock hour counter 16, and the switching circuit 20c of the display modulation circuit 20 is also connected to the input terminal B. The decode signal from the modulation decoder circuit 20b, which is input to the modulation decoder circuit 20b, is controlled to be supplied to the driver circuit 20d. The driver signal DP ₃ outputted through the driver circuit 20d causes the dot matrix display device 21 to display the hour digit in a larger number than the normally displayed number, as shown in FIG. Let me know when you're summer. Furthermore, when the correction digit selection switch S ₂ is pressed once, the correction digit selection circuit 17 outputs selection signals C ₁ , C ₂ ,
It returns to the normal non-correction state in which _C3 is not output, and the normal time is displayed as shown in FIG. 4A. Therefore, in the embodiment described above, the number of the digit to be corrected becomes larger, thereby making the digit to be corrected clearer, and the number to be corrected becomes much easier to recognize since it is larger than the normally displayed number. Note that the modulation method of the display modulation circuit in the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. It is also possible to use a modulation method that increases or decreases the numbers in the horizontal direction. Furthermore, in the second embodiment, three display modulation circuits 18, 1 are provided corresponding to the seconds counter 12, minute counter 14, and clock hour counter 16 of the time measurement circuit.
9 and 20, but in other embodiments, for example, each time counter information K ₁ ,
By providing a switching circuit for selecting K ₂ and K ₃ and configuring the output of the switching circuit to be input to a single display modulation circuit in a time-sharing manner, one display modulation circuit can display seconds, minutes, and hour digits. Display modulation is also possible. Further, in the first embodiment, a voltage detection circuit was explained as an example of a state detection circuit for detecting the internal state of a watch, but other embodiments of the state detection circuit include a pulse meter and a thermometer having an external sensor. It is also possible to modulate the numbers or characters displayed on the dot matrix display device by a detection signal from a barometer motor rotation detection circuit, etc., and the internal state of the watch can be set by the external signal mentioned in the second embodiment. As an example of the state detection circuit, a correction digit selection circuit in time adjustment has been described as an example, but other examples include a time setting digit selection circuit in an alarm time setting circuit and a timer time setting circuit. It is also possible to modulate the display of a selected setting digit or correction digit in a timer time setting digit selection circuit, a correction digit selection circuit in a calendar circuit, etc. As described above, in the present invention, the display modulation circuit is operated according to the internal state by the detection signal from the state detection circuit that detects the internal state of the watch, and the size of the numbers or characters displayed on the dot matrix display device is changed. This system is designed to notify the user by modulating the display.Compared to the conventional flashing display method, the warning effect is the same, but there is almost no time for the display to go off, so it is extremely easy to display the content. This has a great practical effect as it can be read easily.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an electronic timepiece according to a first embodiment of the present invention, FIGS. 2A and 2B are plan views showing the display states of the dot matrix display device in FIG. Figure 3 is a circuit block diagram of an electronic watch that is a reference example of the present invention, and Figures
FIG. 3 is a plan view showing display states taken by the dot matrix display device in the figure. 1, 8... oscillation circuit, 2, 9... frequency dividing circuit,
3, 10... timing circuit, 4, 18, 19, 20...
...Display modulation circuit, 4a, 18a, 19a, 20a
...Normal decoder circuit, 4b, 18b, 19
b, 20b...Modulation decoder circuit, 4c, 1
1, 13, 15, 18c, 19c, 20c... switching circuit, 4d, 18d, 19d, 20d... driver circuit, 5, 21... dot matrix display device, 6... voltage detection circuit, D ₁ , D ₂ ...Decode signal, BD...Voltage detection signal, CP...Control signal,
_S1 ...Switch for time correction, _S2 ...Switch for selecting correction digit, 17...Circuit for selecting correction digit, _C1 , _C2 ,
C ₃ ... selection signal, K ₁ , K ₂ , K ₃ ... timing information,
DP ₁ , DP ₂ , DP ₃ ...Driver signals.

Claims (1)

[Claims] 1. An oscillation circuit, a frequency divider circuit that receives the oscillation signal from the oscillation circuit, a clock circuit that receives the frequency division signal from the frequency divider circuit, and displays the time etc. using the clock signal of the clock circuit. In the small display device equipped with a dot matrix display device, a modulation circuit for supplying a modulation signal to the dot matrix display device is disposed between the clock circuit and the dot matrix display device, and the internal state is further monitored. The modulation circuit includes a state detection circuit for detecting a state, and a gate means that receives a signal from the state detection circuit and the frequency dividing circuit or the time measurement circuit, and the modulation circuit receives the signal from the time measurement circuit and determines the normal time. A normal decoder circuit for displaying, a modulation decoder circuit for modulating the display by inputting the signal from the clock circuit, and a modulation decoder circuit for controlling the display by controlling the signal from the gate means. A modulation decoder circuit and a switching circuit for switching display, and are configured to modulate the display of the dot matrix display device in accordance with the signal from the frequency dividing circuit or the clock circuit. A small display device.