JPS6359108A - Bias circuit - Google Patents
Bias circuitInfo
- Publication number
- JPS6359108A JPS6359108A JP61204204A JP20420486A JPS6359108A JP S6359108 A JPS6359108 A JP S6359108A JP 61204204 A JP61204204 A JP 61204204A JP 20420486 A JP20420486 A JP 20420486A JP S6359108 A JPS6359108 A JP S6359108A
- Authority
- JP
- Japan
- Prior art keywords
- bias circuit
- impedance
- resistor
- distributed constant
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 23
- 238000010586 diagram Methods 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
- H03F3/605—Distributed amplifiers
- H03F3/607—Distributed amplifiers using FET's
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は通信、レーダ等に用いられる超広帯域増幅器
、とくに分布型増幅器に用いられるバイアス回路に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to ultra-wideband amplifiers used in communications, radar, etc., and particularly to bias circuits used in distributed amplifiers.
第4図はIEEE Transaction on M
ierow’ave The。Figure 4 shows IEEE Transaction on M
yellow'ave The.
−ry and Techniques、 Vol、
MTT−32,No、 12. December19
84、 p1705に示された従来のバイアス回路を用
いた分布型増幅器の構成図である。上記文献中では6個
の単位FETを用いた場合;こつぃて示しているが、こ
こでは説明を簡単にするために3個の単位FETの場合
について示している。-ry and Techniques, Vol.
MTT-32, No, 12. December19
84, p1705 is a configuration diagram of a distributed amplifier using a conventional bias circuit. In the above-mentioned document, a case is shown in which six unit FETs are used; however, in order to simplify the explanation, a case in which three unit FETs are used is shown here.
この図において(1)は単位FET、(2+はこの単位
F E T (]、)のゲート間を接続する伝送線路、
(3)は同じく単位F E T (11のドレイン間を
接続する伝送線路、(4)は終端抵抗、(5)は単位F
E T (1)のゲートに直流バイアスを印加するた
めのゲートバイアス抵抗、(6)は直流阻止コンデンサ
、(7)は所望のインピーダンスを得るためのコンデン
サ、(8)は分布定数線路、(9)はコンデンサ、00
)はこの分布定数線路(8)とコンデンサ(9)からな
るバイアス回路、 (11)は入力端子、 (12)は
出力端子、 (13)はゲートバイアス端子、 (14
)はドレインパノアス端子である。In this figure, (1) is a unit FET, (2+ is a transmission line connecting the gates of this unit FET (],),
(3) is the same unit F
E T (1) A gate bias resistor for applying a DC bias to the gate, (6) a DC blocking capacitor, (7) a capacitor for obtaining a desired impedance, (8) a distributed constant line, (9) ) is a capacitor, 00
) is a bias circuit consisting of this distributed constant line (8) and a capacitor (9), (11) is an input terminal, (12) is an output terminal, (13) is a gate bias terminal, (14)
) is the drain panoass terminal.
直流阻止コンデンサ(6)の容量はマイクロ波帯で十分
小さなリアクタンスになるように選ばれており、ゲート
バイアス抵抗(5)は増幅器特性への影響が小さくなる
ように高抵抗に選ばれている。また。The capacitance of the DC blocking capacitor (6) is selected so as to have a sufficiently small reactance in the microwave band, and the gate bias resistor (5) is selected to have a high resistance so as to have a small influence on the amplifier characteristics. Also.
終端抵抗(4)は広帯域にわたって入力、:、、IA1
子(11)および出力端子(12)のVSWRの改善を
図るために用いられており、はぼ50Ωに選ばれている
。The terminating resistor (4) inputs over a wide band: , IA1
It is used to improve the VSWR of the terminal (11) and the output terminal (12), and is selected to be approximately 50Ω.
以上のように構成された分布型増幅器において。In the distributed amplifier configured as above.
ゲートバイアス端子(13)とドレインバイアス端子(
14)とからそれぞれ直流バイアスを印加することによ
り、各単位F E T (11が動作状態となる。この
ような状態において、入力端子(11)からマイクロ波
が入射した場合、マイクロ波は各単位F E T (1
)にほぼ等しく分配される。分配されたマイクロ波は各
単位F E T (11で増幅され、出力端子(12)
に到達する。Gate bias terminal (13) and drain bias terminal (
By applying a DC bias from 14) to each unit, each unit FET (11) becomes operational.In such a state, when microwaves are incident from the input terminal (11), the microwaves FET (1
) is distributed approximately equally. The distributed microwaves are amplified by each unit FET (11) and sent to the output terminal (12).
reach.
−fflにこの種の増幅器は1オクタ一ブ以上の広帯域
増幅器に適した構造である。これに用いるバイアス回路
α0)は広帯域にわたって増幅器特性に影響を与えない
ように高インピーダンス特性を有するものが必要となる
。-ffl This type of amplifier has a structure suitable for a wideband amplifier of one octave or more. The bias circuit α0) used for this needs to have high impedance characteristics so as not to affect the amplifier characteristics over a wide band.
この図に示すバイアス回路001において分布定数線路
(8)の特性インピーダンスをZ、長さを1とし。In the bias circuit 001 shown in this figure, the characteristic impedance of the distributed constant line (8) is Z and the length is 1.
コンデンサ(9)の容量を十分大きく選べば、第4図の
A点からバイアス回路αω側を見たインピーダンスZ^
は第(1)式で与えられる。If the capacitance of the capacitor (9) is selected to be sufficiently large, the impedance Z^ when looking at the bias circuit αω side from point A in Figure 4
is given by equation (1).
Z = Z tan−”−’−’−(11八
λ
ここでλは波長である。Z = Z tan-”-'-'-(118
λ where λ is the wavelength.
分布定数線路(8)の長さIをある周波数fに対して一
波長に選んだ場合t lAはOO(Ω)となる。しかし
、2fに対してはzAは0(Ω)となってしまう。When the length I of the distributed constant line (8) is selected to be one wavelength for a certain frequency f, tlA becomes OO(Ω). However, for 2f, zA becomes 0 (Ω).
従来の広帯域型増幅器、とくに分布型増幅器に用いられ
るバイアス回路α0)は以上のように構成されているの
で、ある周波数に対しては高インピーダンス特性を有す
るが、2倍の周波数に対しては低インピーダンス特性と
なる。従って、2倍の周波数に対しては第4図のA点で
マイクス波的に短絡されるため、出力端子(12)にお
けるVSWRは非常に劣化してしまうとともに平担な利
得特性が得られない問題点があった。The bias circuit α0) used in conventional broadband amplifiers, especially distributed amplifiers, is configured as described above, so it has a high impedance characteristic at a certain frequency, but a low impedance characteristic at twice the frequency. It becomes an impedance characteristic. Therefore, for twice the frequency, the microphone wave is short-circuited at point A in Fig. 4, so the VSWR at the output terminal (12) deteriorates significantly and a flat gain characteristic cannot be obtained. There was a problem.
この発明は上記のような問題点を解消するためになされ
たもので、広帯域増幅器の増幅特性に影響を与丸る乙と
なく、各単位F E T (11に所望の直流バイアス
を印加するためのバイアス回路を得ることを目的とする
。This invention was made in order to solve the above-mentioned problems, and it is possible to apply a desired DC bias to each unit FET (11) without affecting the amplification characteristics of the wideband amplifier. The purpose is to obtain a bias circuit for
この発明に係わるバイアス回路は高特性インピーダンス
を有する複数個の分布定数線路と複数個のコンデンサと
で低域通過フィルタを形成し、かつ、上記コンデンサの
少なくとも1個に直列に抵抗を接続しtこ構成にしたも
のである。The bias circuit according to the present invention includes a low-pass filter formed by a plurality of distributed constant lines having high characteristic impedance and a plurality of capacitors, and a resistor connected in series with at least one of the capacitors. It is structured as follows.
この発明におけるバイアス回路は広帯域にわtこって高
インピーダンス特性を得ることにより、バイアス回路の
増幅器特性への影響を小さくする。The bias circuit according to the present invention has high impedance characteristics over a wide band, thereby reducing the influence of the bias circuit on amplifier characteristics.
以下、この発明の一実施例を図について説明する。第1
図はこの発明の一実施例を用いた分布型増幅器の構成図
であり、この図において(10)はこの発明要点をなす
バイアス回路でこのバイアス回路aO+は分布定数線路
+81. (17)とコンデンサ(91,(16)とで
低域通過フィルタを形成し、しかもコンデンサ(16)
には直列に抵抗(15)が直列に接続された構成である
。なおこのバイアス回路以外の構成は第4図に示す従来
の回路と同様なものである。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a distributed amplifier using an embodiment of the present invention. In this figure, (10) is a bias circuit which is the essential point of this invention, and this bias circuit aO+ is a distributed constant line +81. (17) and the capacitor (91, (16)) form a low-pass filter, and the capacitor (16)
A resistor (15) is connected in series with the resistor (15). Note that the configuration other than this bias circuit is similar to the conventional circuit shown in FIG.
上記コンデンサ(16)の容量は周波数fに対して比較
的大きなりアクタンスを示し、2fに対しては小さなリ
アクタンスを示すように適当な値に選ばれている。また
、コンデンサ(9)はfに対して十分小さなリアクタン
スを示すような容量に選ばれている。The capacitance of the capacitor (16) is selected to be an appropriate value so that it exhibits a relatively large actance with respect to the frequency f and a small reactance with respect to 2f. Further, the capacitor (9) is selected to have a capacitance that exhibits a sufficiently small reactance with respect to f.
分布定数線路(81,(17)の長さをfに対して4波
長に選び、特性インピーダンスをZに選んだ場合。When the length of the distributed constant line (81, (17) is selected to be 4 wavelengths for f, and the characteristic impedance is selected to be Z.
図のA点からバイアス回路頭側を見たインピーダンス2
^はfに対してほぼoO(Ω)となる。また、2fに対
してはZA= Z2/ I’t (Ω)となる。たf!
シ、Rは抵抗(15)の抵抗値である。Impedance 2 when looking at the head side of the bias circuit from point A in the diagram
^ becomes approximately oO (Ω) with respect to f. Further, for 2f, ZA=Z2/I't (Ω). Ta f!
C and R are the resistance values of the resistor (15).
ここで分布定数線路(17)の特性インピーダンスを高
く選ぶことにより、2fに対してもZAは大きな値とな
る。By selecting a high characteristic impedance of the distributed constant line (17), ZA becomes a large value even for 2f.
従って、f〜2fにわたってA点からバイアス回路頭側
を見たインピーダンスZdj高インピーダンス特性とな
る。Therefore, the impedance Zdj seen from point A toward the head of the bias circuit has a high impedance characteristic over f to 2f.
このバイアス回路α0)はマイクロ波集積回路技術を用
いることにより、容易に実現できる回路構成である。ま
た、モノリシック集積回路技術を用いればバイアス回路
aolを含む分布型増幅器全体を1個の半導体基板上に
実現することが可能である。This bias circuit α0) has a circuit configuration that can be easily realized by using microwave integrated circuit technology. Further, by using monolithic integrated circuit technology, it is possible to realize the entire distributed amplifier including the bias circuit aol on one semiconductor substrate.
なお、上記実施例では分布定数を2路(8)と(16)
の特性インピーダンスおよび長さが同一の場合について
示したが、異なっていても良い。また、第2図に示すよ
うにバイアス回路−の構成素子数を増やしたものであっ
ても良い。さらに、第3図に示すようにこのバイアス回
路α切は各単位F E T [1)のソースに抵抗(1
5)とコンデンサ(16)とを装荷して単一電源で動作
する分布型増幅器に使用しても良い。In addition, in the above example, the distribution constant is divided into two paths (8) and (16).
Although the case where the characteristic impedance and length of are the same is shown, they may be different. Further, as shown in FIG. 2, the number of constituent elements of the bias circuit may be increased. Furthermore, as shown in FIG.
5) and a capacitor (16) may be used in a distributed amplifier that operates from a single power supply.
以上は分布型増幅器にバイアス回路001を用いた場合
について説明したが帰還型増幅器等、広帯域増幅器であ
れば全てに適用できるものである。Although the case where the bias circuit 001 is used in a distributed amplifier has been described above, it can be applied to any wideband amplifier such as a feedback amplifier.
以上のように、この発明のバイアス回路は高特性インピ
ーダンスを有する複数個の分布定数線路と複数個のコン
デンサとで低域通過フィルタを形成し、かつ、コンデン
サの少なくとも1個に直列に抵抗を接続した構成となっ
ているtこめ、広帯域にわたって高インピーダンス特性
が得られろ。従って、このようなバイアス回路を分布型
増幅器に用いた場合、広帯域にわたってバイアス回路の
増幅器特性への影響が小さくなるため、低vswrt。As described above, the bias circuit of the present invention forms a low-pass filter with a plurality of distributed constant lines having high characteristic impedance and a plurality of capacitors, and a resistor is connected in series with at least one of the capacitors. Because of this configuration, high impedance characteristics can be obtained over a wide band. Therefore, when such a bias circuit is used in a distributed amplifier, the influence of the bias circuit on the amplifier characteristics over a wide band is reduced, resulting in a low vswrt.
平担な利得特性等を有する広帯域増幅器を実現できる。A wideband amplifier having flat gain characteristics etc. can be realized.
第1図はこの発明の一実施例によるバイアス回路を用い
た分布型増幅器の構成図、第2図はこの発明の他の実施
例のバイアス回路の構成図、第3図はこのバイアス回路
を単一電源で動作する分布型増幅器に適用した場合の構
成図、第4図は従来のバイアス回路を用いた分布型増幅
器の構成図である。
これらの図において+11は単位F E T 、 (2
+、 (31は伝送線路、(4)は終端抵抗、(5)は
ゲーI・バイアス抵抗、(6)は直流阻止コンデンサ、
(71,(91,(16)はコンデンサ、 +81.
(17)は分布定数線路、aO)はバイアス回路、
(11)は入力端子、 (12)は出力端子、 (13
)ハ’y’ I・/<イアス端子、 (14)はドレ
インバイアス端子、 (15)は抵抗である。
なお2図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a block diagram of a distributed amplifier using a bias circuit according to one embodiment of the present invention, FIG. 2 is a block diagram of a bias circuit according to another embodiment of the present invention, and FIG. 3 is a simplified diagram of this bias circuit. FIG. 4 is a block diagram of a distributed amplifier using a conventional bias circuit. In these figures, +11 is the unit F ET , (2
+, (31 is a transmission line, (4) is a terminating resistor, (5) is a gate I/bias resistor, (6) is a DC blocking capacitor,
(71, (91, (16) are capacitors, +81.
(17) is a distributed constant line, aO) is a bias circuit,
(11) is the input terminal, (12) is the output terminal, (13
) H'y'I/<Ias terminal, (14) is a drain bias terminal, and (15) is a resistor. Note that in the two figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
個の高特性インピーダンスを有する分布定数線路と複数
個のコンデンサとで低域通過フィルタを形成し、かつ、
上記コンデンサのうち少なくとも1個のコンデンサに直
列に抵抗を接続したことを特徴とするバイアス回路。In a bias circuit used in a wideband amplifier, a low-pass filter is formed by a plurality of distributed constant lines having high characteristic impedance and a plurality of capacitors, and
A bias circuit characterized in that a resistor is connected in series to at least one of the capacitors.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61204204A JPS6359108A (en) | 1986-08-28 | 1986-08-28 | Bias circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61204204A JPS6359108A (en) | 1986-08-28 | 1986-08-28 | Bias circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6359108A true JPS6359108A (en) | 1988-03-15 |
JPH0577211B2 JPH0577211B2 (en) | 1993-10-26 |
Family
ID=16486556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61204204A Granted JPS6359108A (en) | 1986-08-28 | 1986-08-28 | Bias circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6359108A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02104115A (en) * | 1988-10-13 | 1990-04-17 | Mitsubishi Electric Corp | Bias circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60233912A (en) * | 1984-04-16 | 1985-11-20 | レイセオン カンパニ− | Distributed amplifier |
-
1986
- 1986-08-28 JP JP61204204A patent/JPS6359108A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60233912A (en) * | 1984-04-16 | 1985-11-20 | レイセオン カンパニ− | Distributed amplifier |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02104115A (en) * | 1988-10-13 | 1990-04-17 | Mitsubishi Electric Corp | Bias circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH0577211B2 (en) | 1993-10-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |