JPS6355103B2 - - Google Patents
Info
- Publication number
- JPS6355103B2 JPS6355103B2 JP55025245A JP2524580A JPS6355103B2 JP S6355103 B2 JPS6355103 B2 JP S6355103B2 JP 55025245 A JP55025245 A JP 55025245A JP 2524580 A JP2524580 A JP 2524580A JP S6355103 B2 JPS6355103 B2 JP S6355103B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- address
- digital
- color
- discrimination
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 239000003086 colorant Substances 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 5
- 230000006870 function Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 7
- 241000238370 Sepia Species 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/46—Colour picture communication systems
Description
【発明の詳細な説明】
本発明は回路構成、論理の変更が簡単であるに
もかかわらず複雑な論理で判別が出来る２色画像
信号判別回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a two-color image signal discriminating circuit that can perform discrimination using complex logic even though the circuit configuration and logic can be easily changed.
従来の回路を第１図及び第２図に示す。光電変
換系からの特定の色成分のアナログ画像信号Ｘと
その補色成分の信号Ｙは、それぞれしきい値x1，
y1を持つ２値化回路１ａ，１ｂに入力される。そ
の出力信号は判別論理回路２で論理演算された２
色デイジタル信号D1，D2を得る。 Conventional circuits are shown in FIGS. 1 and 2. The analog image signal X of a specific color component and the signal Y of its complementary color component from the photoelectric conversion system are each given a threshold value x 1 ,
It is input to the binarization circuits 1a and 1b having y1 . The output signal is subjected to a logical operation in the discriminator logic circuit 2.
Obtain color digital signals D 1 and D 2 .
又第２図では同じくアナログ画像信号Ｘ，Ｙは
アナログ減算回路３に入力されＸ−Ｙ及びＸの信
号がしきい値x2，y2を持つ２値化回路４ａ，４ｂ
によつて、２色デイジタル信号D1，D2を得る。 Similarly, in FIG. 2, analog image signals X and Y are input to an analog subtraction circuit 3, and the X-Y and X signals are input to binarization circuits 4a and 4b having threshold values x 2 and y 2
Thus, two-color digital signals D 1 and D 2 are obtained.
以上から、アナログ画像信号Ｘ，Ｙのレベルに
対して判別される領域の関係は、第１図の回路に
対しては例えば第３図、第２図の回路に対しては
例えば第４図となる。第３図、第４図で領域Ａは
特定の色と判別され、領域Ｂはそれ以外の色、領
域Ｃは白と判別される。 From the above, the relationship of the areas determined with respect to the levels of the analog image signals X and Y is as shown in, for example, FIG. 3 for the circuit in FIG. Become. In FIGS. 3 and 4, area A is determined to be a specific color, area B is determined to be another color, and area C is determined to be white.
第３図、第４図から明らかなように、従来の回
路では、２色を判別する境界が線形であるという
制限があり、実現できる特性に制約を加えてい
る。したがつて要求される特性によつては、光電
変換系の特性を変更しなければならない。又それ
以外の場合もしきい値を変更する回路が必要とな
るという欠点がある。 As is clear from FIGS. 3 and 4, in the conventional circuit, there is a limitation that the boundary for distinguishing two colors is linear, which places restrictions on the characteristics that can be realized. Therefore, depending on the required characteristics, the characteristics of the photoelectric conversion system must be changed. Furthermore, in other cases, there is a drawback that a circuit for changing the threshold value is required.
本発明の目的は従来の技術の上記欠点を改善し
て簡単かつ自由に判別領域の境界を設定し又変更
出来る２色画像信号判別回路を提供することにあ
り、その特徴は、特定の色成分とその補色成分の
アナログ画像信号をデイジタル信号に変換するア
ナログデイジタル変換回路と、特定の色とそれ以
外の色の有無を示すデイジタル画像信号を記憶す
るメモリー回路と、前記変換回路の出力と必要に
よりもうけられる制御信号に従つて前記メモリー
回路のアドレスを与えるアドレス回路とを有し、
前記アドレスに対して判別領域の境界が所望の非
線形関数となるように前記メモリー回路の内容が
予め設定されるごとき２色画像信号判別回路にあ
る。以下図面により実施例を説明する。 An object of the present invention is to provide a two-color image signal discriminating circuit that can easily and freely set and change the boundaries of a discrimination area by improving the above-mentioned drawbacks of the conventional technology. and an analog-to-digital conversion circuit that converts an analog image signal of its complementary color component into a digital signal, a memory circuit that stores a digital image signal indicating the presence or absence of a specific color and other colors, and an output of the conversion circuit and, depending on necessity, an address circuit that provides an address of the memory circuit in accordance with a generated control signal;
The two-color image signal discriminating circuit is such that the contents of the memory circuit are set in advance so that the boundary of the discriminating area becomes a desired nonlinear function with respect to the address. Examples will be described below with reference to the drawings.
第５図は本発明の第１の実施例であつて、５
ａ，５ｂはアナログデイジタル変換回路、６はそ
のデイジタル信号を次段のメモリー回路のアドレ
スへ入力する回路、７はメモリー回路である。 FIG. 5 shows a first embodiment of the present invention.
Reference numerals a and 5b are analog-to-digital conversion circuits, 6 is a circuit for inputting the digital signal to the address of the next stage memory circuit, and 7 is a memory circuit.
まず特定の色成分のアナログ画像信号Ｘとその
補色成分の信号Ｙは、アナログデイジタル変換回
路でデイジタルの画像信号となる。 First, an analog image signal X of a specific color component and a signal Y of its complementary color component are converted into digital image signals by an analog-to-digital conversion circuit.
次にデイジタル信号はアドレス入力回路６を経
てメモリー回路７のアドレス入力となり、各アド
レスの値に応じて２色デイジタル信号D1，D2が
得られる。なおメモリー回路６には、信号レベル
（アドレス）に対応して出力したい２色デイジタ
ル信号D1，D2の値が、あらかじめ格納されてい
る。 Next, the digital signal passes through the address input circuit 6 and becomes the address input of the memory circuit 7, and two-color digital signals D 1 and D 2 are obtained according to the value of each address. Note that the memory circuit 6 stores in advance the values of the two-color digital signals D 1 and D 2 that are desired to be output in accordance with the signal levels (addresses).
アドレス入力回路６の構成、動作およびメモリ
ー回路７との関係、同じくメモリー回路７のデー
タ格納について更に詳細に説明する。 The structure and operation of the address input circuit 6, its relationship with the memory circuit 7, and data storage in the memory circuit 7 will be explained in more detail.
アドレス入力回路６はメモリー回路７のアドレ
スを入力するための回路であり、特定の色成分の
アナログ画像信号Ｘとその補色成分の信号Ｙのそ
れぞれのレベルを、必要とする任意のビツト数
（例えば４ビツト）にアナログデイジタル変換し
たデイジタル信号（それぞれXD，YDと呼ぶ）を
メモリー回路７のアドレスに極性、順序等を適切
に対応づけて入力するためのデイジタル回路であ
る。例えばアドレス入力回路６からは上位４ビツ
トとしてのXDと下位４ビツトとしてのYDとから
構成される８ビツトのアドレス情報が出力され
る。 The address input circuit 6 is a circuit for inputting the address of the memory circuit 7, and inputs the levels of the analog image signal X of a specific color component and the signal Y of its complementary color component to any required number of bits (for example, This is a digital circuit for inputting digital signals (referred to as X D and Y D , respectively) obtained by analog-to-digital conversion (4 bits) by appropriately correlating the polarity, order, etc. with the address of the memory circuit 7. For example, the address input circuit 6 outputs 8-bit address information consisting of X D as the upper 4 bits and Y D as the lower 4 bits.
また、メモリー回路７に格納される各データ
は、それぞれ２ビツトで構成され、この２ビツト
のそれぞれのビツトが２色デイジタル信号Ｄ１，
Ｄ２に対応する。１例として第６図、第７図では
メモリー回路７のアドレスはＸ，Ｙのレベルを示
すデイジタル信号XD，YDの各ビツトを前述の如
くXD，YDの順に並べたものであり、その各アド
レスに対して第６図、第７図のＡの領域（特定の
色に対応）ではメモリー回路７のデータはＤ１が
デイジタル信号で“１”となるようにＤ２が
“０”となるように、Ｂの領域（それ以外の色に
対応）ではＤ１が“０”、Ｄ２が“１”、Ｃの領域
（白に対応）ではＤ１，Ｄ２とも“０”となるよ
うにあらかじめ格納されている。すなわちＤ１の
“１”が特定の色を示しＤ２の“１”がそれ以外
の色を示すことになる。 Each piece of data stored in the memory circuit 7 is composed of 2 bits, and each of these 2 bits corresponds to the two-color digital signal D1,
Corresponds to D2. As an example, in FIGS. 6 and 7, the address of the memory circuit 7 is the bits of the digital signals X D and Y D indicating the levels of X and Y arranged in the order of X D and Y D as described above. , for each address, in the area A in FIGS. 6 and 7 (corresponding to a specific color), the data in the memory circuit 7 is such that D1 becomes "1" as a digital signal and D2 becomes "0". So, in the area B (corresponding to other colors), D1 is stored as “0” and D2 is “1”, and in the area C (corresponding to white), both D1 and D2 are stored as “0”. has been done. That is, "1" in D1 indicates a specific color, and "1" in D2 indicates other colors.
なお入力アナログ画像信号Ｘ，Ｙは画像の１画
素毎時間的にシリアル入力され、出力にはその画
素に対応するＤ１，Ｄ２が各回路での遅延を経
て、シリアルに出力される。 The input analog image signals X and Y are inputted serially for each pixel of the image, and D1 and D2 corresponding to that pixel are outputted serially after being delayed in each circuit.
このようにアナログ画像信号Ｘ，Ｙをそれぞれ
AD変換したデイジタル信号XD，YDを用いてメモ
リー回路７のアドレス情報を構成し、このアドレ
ス情報でアドレス指定されるメモリー回路７の各
データとして、例えば第６図あるいは第７図の如
く判別領域Ａ，ＢあるいはＣのいずれかに対応し
た２色デイジタル信号D1，D2を格納するように
しているため、判別領域Ａ，Ｂ，Ｃの境界は従来
例で示した様な直線に限らず、第６図、第７図の
如く曲線でも構成でき、第７図のように特異点８
さえも挿入できることとなる。 In this way, the analog image signals X and Y are
Address information of the memory circuit 7 is constructed using the AD-converted digital signals X D and Y D , and each data of the memory circuit 7 addressed by this address information is discriminated as shown in FIG. 6 or FIG. 7, for example. Since two-color digital signals D 1 and D 2 corresponding to either areas A, B, or C are stored, the boundaries between discrimination areas A, B, and C are limited to straight lines as shown in the conventional example. However, it can also be constructed with a curved line as shown in Figures 6 and 7, and the singular point 8 as shown in Figure 7.
This means that even objects can be inserted.
例えば第８図は赤成分とその補色成分を出力す
る光電変換系によつて得られたサンプルａ，ｂ，
ｃ，ｄ，ｅ，ｆ、に対する画像信号Ｘ，Ｙのレベ
ルのデータである。 For example, Fig. 8 shows samples a, b, and
This is level data of image signals X and Y for pixels c, d, e, and f.
ここでａはオレンジ色、ｂはセピア色、ｃはバ
イオレツト（以上小林記録紙CRインク）ｄは
赤鉛筆の赤色、ｅはボールペンの赤色、ｆは油性
インクフエルトペンの赤色である。 Here, a is orange, b is sepia, c is violet (Kobayashi Recording Paper CR Ink), d is the red of a red pencil, e is the red of a ballpoint pen, and f is the red of an oil-based ink felt pen.
したがつて赤色のみｄ，ｅ，ｆを赤と判別した
い場合は、曲線α（…）を境界とし、赤色及びオ
レンジ色ｄ，ｅ，ｆ，ａを赤と判別する場合は、
曲線β（−・−）を境界とし、さらにセピア色も
含める場合ｄ，ｅ，ｆ，ａ，ｂは曲線γ（…）を
境界としなければならない。 Therefore, if you want to distinguish only red colors d, e, and f as red, use the curve α(...) as the boundary, and if you want to distinguish red and orange colors d, e, f, and a as red,
If the curve β(-·-) is the boundary, and sepia color is also included, the curve γ(...) must be the boundary of d, e, f, a, and b.
これらの曲線α，β，γによる判別特性はメモ
リーへのデータ格納によつて自由に行えるわけ
で、メモリー領域を２倍以上にとつて制御信号を
アドレスに入力すれば瞬時に判別特性を切換える
こともできる。すなわち、判別回路の特性を要求
に応じて自由に設定できかつ変更も簡単で瞬時に
できるという利点がある。 The discrimination characteristics based on these curves α, β, and γ can be freely changed by storing data in the memory, and if the memory area is doubled or more and a control signal is input to the address, the discrimination characteristics can be switched instantly. You can also do it. That is, there is an advantage that the characteristics of the discriminating circuit can be freely set according to requirements, and changes can be made easily and instantaneously.
第９図は第２の実施例である。Ｚは判別特性切
換用のマニユアルスイツチ信号である。ここでＺ
の値を変えるだけで判別の特性を簡単に変更で
き、例えば原稿の濃淡時の切換が要易に出来る。
即ち、第２の実施例では、アナログ画像信号Ｘ，
ＹをAD変換して得られたデイジタル信号XD，YD
の他に、２色画像判別回路の判別特性を切換える
ために必要なビツト数を有するデイジタル信号Ｚ
からなる複数のビツトを有する信号をメモリー回
路７のアドレス情報とする。 FIG. 9 shows a second embodiment. Z is a manual switch signal for switching the discrimination characteristic. Here Z
The discrimination characteristics can be easily changed by simply changing the value of , and for example, it is possible to easily change the density of a document.
That is, in the second embodiment, the analog image signals X,
Digital signals X D , Y D obtained by AD converting Y
In addition, a digital signal Z having the necessary number of bits to switch the discrimination characteristics of the two-color image discrimination circuit.
A signal having a plurality of bits consisting of the following is used as the address information of the memory circuit 7.
このように、メモリー回路７のアドレスをデイ
ジタル信号Ｚで拡張すれば、必要とする数だけの
判別特性を実現するためのデータ格納領域が確保
できる。 In this way, by extending the address of the memory circuit 7 with the digital signal Z, data storage areas for realizing the required number of discrimination characteristics can be secured.
又、ＺをＸ，Ｙの多重化制御信号とすれば、２
系列以上の光電変換系に対して、系列毎に独立な
特性を有する判別回路が実現できるという利点が
ある。 Also, if Z is the multiplex control signal for X and Y, then 2
For photoelectric conversion systems of more than one series, there is an advantage that a discrimination circuit having independent characteristics for each series can be realized.
第１０図は第３の実施例である。５ｃはアナロ
グデイジタル変換回路、９はピーク値検出回路で
ある。２の例では画像信号のピークによつて判別
回路の特性を瞬時に変えることができるので、自
動スライサーとして機能するという利点がある。 FIG. 10 shows a third embodiment. 5c is an analog-to-digital conversion circuit, and 9 is a peak value detection circuit. In example 2, since the characteristics of the discrimination circuit can be instantaneously changed depending on the peak of the image signal, it has the advantage of functioning as an automatic slicer.
第１図と第２図は従来の２色判別回路の構成
図、第３図と第４図はその動作説明図、第５図は
本発明の第１の実施例の構成図、第６図、第７
図、第８図、は第５図の回路の動作説明図、第９
図、は第２の実施例の構成図、第１０図、は第３
の実施例の構成図である。
１ａ，１ｂは２値化回路、２は判別論理回路、
３はアナログ減算回路、４ａ，４ｂは２値化回
路、５ａ，５ｂ，５ｃはアナログデイジタル変換
回路、６はメモリー回路へのアドレス入力回路、
７はメモリー回路、８は判別の特異点、９はピー
ク値検出回路、Ｘ，Ｙは２色アナログ画像信号、
D1，D2は２色デイジタル画像信号、Ａ，Ｂ，Ｃ
はそれぞれの色の判別領域、x1，x2，y1，y2は２
値化回路のしきい値。
1 and 2 are configuration diagrams of a conventional two-color discrimination circuit, FIGS. 3 and 4 are diagrams explaining its operation, FIG. 5 is a configuration diagram of the first embodiment of the present invention, and FIG. 6 , 7th
Figures 8 and 9 are explanatory diagrams of the operation of the circuit in Figure 5, and Figure 9.
, is a configuration diagram of the second embodiment, and FIG. 10 is a configuration diagram of the third embodiment.
It is a block diagram of an Example. 1a and 1b are binarization circuits, 2 is a discrimination logic circuit,
3 is an analog subtraction circuit, 4a, 4b are binarization circuits, 5a, 5b, 5c are analog-to-digital conversion circuits, 6 is an address input circuit to the memory circuit,
7 is a memory circuit, 8 is a singular point for discrimination, 9 is a peak value detection circuit, X and Y are two-color analog image signals,
D 1 and D 2 are two-color digital image signals, A, B, and C.
is the discrimination area of each color, x 1 , x 2 , y 1 , y 2 is 2
Threshold value of valorization circuit.
Claims (1)
信号をデイジタル信号に変換するアナログデイジ
タル変換回路と、特定の色とそれ以外の色の有無
を示すデイジタル画像信号を記憶するメモリー回
路と、前記変換回路の出力と必要によりもうけら
れる制御信号に従つて前記メモリー回路のアドレ
スを与えるアドレス回路とを有し、前記アドレス
に対して判別領域の境界が所望の非線形関数とな
るように前記メモリー回路の内容が予め設定され
ることを特徴とする２色画像信号判別回路。 ２ 前記制御信号が特性切換制御信号である特許
請求の範囲第１項の２色画像信号判別回路。 ３ 前記制御信号が画像信号のピーク値に対応す
るデイジタル信号である特許請求の範囲第１項の
２色画像信号判別回路。 ４ 前記特定の色成分が赤色成分であることを特
徴とする特許請求の範囲第１項記載の２色画像信
号判別回路。[Scope of Claims] 1. An analog-to-digital conversion circuit that converts analog image signals of a specific color component and its complementary color component into digital signals, and a memory that stores digital image signals indicating the presence or absence of the specific color and other colors. circuit, and an address circuit for giving an address of the memory circuit according to the output of the conversion circuit and a control signal generated as necessary, the boundary of the discrimination area being a desired nonlinear function with respect to the address. A two-color image signal discriminating circuit, wherein the contents of the memory circuit are set in advance. 2. The two-color image signal discrimination circuit according to claim 1, wherein the control signal is a characteristic switching control signal. 3. The two-color image signal discrimination circuit according to claim 1, wherein the control signal is a digital signal corresponding to a peak value of the image signal. 4. The two-color image signal discrimination circuit according to claim 1, wherein the specific color component is a red component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2524580A JPS56123073A (en) | 1980-03-03 | 1980-03-03 | Bicolor picture signal deciding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2524580A JPS56123073A (en) | 1980-03-03 | 1980-03-03 | Bicolor picture signal deciding circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56123073A JPS56123073A (en) | 1981-09-26 |
| JPS6355103B2 true JPS6355103B2 (en) | 1988-11-01 |
Family
ID=12160593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2524580A Granted JPS56123073A (en) | 1980-03-03 | 1980-03-03 | Bicolor picture signal deciding circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56123073A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0283404A (en) * | 1988-09-21 | 1990-03-23 | Anritsu Corp | Flatness measuring method |
| JPH02176411A (en) * | 1988-12-27 | 1990-07-09 | Fujitsu Ltd | Surface-waviness checking apparatus and optical quantity correcting method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6073792A (en) * | 1983-09-30 | 1985-04-25 | Hitachi Ltd | Color coding device |
| JPS61251971A (en) * | 1985-04-30 | 1986-11-08 | Fanuc Ltd | Image processor |
| JPS6243781A (en) * | 1985-08-20 | 1987-02-25 | Fanuc Ltd | Image processor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4910674A (en) * | 1972-05-24 | 1974-01-30 | ||
| JPS53106521A (en) * | 1977-02-28 | 1978-09-16 | Nec Corp | Color picture analyzer |
-
1980
- 1980-03-03 JP JP2524580A patent/JPS56123073A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4910674A (en) * | 1972-05-24 | 1974-01-30 | ||
| JPS53106521A (en) * | 1977-02-28 | 1978-09-16 | Nec Corp | Color picture analyzer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0283404A (en) * | 1988-09-21 | 1990-03-23 | Anritsu Corp | Flatness measuring method |
| JPH02176411A (en) * | 1988-12-27 | 1990-07-09 | Fujitsu Ltd | Surface-waviness checking apparatus and optical quantity correcting method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56123073A (en) | 1981-09-26 |
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