JPS6354743A - Method of standard cell layout - Google Patents

Abstract

PURPOSE:To shorten the time required for a standard cell layout by forming transistors as fundamental elements in the constitution of a logic circuit in several kinds of fundamental transistors according to a P channel, an N channel, the type of electrode wirings, size, etc., previously preparing these transistors and using them as the fundamental units of the layout. CONSTITUTION:Various transistors organizing a standard cell are named accord ing to P and N channels for the transistors, contact-holes for source-drain and size, and the names and patterns are prepared previously as fundamental transis tor groups. When manufacturing the standard cell, each section of the layout of the standard cell is named in said manner, the kinds of respective transistors are determined from the arrangement of the names, the transistors of interest are taken out of said fundamental transistor groups, spaces among the transistors are decided in accordance with design criteria and the transistors are disposed. Names such as ones consisting of three characters are given to respective fundamental transistors, both ends of three characters are displayed by symbols representing the shapes of sources-drains, and contact-hole absence A, contact-hole presence B, a power supply C, etc. are named.

Description

[Detailed Description of the Invention] [Summary] A standard cell layout method in which several types of single transistors prepared in advance are used as the basic layout unit.

[Industrial application field]

The present invention relates to a standard cell layout method that can quickly respond to changes in design standards.

[Conventional technology]

Traditionally, LSI layout methods include inverter, AND, OR, selector, and adder.

There is a method in which logic that is used repeatedly, such as latches and flip-flops, is prepared in advance as standard cells. The standard cell used in this method is
Even in logic, different technologies have different cell dimensions and internal pattern shapes, so the layout is re-laid out for each technology.

Therefore, it takes a long time to develop standard cells.

[Problem that the invention seeks to solve]

Conventionally, standard cell layouts have been carried out so that each cell satisfies design standards and optimizes cell dimensions, input/output terminal positions, etc. However, with this conventional method, when there is a major change in design standards due to the adoption of a new wafer process, such as using a thinner minimum wiring width, the design must be redesigned from the transistor pattern, which is time-consuming. It is difficult to take immediate action. The same applies when it becomes necessary to create many standard cells at once.

In the present invention, transistors, which are the basic elements of the configuration of a logic circuit, are prepared in advance into several types of basic transistors according to p-channel, n-channel, type and size of electrode wiring, etc., and are used as the basic unit of layout. According to
This is an attempt to shorten the time required for standard cell layout.

[Means for solving problems]

In the present invention, basic transistors are used in groups according to the design criteria of the technology of the standard cell to be created, and each basic transistor is given a name consisting of three letters.

As shown in FIG. 1 (Fa), both ends of the three letters are symbols representing the shape of the ends (source, drain) of the MOS transistor, and are either A without contact hole, B with contact hole, or Bc with contact hole. The letter in the center is a symbol representing the type of transistor (MOS); P-channel transistor P with standard channel width and channel length, N-channel transistor N, P-channel transistor G or S for forming a latch, and N-channel transistor H or T1. There are seven types: and others (created as necessary). Various types of basic transistors are shown in FIGS. 2 and 3.

Figure 2 (al~(kl is a P-channel transistor,
Figures (a) to Fkl are N-channel transistors, and the cross mark indicates that a contact hole can be provided at this position. As shown in FIG. 2, the letter P in the center indicates that the channel width is standard length, G indicates that the channel width is short, and S indicates that the channel width is similarly short and long. Further, as shown in FIG. 3, the letter N in the center indicates that the channel width is standard length, H indicates that the channel width is short, and T indicates that the channel width is similarly short and long. The fact that the contact mark + in the source/drain region is surrounded by a rectangular frame indicates that this portion is not a source/drain, but the underlying substrate is exposed, and therefore the contact at this location is a contact to the substrate.

By doing this, you can tell what type of transistor it is just by looking at its name. For example, in the case of BPB, the source and drain can be contacted and the P channel M has a standard channel width.
It turns out that it is an OS transistor.

In the present invention, such a group of basic transistors is prepared in advance in the form of, for example, vector data representing the above-mentioned name and its pattern, and the required basic transistors are extracted from the group and a standard cell layout is performed by combining them. First, create data that breaks down the standard cell to be created into basic transistors, and use this data to select, arrange, and wire the basic transistors.

When changing the standard cell layout due to changes in design standards, a method is used in which the already designed standard cell is disassembled into the basic transistors and replaced with newly designed basic transistors. In this way, once the basic transistors have been changed due to a change in the design standard, all that is left to do is to use them in the layout (required time can be significantly shortened. An example will be explained below. .

〔Example〕

Figure 4 is a symbol diagram of a half adder, and Figure 5 is a symbol diagram of a half adder.
The figure is a circuit diagram of 0MO5.

This half-adder Nant gate G+ includes P-channel transistors Ql, G2 and N-channel transistors Q3. G
4, or gate G2 and Nantes gate G3 are P
It is composed of channel transistors Q5 to Q7 and an N-channel transistor Q a = G40. Furthermore, the inverter Ga, G5 is a P-channel transistor Ql 1 ,
Ql 3 and N-channel transistor Q12. Consists of Q14.

FIG. 6 is a schematic plan view of this half adder constructed on a semiconductor substrate. In this figure, the contact holes are indicated by stamps. If each area is named by an operator according to the above rules or automatically by pattern recognition, it will look like this (if the symbols on the P channel side are arranged from the left end: CPB / CPB / PC / PB / PA / P
C/PR, and if you arrange the symbols on the N channel side from the left end, it becomes CNB/BNA/NG/ NB/ NB/
NB/CNB. The lines are divided based on the symbols P and N in the center (and as shown above, there are places where there are only two symbols, but this is a part where the source and drain are shared with the adjacent transistor. and becomes as follows.

CPB/CPB /BPC/CPB /BPA /AP
C/CPB and CNB/BNA /ANC/CNB /BNB /BN
B/CNB These constitute Q1 to Ql4 as shown, and in turn constitute G1 to G5 (however, some wiring is not connected). By naming the plan view (layout) of a standard cell in this way, it is possible to break it down into basic transistors and identify common parts.

After disassembling the basic transistor, replace it with the basic transistor shown in FIG. 7 (same type as in FIGS. 2 and 3, but of a new design). The spacing between each basic transistor is as follows. That is, the origin of the basic transistor is the center of the gate, and the distance X between the gate centers is the lateral spacing of the basic transistor, as shown in FIG. 1('b). The minimum spacing between basic transistors is λ, source and drain.

C, for example, as shown in Table 1.2 (.

Table 1 (P channel) Table 2 (N channel) The vertical distance Y between the P channel transistor and the N channel transistor is taken as shown in FIG. 1(C). FIG. 8 shows the state after replacement. Although the arrangement is the same as that shown in FIG. 6, it is smaller than that shown in FIG. 6 because it is based on the design standard of small wiring width.

Figure 9 shows a latch circuit, (a) is a symbol diagram, (b)
) is a circuit diagram. Reference numerals II and 12 are inverters constituting a flip-flop, and GI is a gate for data acquisition. QI-G3 is a P-channel MOS transistor, Q4
~Q6 is an N-channel MO3) transistor, G2. G5
11, G3. G6 is I2, and Ql, G4 is G
1.

If a combination of basic transistors is made as described above, the result will be as shown in FIG. 10, and if wired, it will be as shown in FIG. 11.

Transistor Q3 that constitutes impark ■2 for latch
．． Q6 has a small channel width and a long channel length.

〔Effect of the invention〕

As explained above, in the present invention, the patterns of the various transistors constituting the standard cell are P.

They are prepared in advance as a basic transistor group by naming them by N channel, with or without contact holes for source and drain, by connection destination (power supply), and by size, and when manufacturing standard cells, the existing needles are used. If so, name each region to know the type of transistor, select and arrange the corresponding transistors from the above basic transistor group, determine the spacing between each transistor according to design standards, and connect them. Therefore, changes in design standards can be dealt with quickly.

[Brief explanation of drawings]

Fig. 1 is an explanatory diagram of the naming and spacing of basic transistors, Figs. 2 and 3 are explanatory diagrams of the names of basic transistors and their patterns, Figs. 4 and 5 are symbol diagrams and circuit diagrams of a half-adder, Figure 6 is a schematic plan view 1 of the half adder of the existing needle, Figure 7 is an explanatory diagram of the names of basic transistors and their patterns according to the new design standards, and Figure 8 is a schematic diagram showing an example of manufacturing Figure 5 from Figure 7. Plan view, Figure 9 is a symbol diagram and circuit diagram of the latch circuit, Figure 10 is
The figure and FIG. 11 are schematic plan views showing an example of manufacturing the device shown in FIG. 9 using basic transistors. In Figures 1 to 3, + indicates a contact hole, and X indicates a contact hole. Y is the interval and A, B, C... are the names.

Claims (1)

[Claims] Various transistors constituting a standard cell are provided with P, N channel, source/drain contact holes,
Name them according to their size and prepare the names and patterns in advance as a basic transistor group. When manufacturing a standard cell, give the above names to each part of the layout of the standard cell, and use the array of names to create a standard cell. Knowing the type of each transistor, extracting the relevant transistor from the basic transistor group,
A standard cell layout method characterized by arranging transistors by determining the spacing between them according to design standards.