JPS6354260B2 - - Google Patents

Info

Publication number
JPS6354260B2
JPS6354260B2 JP10225581A JP10225581A JPS6354260B2 JP S6354260 B2 JPS6354260 B2 JP S6354260B2 JP 10225581 A JP10225581 A JP 10225581A JP 10225581 A JP10225581 A JP 10225581A JP S6354260 B2 JPS6354260 B2 JP S6354260B2
Authority
JP
Japan
Prior art keywords
input
transmission
receiving circuit
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP10225581A
Other languages
Japanese (ja)
Other versions
JPS585040A (en
Inventor
Kenichi Sasaki
Yukihiro Maruyama
Nobutaka Ishigaki
Hishiichi Komya
Masaaki Sasagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10225581A priority Critical patent/JPS585040A/en
Publication of JPS585040A publication Critical patent/JPS585040A/en
Publication of JPS6354260B2 publication Critical patent/JPS6354260B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00Arrangements affording multiple use of the transmission path
    • H04L5/14Two-way operation using the same type of signal, i.e. duplex
    • H04L5/16Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Description

【発明の詳細な説明】 本発明は時分割双方向伝送の受信回路方式に関
するものである。本発明は電話加入者線における
双方向時分割伝送装置に利用することができる。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving circuit system for time-division bidirectional transmission. INDUSTRIAL APPLICATION This invention can be utilized for the bidirectional time division transmission apparatus in a telephone subscriber line.

従来の時分割双方向伝送の送信受信回路方式を
第1図に示す。第1図において、1は送信信号入
力端子、2は送信クロツク信号入力端子、3は送
信回路、4は整合終端抵抗、5は送信回路出力
部、6はトランス、7は伝送線路、8はスイツ
チ、9は受信回路、10は可変減衰器、11は等
化増幅器、12は自動利得制御部、13は時定数
回路、14は受信等化信号出力端子、15は送信
受信制御信号の如く構成されており、送信時には
送信受信制御信号15の送信指示命令により、送
信信号入力端子1より送信信号は送信回路3より
伝送線路7に送出されるが、送信回路出力部5に
接続されているスイツチ8は開くので送信信号は
受信回路9には入力されない。受信時には送信受
信制御信号15の受信指示命令により送信信号入
力端子1の送信信号は無信号となつており、送信
回路3の出力は零レベルとなり、スイツチ8は閉
じるので伝送線路7よりの受信信号は送信回路出
力部5から受信回路9に入力され等化増幅されて
受信等化信号出力端子14に出力される。
FIG. 1 shows a conventional transmitting/receiving circuit system for time-division bidirectional transmission. In Figure 1, 1 is a transmission signal input terminal, 2 is a transmission clock signal input terminal, 3 is a transmission circuit, 4 is a matching termination resistor, 5 is a transmission circuit output section, 6 is a transformer, 7 is a transmission line, and 8 is a switch. , 9 is a reception circuit, 10 is a variable attenuator, 11 is an equalization amplifier, 12 is an automatic gain control section, 13 is a time constant circuit, 14 is a reception equalization signal output terminal, and 15 is a transmission/reception control signal. At the time of transmission, the transmission signal is sent from the transmission signal input terminal 1 to the transmission line 7 from the transmission circuit 3 according to the transmission instruction command of the transmission/reception control signal 15. is open, so the transmission signal is not input to the receiving circuit 9. At the time of reception, the transmission signal at the transmission signal input terminal 1 is no signal due to the reception instruction command of the transmission and reception control signal 15, the output of the transmission circuit 3 is at zero level, and the switch 8 is closed, so that the reception signal from the transmission line 7 is not transmitted. is inputted from the transmitting circuit output section 5 to the receiving circuit 9, equalized and amplified, and outputted to the received equalized signal output terminal 14.

しかしながら、第1図の回路ではスイツチ8が
受信信号の信号路に入つているために、例えばス
イツチ8をリレーの如くの機械式スイツチで構成
する場合には高速動作が難しく、またアナログ
ICスイツチで構成する場合には導通抵抗の変動
による受信信号のレベル変動や低電源電圧動作で
の信号歪の発生等により受信信号の受信等化特性
を劣化させるような欠点があつた。
However, in the circuit shown in Fig. 1, switch 8 is in the signal path of the received signal, so if switch 8 is configured with a mechanical switch such as a relay, high-speed operation is difficult, and analog
When configured with an IC switch, there are drawbacks such as the reception equalization characteristics of the received signal being degraded due to fluctuations in the level of the received signal due to fluctuations in conduction resistance and signal distortion caused by low power supply voltage operation.

本発明の目的は従来の技術の上記欠点を改善し
て受信回路の受信等化特性を改善することにあ
り、その特徴は、 送信回路の出力端と、受信回路の入力端とが共
通の伝送路に接続され、該送信回路と受信回路と
が送信受信制御信号に従つて時分割的に切換えら
れ、該受信回路が、入力端に接続される可変減衰
器と、その出力に接続され受信等化信号出力端子
に出力信号を提供する等化増幅器と、受信等化信
号出力端子におけるレベルに従つて前記可変減衰
器の減衰量を制御する自動利得制御部とを有する
ごとき、時分割双方向伝送の受信回路方式におい
て、前記等化増幅器の出力と受信等化信号出力端
子との間に、第1入力及び第2入力を有し該入力
が前記送信受信制御信号に従つて切換えられる入
力選択器がもうけられ、前記第1入力は前記等化
増幅器の出力に接続され、前記第2入力は予じめ
定められる電位に接続され、送信受信制御信号の
受信指示期間には第1入力が選択され送信指示期
間には第2入力が選択されるごとき時分割双方向
伝送の受信回路方式にある。以下図面により実施
例を説明する。
An object of the present invention is to improve the reception equalization characteristics of a reception circuit by overcoming the above-mentioned drawbacks of the conventional technology. The transmitting circuit and the receiving circuit are connected to a variable attenuator connected to the input terminal, and the receiving circuit is connected to a variable attenuator connected to the input terminal, and the receiving circuit is connected to the variable attenuator connected to the input terminal, and the receiving circuit is connected to the variable attenuator connected to the input terminal, and the receiving circuit is connected to the variable attenuator connected to the input end, and the receiving circuit is connected to the variable attenuator connected to the input end, and the receiving circuit is connected to a variable attenuator connected to the input end, and the receiving circuit is connected to the variable attenuator and the receiving circuit is connected to the variable attenuator connected to the input end, and the receiving circuit is connected to the variable attenuator and the receiving circuit is connected to the variable attenuator connected to the input end. time-division bidirectional transmission, including an equalizing amplifier that provides an output signal to an equalized signal output terminal; and an automatic gain control section that controls the amount of attenuation of the variable attenuator according to the level at the received equalized signal output terminal. In the receiving circuit system, the input selector has a first input and a second input between the output of the equalizing amplifier and the received equalized signal output terminal, and the input is switched according to the transmitting/receiving control signal. is provided, the first input is connected to the output of the equalization amplifier, the second input is connected to a predetermined potential, and the first input is selected during the reception instruction period of the transmission/reception control signal. During the transmission instruction period, the receiving circuit system employs time-division bidirectional transmission in which the second input is selected. Examples will be described below with reference to the drawings.

第2図は本発明の実施例であつて、21は送信
信号入力端子、22は送信クロツク信号入力端
子、23は送信回路、24は整合終端抵抗、25
は送信回路出力部、26はトランス、27は伝送
線路、28は受信回路、29は可変減衰器、30
は等化増幅器、31は入力選択増幅器、32は第
1正相入力、33は第2正相入力、34は自動利
得制御部、35は時定数回路、36は受信等化信
号出力端子、37は送信受信制御信号である。
FIG. 2 shows an embodiment of the present invention, in which 21 is a transmission signal input terminal, 22 is a transmission clock signal input terminal, 23 is a transmission circuit, 24 is a matching termination resistor, 25
is a transmitting circuit output section, 26 is a transformer, 27 is a transmission line, 28 is a receiving circuit, 29 is a variable attenuator, 30
31 is an equalization amplifier, 31 is an input selection amplifier, 32 is a first positive phase input, 33 is a second positive phase input, 34 is an automatic gain control section, 35 is a time constant circuit, 36 is a received equalization signal output terminal, 37 is a transmission/reception control signal.

時分割双方向伝送では、1組の伝送線路を時分
割で送信及び受信を繰り返して使用する。第2図
の信号の流れを説明すると、送信信号入力端子2
1に入力された送信信号は送信クロツク信号入力
端子22の送信クロツク信号によつて整形され、
低インピーダンス出力の送信回路23から整合終
端抵抗24を経てトランス26に送られ伝送線路
27に送出される。一方伝送線路27より送られ
てくる受信信号は、トランス26を経て送信回路
出力部25で分岐されて受信回路28に入力され
る。受信回路28では伝送線路27による信号の
減衰を補償するため自動利得制御系を構成してお
り、受信信号の振幅を検出して振幅大なる時に
は、自動利得制御部34の内の時定数回路35を
充電させて可変減衰器29の減衰量を大きくして
等化増幅器30に送り込むことによつて受信回路
28の利得を下げ、振幅小なる時には時定数回路
35を放電させて可変減衰器29の減衰量を小さ
くし受信回路28の利得を上げることによつて、
受信等化信号出力端子36の信号レベルを常に一
定にする。
In time-division bidirectional transmission, one set of transmission lines is repeatedly used for transmission and reception in a time-division manner. To explain the signal flow in Figure 2, the transmission signal input terminal 2
The transmission signal inputted to 1 is shaped by the transmission clock signal of the transmission clock signal input terminal 22,
The signal is sent from the low-impedance output transmission circuit 23 to the transformer 26 via the matching termination resistor 24, and then to the transmission line 27. On the other hand, the reception signal sent from the transmission line 27 passes through the transformer 26, is branched at the transmission circuit output section 25, and is input to the reception circuit 28. The receiving circuit 28 includes an automatic gain control system to compensate for signal attenuation caused by the transmission line 27. When the amplitude of the received signal is detected and the amplitude becomes large, the time constant circuit 35 of the automatic gain control section 34 is configured. is charged to increase the attenuation of the variable attenuator 29 and send it to the equalizing amplifier 30 to lower the gain of the receiving circuit 28. When the amplitude is small, the time constant circuit 35 is discharged to increase the attenuation of the variable attenuator 29. By reducing the amount of attenuation and increasing the gain of the receiving circuit 28,
The signal level of the received equalized signal output terminal 36 is always kept constant.

送信時を考えると、前述した如く送信信号は送
信クロツク信号に従つて送信回路23より整合終
端抵抗24、トランス26を経て伝送線路27に
送出される。それと同時に送信回路出力部25よ
り受信回路28にも送信信号が入力される。一般
に受信時には受信信号は伝送線路損失によつて微
少レベル信号となつており、受信回路28は自動
利得制御部34によつて高利得に保持されてい
る。このような状態の時大レベルの送信信号が入
力されると、受信回路28は入力選択増幅器31
が無いと、自動利得制御部34の内の時定数回路
35が一般に充電時定数が小さいために、すばや
く応答し受信回路28の利得を下げてしまう。と
ころが逆に時定数回路35の放電時定数は一般に
大きいため、送信から受信に切替わつた時受信信
号レベルが小さいにもかかわらず、受信回路28
の利得は急には大きくなれず受信信号の正しい等
化が行われないことになる。そこで一種の演算増
幅器でその入力部を多数所有し、各入力を制御信
号によつて選択切替え制御するような、例えば逆
相入力を1個、正相入力を2個持ち、2つの正相
入力の各々の定電流源部を制御して導通または非
導通とすることによつて、2つの正相入力のうち
の1つを選択するような入力選択器である入力選
択増幅器31を導入すると、該入力選択増幅器3
1は送信受信制御信号37によつて制御され、送
信指示命令がくると該入力選択増幅器31の受信
回路制御信号入力である第2正相入力が選択出力
され、例えば受信回路制御信号として相対的な零
レベルを設定すれば該入力選択増幅器31の出力
は零レベルとなり、受信指示命令がくると受信信
号入力である第1正相入力が選択出力される。従
つて送信時には送信回路出力部25より受信回路
28に入力された送信信号は自動利得制御部34
には到達できず、自動利得制御部34の入力は受
信回路28の入力レベルに関係なく常に零レベル
信号となり、受信回路28の利得はほぼ受信時に
設定された値に保持され次の受信に備えることが
できる。
Considering the time of transmission, as described above, the transmission signal is sent from the transmission circuit 23 to the transmission line 27 via the matching termination resistor 24 and the transformer 26 in accordance with the transmission clock signal. At the same time, a transmission signal is also input to the reception circuit 28 from the transmission circuit output section 25. Generally, during reception, the received signal is at a very low level due to transmission line loss, and the receiving circuit 28 is maintained at a high gain by the automatic gain control section 34. When a high-level transmission signal is input in such a state, the receiving circuit 28 selects the input selection amplifier 31.
Without this, the time constant circuit 35 of the automatic gain control section 34 generally has a small charging time constant, so it responds quickly and lowers the gain of the receiving circuit 28. However, on the contrary, since the discharge time constant of the time constant circuit 35 is generally large, when switching from transmission to reception, the reception circuit 28
The gain cannot suddenly increase and the received signal will not be equalized correctly. Therefore, it is a type of operational amplifier that has many input parts and each input is selectively controlled by a control signal, for example, it has one negative phase input, two positive phase inputs, and two positive phase inputs. Introducing the input selection amplifier 31, which is an input selector that selects one of the two positive-phase inputs by controlling each constant current source section to conduct or non-conduct. The input selection amplifier 3
1 is controlled by a transmission/reception control signal 37, and when a transmission instruction command is received, the second positive phase input which is the receiving circuit control signal input of the input selection amplifier 31 is selectively outputted, and for example, a relative signal is output as a receiving circuit control signal. If a zero level is set, the output of the input selection amplifier 31 becomes zero level, and when a reception instruction command is received, the first positive phase input, which is the reception signal input, is selected and output. Therefore, during transmission, the transmission signal input from the transmission circuit output section 25 to the reception circuit 28 is transmitted to the automatic gain control section 34.
cannot be reached, and the input to the automatic gain control section 34 is always a zero level signal regardless of the input level to the receiving circuit 28, and the gain of the receiving circuit 28 is maintained at approximately the value set at the time of reception in preparation for the next reception. be able to.

一方受信時には、送信信号入力端子21に入力
される送信信号は送信受信制御信号37によつて
無信号に制御されているため、送信回路23の出
力は零レベルであり、また送信回路出力は低イン
ピーダンスであるため、伝送線路27よりの受信
信号はトランス26を経て整合終端抵抗24でイ
ンピーダンス整合されて受信され、送信回路出力
部25より受信回路28に入力される。受信時に
は入力選択増幅器31は受信信号入力である第1
正相入力を選択出力するため、受信回路28は自
動利得制御部34を含んだ正常なループを形成し
て受信動作を行い、受信信号を正しく等化して受
信等化信号出力端子36に出力する。
On the other hand, during reception, the transmission signal input to the transmission signal input terminal 21 is controlled to be non-signal by the transmission/reception control signal 37, so the output of the transmission circuit 23 is at zero level, and the output of the transmission circuit is low. Since the impedance is impedance, the received signal from the transmission line 27 passes through the transformer 26, is impedance matched by the matching termination resistor 24, and is received, and is input from the transmitting circuit output section 25 to the receiving circuit 28. During reception, the input selection amplifier 31 selects the first input which is the received signal input.
In order to selectively output the positive phase input, the receiving circuit 28 forms a normal loop including the automatic gain control section 34 to perform the receiving operation, correctly equalizes the received signal, and outputs it to the received equalized signal output terminal 36. .

以上説明したように、実施例では時分割双方向
伝送の送信受信回路において、受信回路に入力選
択増幅器を導入することにより、送信回路出力部
と受信回路入力部を直結した状態で受信回路を構
成しても送信時に受信回路の制御利得の急変を阻
止することができ、また受信信号の信号路にスイ
ツチを含まないので信号劣化を抑えることがで
き、さらにまた入力選択増幅器は受信回路で使用
する等化増幅器等の他の増幅器と同一技術で達成
できるため選択回路を含む受信回路全体をLSI化
できるという利点をもつている。
As explained above, in the embodiment, in the transmitting/receiving circuit for time-division bidirectional transmission, by introducing an input selection amplifier into the receiving circuit, the receiving circuit is configured with the transmitting circuit output section and the receiving circuit input section directly connected. It is possible to prevent sudden changes in the control gain of the receiving circuit during transmission even when the signal is transmitted, and since there is no switch in the signal path of the received signal, signal degradation can be suppressed.Furthermore, the input selection amplifier can be used in the receiving circuit. Since it can be achieved using the same technology as other amplifiers such as equalizing amplifiers, it has the advantage that the entire receiving circuit including the selection circuit can be implemented as an LSI.

本発明は、時分割双方向伝送における受信回路
に入力選択増幅器を導入することによつて、容易
に信号劣化を抑えた時分割双方向伝送の送信受信
回路を構成でき、例えば加入者線の時分割双方向
伝送装置に利用することができる。
By introducing an input selection amplifier into the receiving circuit for time-division bidirectional transmission, the present invention can easily configure a transmitting/receiving circuit for time-division bidirectional transmission that suppresses signal deterioration. It can be used for split bidirectional transmission equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の時分割双方向伝送の送信受信回
路の構成図、第2図は本発明による時分割双方向
伝送の送信受信回路の構成図である。各図におい
て、1は送信信号入力端子、2は送信クロツク信
号入力端子、3は送信回路、4は整合終端抵抗、
5は送信回路出力部、6はトランス、7は伝送線
路、8はスイツチ、9は受信回路、10は可変減
衰器、11は等化増幅器、12は自動利得制御
部、13は時定数回路、14は受信等化信号出力
端子、15は送信受信制御信号、21は送信信号
入力端子、22は送信クロツク信号入力端子、2
3は送信回路、24は整合終端抵抗、25は送信
回路出力部、26はトランス、27は伝送線路、
28は受信回路、29は可変減衰器、30は等化
増幅器、31は入力選択増幅器、32は第1正相
入力、33は第2正相入力、34は自動利得制御
部、35は時定数回路、36は受信等化信号出力
端子、37は送信受信制御信号である。
FIG. 1 is a configuration diagram of a conventional time-division bidirectional transmission transmission/reception circuit, and FIG. 2 is a configuration diagram of a time-division bidirectional transmission transmission/reception circuit according to the present invention. In each figure, 1 is a transmission signal input terminal, 2 is a transmission clock signal input terminal, 3 is a transmission circuit, 4 is a matching termination resistor,
5 is a transmitting circuit output section, 6 is a transformer, 7 is a transmission line, 8 is a switch, 9 is a receiving circuit, 10 is a variable attenuator, 11 is an equalization amplifier, 12 is an automatic gain control section, 13 is a time constant circuit, 14 is a reception equalization signal output terminal, 15 is a transmission/reception control signal, 21 is a transmission signal input terminal, 22 is a transmission clock signal input terminal, 2
3 is a transmission circuit, 24 is a matching termination resistor, 25 is a transmission circuit output section, 26 is a transformer, 27 is a transmission line,
28 is a receiving circuit, 29 is a variable attenuator, 30 is an equalization amplifier, 31 is an input selection amplifier, 32 is a first positive phase input, 33 is a second positive phase input, 34 is an automatic gain control section, and 35 is a time constant. 36 is a reception equalization signal output terminal, and 37 is a transmission/reception control signal.

Claims (1)

【特許請求の範囲】 1 送信回路の出力端と受信回路の入力端とが共
通の伝送路に接続され、該送信回路と受信回路と
が送信受信制御信号に従つて時分割的に切換えら
れ、該受信回路が、入力端に接続される可変減衰
器と、その出力に接続され受信等化信号出力端子
に出力信号を提供する等化増幅器と、受信等化信
号出力端子におけるレベルに従つて前記可変減衰
器の減衰量を制御する自動利得制御部とを有する
ごとき、時分割双方向伝送の受信回路方式におい
て、前記等化増幅器の出力と受信等化信号出力端
子との間に、第1入力及び第2入力を有し該入力
が前記送信受信制御信号に従つて切換えられる入
力選択器がもうけられ、前記第1入力は前記等化
増幅器の出力に接続され、前記第2入力は予じめ
定められる電位に接続され、送信受信制御信号の
受信指示期間には第1入力が選択され送信指示期
間には第2入力が選択されることを特徴とする、
時分割双方向伝送の受信回路方式。 2 前記入力選択器が少なくとも2個の正相入力
をもつ演算増幅器であり、各正相入力が各々第1
入力及び第2入力であることを特徴とする特許請
求の範囲第1項の時分割双方向伝送の受信回路方
式。
[Claims] 1. The output end of the transmitting circuit and the input end of the receiving circuit are connected to a common transmission path, and the transmitting circuit and the receiving circuit are switched in a time-sharing manner according to a transmitting/receiving control signal, The receiving circuit includes a variable attenuator connected to the input terminal, an equalizing amplifier connected to the output thereof and providing an output signal to the received equalized signal output terminal, and a variable attenuator connected to the input terminal, an equalizing amplifier connected to the output thereof and providing an output signal to the received equalized signal output terminal, and the receiving circuit according to the level at the received equalized signal output terminal. In a receiving circuit system for time-division bidirectional transmission, which includes an automatic gain control section that controls the amount of attenuation of a variable attenuator, a first input signal is connected between the output of the equalizing amplifier and the received equalized signal output terminal. and a second input, the input selector being switched in accordance with the transmit/receive control signal, the first input being connected to the output of the equalizing amplifier, and the second input being previously selected. connected to a predetermined potential, the first input is selected during the reception instruction period of the transmission/reception control signal, and the second input is selected during the transmission instruction period;
Receiving circuit system for time-division bidirectional transmission. 2. The input selector is an operational amplifier having at least two positive phase inputs, each positive phase input being
A receiving circuit system for time-division bidirectional transmission according to claim 1, characterized in that the receiving circuit system is an input and a second input.
JP10225581A 1981-07-02 1981-07-02 Receiving circuit system for time-division two-way transmission Granted JPS585040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10225581A JPS585040A (en) 1981-07-02 1981-07-02 Receiving circuit system for time-division two-way transmission

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10225581A JPS585040A (en) 1981-07-02 1981-07-02 Receiving circuit system for time-division two-way transmission

Publications (2)

Publication Number Publication Date
JPS585040A JPS585040A (en) 1983-01-12
JPS6354260B2 true JPS6354260B2 (en) 1988-10-27

Family

ID=14322480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10225581A Granted JPS585040A (en) 1981-07-02 1981-07-02 Receiving circuit system for time-division two-way transmission

Country Status (1)

Country Link
JP (1) JPS585040A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009267943A (en) * 2008-04-28 2009-11-12 Toshiba Corp Transmission device for railway vehicle and transmission system for railway vehicle

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123254A (en) * 1982-01-19 1983-07-22 Nec Corp Time-division two-way transmitter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009267943A (en) * 2008-04-28 2009-11-12 Toshiba Corp Transmission device for railway vehicle and transmission system for railway vehicle

Also Published As

Publication number Publication date
JPS585040A (en) 1983-01-12

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