JPS6353783A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shift storage data in the unit of line or column, and executing the processing for moving, inclining, and rotating, etc. display image at a high speed by constituting a memory array in a dual port constitution to make it accessible either from the X-axis or Y-axis, and providing a shift register for each data line. CONSTITUTION:Memory cells can be accessed from the X-axis through X-axis word lines and Y-axis complementary data lines which is the ordinary accessing, and can be accessed from the Y-axis through Y-axis word lines and X-axis complementary data lines. Also, the complementary data lines in the respective axis directions are connected to the respective bits corresponding to a shift register SRX or SRY, hence a serial writing and serial reading in the unit of line or column can be executed from an external equipment. Further, a complementary common data line is provided respectively for the X-axis and the Y-axis, hence a memory access in the unit of one bit can be executed from either the X-axis or the Y-axis. Accordingly, only by designating the line or column address of the memory and the amount of shifting, the shifting processing of the storage data in the unit of line or column can be executed autonomously. As a result, the processing for moving, inclining, or rotating, etc. a display image can be executed at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to techniques that are effective for use in semiconductor storage devices for image processing.

[Conventional technology]

As a so-called image memory for controlling CRT (cathode ray discharge tube) displays and temporarily storing displayed images,
There is a static type RAM that is accessed in units of one bit or multiple bits. These static type RA
Regarding M, for example, in September 1983, ■ "Hitachi IC Memory Data Book J, pp. 43-248" published by Hitachi, Ltd.
It is written on the page.

[Problem that the invention seeks to solve]

In an image processing system including the image memory as described above, the display screen is often moved in the X-axis or Y-axis direction, tilted, or rotated. When the above-mentioned conventional semiconductor storage device is used as an image memory and the control is performed by a normal microcomputer, etc., the processing of moving, m-tilting, and rotating the displayed image must be performed many times in units of access bits of the memory. In addition to accessing memory, the microcomputer must repeat the troublesome arithmetic processing for shifting.

That is, for example, the display image of (A) in FIG.
If you want to tilt as shown in B), first read out the stored data of one row in the access bit unit of the image memory, and transfer it to the memory in the main device by multiple memory accesses. Next, set the fixed axis a of that row. The shift ff1 (C'' -〇) is calculated according to the distance from -b, and the operation to shift the contents of the memory of the main device by the shift amount is repeated for each operation bit of the main device.Arithmetic processing is performed within the main device. When the process is completed, the contents of the memory must be written to the image memory in units of access bits, and the stored data of the next row must be read out, which must be repeated several times for each row.

Therefore, if the above processing is repeated for all rows of the display image, a huge number of memory accesses will be required, and the processing load on the main device for shift calculations will be extremely heavy.

The inventors of the present application focused on the fact that shift processing of stored data in units of rows is frequently used in the processing of moving, tilting, or rotating these display images, and developed a semiconductor memory device that is effective for processing these display images. did.

An object of the present invention is to provide a semiconductor memory device having new functions.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
The RAM (random access memory) memory array has a dual-port structure that can be accessed from either the X axis (row) or the Y axis (column), and a shift register is provided on each data line, so that -times of memory can be In accessing, it has a function of reading stored data into the shift register in units of rows or columns, shifting it an arbitrary number of times, and then rewriting it.

[For production]

According to the above-mentioned means, it is possible to shift stored data in units of rows or columns simply by specifying the memory row or column address and shift amount. This can be done at high speed and can reduce the processing load on the main device that controls the image memory.

〔Example〕

FIG. 1 shows a static type RA to which this invention is applied.
A block diagram illustrating one embodiment of M is shown. Circuit elements constituting each circuit block in the figure are formed on a single semiconductor substrate, such as single crystal silicon, using known semiconductor integrated circuit manufacturing techniques, although not particularly limited thereto.

In the static RAM of this embodiment, the memory cells constituting the memory array M-ARY are coupled to both the X-axis word line and the X-axis complementary data line, and the Y-axis word line and the Y-axis complementary data line, respectively. be done. Therefore, normal access from the X-axis using the X-axis word line and Y-axis complementary data line and access from the Y-axis using the Y-axis word line and the X-axis complementary data line are possible. In addition, complementary data lines in each axial direction are connected to shift registers SRX or SRY.
This static RAM reads the stored data of the memory cell connected to the designated word line into these shift registers, shifts it a predetermined number of times, and then writes it again. It also has the function of using these shift registers to perform serial write or read operations in row or column units from an external device.

The static RAM of this embodiment is further provided with complementary common data lines for the X-axis and Y-axis, so that memory access can be performed bit by bit from both the X-axis or the Y-axis.

Therefore, in the static RAM of this embodiment,
A serial mode signal SRM is provided as a control signal for specifying a 1-bit unit access operation or a row or column unit serial access operation, and an access direction control signal X is provided as a control signal for specifying an access direction.
/Y is provided.

FIG. 2 shows a circuit diagram of an embodiment of the memory array M-ARY. Before explaining other circuit blocks in FIG. 1, the memory array M-AR
The configuration of Y will be explained. The MOSFET shown in the figure is
All are N-channel type.

In FIG. 2, the memory array M-ARY has n+1 X-axis word lines wxi arranged in the vertical direction of the figure.
~WXn and fi+1 set of X-axis complementary data lines DXO-D
XO-DXn-DXn and the same number of Y-axis word lines wy arranged in the horizontal direction in the figure.

~WYn and Y-axis complementary data line DYO・DYO~DYn
-DYn, and (n+1) two static type memory cells arranged at the intersections of these word lines and complementary data lines.

Each memory cell includes an N-channel MO3FET QI and C2 whose gates and drains are cross-connected to each other, as shown in memory cell MC0O in FIG.
These MOS FET Q 1 and C2 do L
Its basic configuration is a static type launch consisting of high resistances R1 and R2 provided between the twin and the circuit power supply voltage Vcc. The sources of MOS FETs Ql and C2 are coupled to the ground potential of the circuit. The drain of each MO5FET is used as the input/output terminal of the memory cell, and two sets of transmission gates) MO3FETQ3. They are coupled to the Y-axis complementary data lines DYO and DYO and the X-axis complementary data lines DXO and DXO via C4, C5 and C6, respectively. Moreover, these transmission gate MO3FETQ3. The gates of Q4, C5, and C6 are commonly connected and coupled to the X-axis word line WXO and the Y-axis word line WYO, respectively.

Similarly, other memory cells M arranged in the same row
The input/output terminals of C01 to M Con to M Cn0 to M Cnn are connected to the X-axis complementary data lines DXO, DXO to DXn-DXn through one set of switches MO5FET.
The gates of each switch MO3FET are respectively coupled to the corresponding Y-axis word lines WYO to WYn. In addition, the input/output terminals of other memory cells MCl0 to MCn0 to MCOn=MCnn arranged in the same column are connected to the switch MOS FET of the other set.
Y-axis complementary data line DYO・DYO-DYn-D via
Yn respectively, and the gate 1- of each switch MO3FET is respectively coupled to the corresponding X-axis word line WXO-WXn. From this, fi+1 memory cells arranged in the same row are coupled to n+1 sets of Y-axis complementary data lines by selecting and specifying the corresponding X-axis word line, and also in the same column. r1+1 placed in
By selecting and specifying the corresponding Y-axis word line, the memory cells are coupled to n+1 sets of X-axis complementary data lines, and storage data is read or stored.

Each of the X-axis word lines WXO to WXn is coupled to an X-axis address decoder DCRX, of which − lines are selected and specified.9 Meanwhile, each of the X-axis complementary data lines DXO and DXO to DX
n-DXn is the X-axis column switch cswx.
Corresponding bits 5RXO to 5 of axis shift register SRX
Coupled to RXn. In addition, the X-axis column switch CS
WX corresponding set of switches M OS FE 'I'
Q7, Qf3~Q9. X via QIO
It is coupled to the axis-complementary common data lines CDX-CDX. The gates of the MO5FET switches in each set are commonly connected, and
Data line selection signal DX from axis address decoder DCRX
O to DXn are supplied respectively.

The X-axis address decoder DCRX receives a complementary internal address signal axO supplied from the X-axis address buffer ADBX.
-axi (here, for example, an internal address signal axQ having the same phase as the external address signal AXO and an internal address signal a having the opposite phase
xQ is combined and expressed as a complementary internal address signal axO (the same applies hereinafter) to form a word line selection signal or data line selection signal for selecting the designated X-axis word line or X-other complementary data line. and the switch MO3FET of the corresponding word line or X-axis column switch cswx
supply to. The operations of these X-axis address decoders DCRX are controlled by a word line selection timing signal φ-sx and a data line selection timing signal φcsx supplied from a timing control circuit TC, which will be described later. That is, the decoding results of complementary internal address signals axO to axi by the X-axis address decoder DCRX are made into word line selection signals by the word line selection timing signal φ-sx, and are made into data line selection signals by the data line selection timing signal φcsχ. It is said that

In each memory cell, the corresponding X-axis word line is selected, Halbert MOSFET Q3, Q, and L are both turned on, and its input/output terminals are coupled to the corresponding Y and other complementary data lines. Also, by selecting the corresponding Y-axis word line and setting it to high level, ;ζ・C SOCH MO S
F E "1" Q 5 and Q6 are both turned on, and their input/output terminals are coupled to the corresponding X-coupled data line.

In the X-axis column switch C S W Only the data line is on the X axis.
It is combined with the supplementary common data pJCDX-COX. Thereby, memory access can be performed in units of one pinpoint.

n+l bit unit circuit S of X-axis shift register SRX
R X O = S R An input switch MOSFET provided between each flip-flop circuit and an output switch provided between each complementary data line and an output terminal with a relatively large driving force of each flip-flop circuit.
FET. The flip-flop circuits of these unit circuits are serially coupled, and the flip-flop circuit of the last unit circuit SRXn is coupled to the flip-flop circuit of the first unit circuit SRXO. As a result, the flip-flop circuit of each unit circuit is
Clock signal φ supplied from timing control circuit TC
Perform circular shift operation according to cpx. On the other hand, the input switch MOSFETs of each unit circuit are turned on all at once by the high level of the input timing signal φprx supplied from the timing control circuit TC, and the storage data read from fi+1 memory cells of the selected column is Load in parallel into the X-axis shift register. In addition, the output inch MOSFETs of each unit circuit are turned on all at once by the output timing signal φpwx supplied from the timing control circuit TC, and the stored data shifted by the X-axis shift register is transferred to the selected column. Write to n+1 memory cells in parallel.

The previous bit and last focus of the X-axis shift register SRX are coupled to the input/output circuit I10 via the serial data signal line SDX-SDX. Static type RA
In the serial write operation mode of M, write data serially supplied from an external device is transmitted to X! by these serial data signal lines. The read data taken into the 1h shift register SRX and taken into the X-axis shift register SRX in the serial read operation mode can be serially output to an external device.

From the above, this; (shift clock signal φcpx of axis shift I/regisc SRX, input timing signal φ
By using the prx and output timing signal φpwx in combination, it is possible to shift and rewrite the stored data in the H+l bit memory cells coupled to the selected word line by a predetermined number of times, and also to rewrite the stored data in the H+l bit memory cells coupled to the selected word line. It is possible to perform serial input/output of stored data in units of rows.

As shown in FIG. 1, Yf* word lines WYO to WYn and Y other complementary data lines DYO-DY 0-DYn-DY
Similarly, in Y-axis address decoder DCRY
, Y-axis shift register SRY and Y-axis column switch c
swy is provided. The Y-axis address decoder DCRY is supplied with complementary internal address signals ayO to ayi from the Y-axis address buffer ADBY, and also receives a word line selection timing signal φt from the timing control circuit TC.
vsy and a data line selection timing signal φcsy are supplied, and the Y-axis shift register SRY is supplied with a shift clock signal φcpy, an input timing signal φpry, and an output timing signal φpwy. - Also, the final bit of the Y-axis shift register SRY is connected to the input/output circuit by serial data signal lines 5DY-3DY! combined into 10;
The Y other complementary data line selected by the Y axis column switch C3WY is coupled to the input/output circuit I10 by the Y other complementary common data line CDY -CDY. From the above, these Y-axis shift register SRY and Y@-based selection circuit can perform bit-by-bit access or column-by-column serial access similar to the case of the X-axis described above, and the memory of each column can be Data can be shifted.

In FIG. 2, the X-axis address buffer ADBX and Y
The axis address buffer ADBY is
Address signal AXO"AXi or Y address signal AYO
~AYi is received, and a complementary internal address signal axQ~axt or a complementary internal address signal mayo□~-a 7% consisting of an internal address signal in phase with these external address signals and an internal address signal in opposite phase is formed, and the corresponding address decoder. These complementary internal address signals are also supplied to address multiplexer AMX.

As described above, in the static RAM of this embodiment, data stored in memory cells is read out to the corresponding shift register SRX or SRY in units of rows or columns, shifted by a predetermined number, and then written into those memory cells again. In this case, the row or column address is the X address signal AXO~AXi or the Y address signal AYO~
AYi, but since the other address signal is not used, this other address signal is used to specify the number by which the stored data should be shifted. Therefore, in the static RAM of this embodiment, the shift crofter signal φcpx supplied to each shift register
Alternatively, a counter CTR for counting φcpy and a comparison circuit MAT for comparing the count value of this counter CTR and a shift number specified from the outside are provided. Further, an address multiplexer AM for selecting the complementary internal address signal axe-axi or the complementary internal address signals ayo to ayi and transmitting the selected complementary internal address signal to the comparison circuit MAT.
X is provided. Address multiplexer AMX receives access direction control signal X from timing control circuit TC.
An internal a signal φxy formed according to /Y is supplied.

Address multiplexer AMX receives internal control signal φx
In the X-axis access mode where y is at a high level,
Complementary internal address signal ayQ-ayi is selected and transmitted to one input terminal of comparison circuit MAT. On the other hand, in the Y-axis access mode in which internal control signal φxy is at a low level, complementary internal address signals axQ to maxi are selected and transmitted to one input terminal of comparison circuit MAT. The output signal of the counter CTR is supplied to the other input terminal of the comparison circuit MAT. This counter CTR receives a shift clock signal φc supplied from the timing control circuit TC to each shift I register via the OR gate circuit OG.
px or φcpy is supplied.

In the shift operation mode of the static type RA 7w, the comparison circuit MAT compares the count output signal of the counter CTR with the complementary internal address signal selected by the address multiplexer AMX, that is, the shift number specified from the outside, and compares both. When they match, a high level match signal CM is output to the timing control circuit TC.The timing control circuit TC stops supplying the shift clock signal to the shift register due to the high level of the match signal CM.

By the way, in the 1-bit unit access mode, the X-axis column switch cswx and the Y-axis column switch csw
Complementary common data line CDX - CDX or CD by y
The read signal of the selected memory cell transmitted to Y-CDY is further amplified by the input/output circuit I10 and output to the external main device via the input/output terminal Dr10. Further, write data input from an external main device via the input/output terminal DI10 is converted into a complementary write signal by the input/output circuit I10, and complementary common data ffl+
, ; υ input, υ On the other hand, in the case of serial access mode, the serial data line SDX -
Read data and write data are serially input and output via the SDX or 5DY-7 and the input/output circuit I10.

The timing control a circuit TC receives a chip enable signal supplied as a control signal from an external main device, a write enable signal %7 (l, TEFBU completion selection signal), a serial mode signal SRM, and an access direction control signal X/ The various timing signals and internal control signals mentioned above are formed by Y and supplied to each circuit.

FIG. 3 shows a timing diagram of one embodiment of the shift operation mode of the static RAM of this embodiment. This timing diagram shows that this static type RAM
An overview of the shift operation will be explained below.

In the timing diagram of Figure 3, is the access direction? The high level of the ti17 rM signal X/Y specifies that the access is in the X-axis direction, and the
The X-axis word line to be selected is specified by i. Furthermore, the number of times the stored data read into the Y-axis shift register SRY is shifted is specified by the Y address signals AYO to AYi.

Serial mode signal SRM is set to low level to specify shift processing, and write enable signal WE is also set to low level.

The static type RAM is set to a selected state by the low level of the chip selection signal C3, and is set to the selected state by the low level of the chip select signal C3.
When E changes from a high level to a low level, it is brought into an activated state.

The static type RAM T receives the X address signal AXO=A supplied by the X-axis address decoder DCRX.
Xi is decoded. When the chip enable signal CE is set to low level at the timing when this decoding operation ends, a high level word line selection timing signal φtvsx is supplied from the timing control circuit TC to the X-axis address decoder DCRX. This results in
A designated X-axis word line is selected, and a read signal according to the stored data of n+1 memory cells coupled to this X-axis word line is sent to the Y other complementary data lines DYO, DYO~
It is transmitted to the Y-axis shift register SRY via DYn-DYn. At the timing when these read signals are established, the input timing signal φpry is supplied from the timing control circuit TC to the Y-axis shift register SRY, the input switch MOS FET is turned on, and the read data of fi+l bits is is taken into the Y-axis shift register SRY.

Next, when the input timing signal φpry goes low, the first shift clock signal φcpy goes high, and the contents of the Y-axis shift register SRY are shifted one by one to the next bit. Furthermore, the counter CTR increments in response to the fall of the shift clock signal φcpy. The stitch count output signal of this counter CTR is output from the comparator circuit M.
It is supplied to one input terminal of AT. The other input terminal of the comparison circuit MAT is connected to an address multiplexer AMX.
output signal is provided. Address multi-breather A
MX selects complementary internal address signals mayO to mayi according to a high-level internal control signal φxy supplied from timing control circuit TC, and sends them to the other input terminal of comparison circuit MAT.

The shift operation of the Y-axis shift register SRY is repeatedly performed by the shift clock signal φcpy supplied one after another from the timing control circuit TC, and at the same time, the shift operation of the Y-axis shift register SRY is performed repeatedly by the shift clock signal
R is also incremented.

In the comparator circuit MAT, when the count output signal of the counter CTR and the output signal of the address multiplexer AMX, that is, the number of shifts specified by the Y address signal AYO'AYi, match, the comparator circuit MAT outputs a high signal to the timing control circuit TC. Sends a level match signal CM. As a result, the timing control circuit TC uses the shift clock signal φ
The supply of cpy is stopped, the shift operation of the Y-axis shift register SRY is stopped, and at the same time, the increment of the counter CTR is also stopped.

In response to the high-level match signal CM sent from the comparison circuit MAT, the timing control circuit TC supplies a high-level output timing signal φpwy to the Y-axis shift register SRY. In the Y-axis shift register SRY,
The output inch MO3FETs (not shown) are turned on all at once, and the data held in each bit of the Y-axis shift register SRY is rewritten into the previously selected (n+1) memory cells. These write data are nothing but data stored in each memory cell before access, which is cyclically shifted a predetermined number of times.

The above shift operation is performed by setting the access direction control signal X/Y to a low level, so that Y! The same process can be performed for n + 1 f memory cells selected by the I11 word line and arranged in the row direction. Therefore, if you want to move the displayed image horizontally (for example, in the X-axis direction), set the access direction control signal This can be done by specifying and repeating the above operations. In this case, the main device sends 57:j! J controller only needs to update the Y-axis address,
There is no need to perform processing for shift operation.

Furthermore, when tilting the display image shown in Fig. 4, the main device can easily obtain a tilted image by simply calculating the distance from the fixed axis a-b and updating the Y-axis address. . Further, for example, when it is desired to rotate a displayed image, a rotated image can be obtained relatively easily and at high speed by repeating the above shift operation in the X-axis and Y-axis directions while performing appropriate zooming processing. In addition, by using the above-mentioned X-axis shift register s r< can be simplified and the processing burden can be reduced.

As shown in the above embodiment, when the present invention is applied to a semiconductor memory device such as a static RAM used as an image memory, the following effects can be obtained. That is, the +13 RAM memory array has a dual port structure that can be accessed from either the X axis (row) or the Y axis (column), and a shift register is provided for each data line, so that in - times of memory access, By providing a function to read stored data into the above shift register in units of rows or columns, shift it arbitrarily, and rewrite it, you can simply specify the memory row or column address and shift amount. The effect is that the shift processing of the stored data can be performed autonomously.

(2) By repeating the shift process in item (1) above, it is possible to achieve the effect that processes such as horizontal or vertical movement, tilting, or rotation of a display image can be performed at high speed.

(3) Items (11 and (2) above) provide the effect of reducing the processing load on the processor of the main device when moving, tilting, or rotating the display image.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. For example, in FIG. 2, the X-axis shift register SRX and the X-axis force input Rams inch cswx are connected to the same end of the complementary data line, but these are connected to both ends of the complementary data line, respectively. Also, a high resistance provided between the two MOS FETs constituting the launch of each static memory cell and the power supply voltage of the circuit can be used, for example, in a load using a P-channel MOS FET. The X-axis shift register SRX and the Y-axis shift register SR'/ coupled to the X-other complementary data line and the Y-other complementary data line, which may be means, do not have a basic configuration of a flimble-fromb circuit, but, for example, A dynamic shift register may be used, and the shift operation of each shift register may be controlled by applying a shift I/Cronk signal from the outside.
A common control circuit may be provided to centrally perform the above-mentioned shift operations, or various embodiments may be adopted such as a block configuration of a static RAM, a combination of control signals, etc.

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to a static type RAM for image memory, which is the field of application that formed the background of the invention.
The present invention is not limited thereto, and can also be used, for example, in dynamic RAM for image memory and various semiconductor storage devices for other uses. The present invention is applicable to semiconductor memory devices in which shift processing is effective at least in units of rows or columns, and devices including the same.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, the RAM memory array has a dual-port structure that can be accessed from either the X axis (row) or the Y axis (column), and a shift register is provided for each data line, so that the stored data is is read into the above shift register in rows or columns,
By providing the function to shift and rewrite an arbitrary number of times, it is possible to autonomously shift stored data in rows or columns by simply specifying the memory row or column address and shift amount. Processing such as moving, tilting, or rotating the displayed image can be performed at high speed, and
The processing load on the processor of the main device during such processing can be reduced.

[Brief explanation of drawings]

Figure 1 shows a static type RAM to which this invention is applied.
2 is a block diagram showing an embodiment of the static RAM memory array and its peripheral circuits of FIG. 1. fI? FIG. 13 is a conceptual diagram of the static type RAM shown in FIG. M-ARY... Memory array, cswx, cSW
Y...Column switch, SRX, SRY...Shift register, DCRX, DCRY...Address decoder, ADBX, ADBY...Address decoder, Ilo
...input/output circuit, CTR...counter, AMX...
・Address multiplexer, MAT...comparison circuit,
TC...timing control circuit. MC00~MCnn...Memory cell, Q1~Q10・
...N-channel MO3FET, R1, R2...resistance. Representative Patent Attorney Yoshio Ogawa ゛・ Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A plurality of X-axis word lines, Y-axis word lines, and X-axis data lines arranged in parallel in the X-axis and Y-axis directions, respectively;
Consisting of an axis data line and a plurality of memory cells whose selection terminals and input/output terminals are combined and coupled to the X-axis word line and Y-axis data line or both the Y-axis word line and the X-axis data line, It has a memory array that can be accessed from the X-axis and Y-axis directions, and an X-axis shift register and a Y-axis shift register whose unit bits are provided corresponding to the X-axis data line and the Y-axis data line, respectively, The data stored in the plurality of memory cells coupled to the specified word line is read to the X-axis shift register or Y-axis shift register, shifted by the specified number in the specified direction, and then read again to the specified word. A semiconductor memory device characterized by having a function of writing to a plurality of memory cells coupled to a line. 2. The number of shifts in the X-axis shift register and Y-axis shift register is specified via the X-address signal and Y-address signal input terminals, respectively, and the semiconductor memory device a counter for counting clock signals applied to the shift register during shift operation; an output signal of the counter;
2. The semiconductor memory device according to claim 1, further comprising a comparison circuit for comparing the address signal or the shift number applied via the Y address signal input terminal.