JPS6353589A - Access circuit for character generator - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an access circuit for a character generator.

[Prior Art] In recent years, as the functions of recording devices such as printers have improved, demands for high-speed printing and high resolution have been increasing. Most of the Korira printers use a microprocessor (MPU) in the control unit to improve functionality, but the processing speed of the MPU is an issue for high-speed printing and high-resolution processing, so conventionally, high-speed MPUs were used. However, this was one of the causes of increased printer costs. In particular, in order to achieve high resolution in a printer that prints using a dot matrix, it is necessary to increase the number of printed dots per area. This meant an increase in the number of character generators, which had the disadvantage of reducing the transfer speed of character patterns and reducing the processing speed of the MPU due to processing to compensate for the lack of address space for the character generator. .

[Problems to be Solved by the Invention] The present invention has been made in view of the above conventional example, and an object of the present invention is to provide an access circuit for a character generator that can read pattern data from a character generator at high speed. .

[Means for Solving the Problems] In order to achieve the above object, the access circuit of the character generator of the present invention has the following configuration.

That is, font information storage means for storing font information of a character from which pattern information is to be read; pattern number storage means for storing the number of pattern data of the character; code information storage means for storing code information of the character; The apparatus includes means for creating an address signal for the pattern information based on the font information, the number of pattern data, and the code information, and means for incrementing the address signal each time the pattern information is read.

[Operation] In the above configuration, an address signal for pattern information is created and output from the font information of the character, the number of pattern data of the character, and the code information of the character without reading the pattern information, and the pattern information is sequentially output from the character generator. can be read.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of overall configuration (Fig. 2)] Fig. 2 shows the access circuit 3 and MPUI of one embodiment of the present invention.
and a diagram showing a connection with a character generator 4.

In the figure, 1 is a microprocessor (MPU) that accesses the character generator 4 via the access circuit 3.
2 is a memory that includes a ROM that stores control programs and data for the MPLI 1, a RAM that serves as a work area for the MPU 1, and the like. Reference numeral 3 designates an access circuit that inputs various data and control signals from the MPU 1 and applies an access signal to the character generator 4. Reference numeral 4 designates a character generator that stores pattern information of characters and symbols.

5 is the data bus of MPU 1, 6 is the read signal signal (C
This is a control signal including S) and the like. 7 is a character generator address signal, which in this embodiment is composed of 20 bits. 8 is pattern data read out from the character generator 4. 9 is a read signal (CGRD) of the character generator 4, and 10 is a chip select signal (CGCS) of the character generator 4.

[Description of Access Circuit (FIGS. 1, 3 and 4) FIG. 1 is a block diagram of the access circuit 3 of this embodiment, and signals common to those in FIG. 2 are indicated by the same symbols.

The data bus 5 is composed of 8 bits (Do to D7), and is input to a font register 202, a byte number register 203, and a code register 204 via a buffer 200. The font register 202 is the lower 4 of the data bus 5.
For example, enter the font information of a character pattern by inputting bits.
If it is 0, it is stored as Gothic, if it is 1, it is Mincho, if it is 2, it is italic, and so on. Byte number register 2
03 stores the number of pattern data (number of bytes) per character to be read. code register 204
is the character code of the character you want to read, for example A S
This is a register that stores CII code.

205 is an input buffer for manually inputting the control signal 6, and 206 is a control signal generation circuit for generating latch signals 207 to 209 and various control signals based on the control signal 6. 210 and 211 are multipliers, which respectively input font information and the number of bytes or the number of bytes and a character code and perform multiplication, output the results to adders 212 and 213, and adder 213 outputs the address signal of the character generator 4. 7 is being created. 214 is a read counter which is incremented by 1 when pattern data 8 is read by 1 byte, and adder 2
The address signal 7 from 13 is incremented by +1. 215 is an output buffer for the address signal 7, 216 is an input buffer for the pattern data 8, and the pattern data 8 is the buffer 20.
1 to the data bus 5. 217 is an output buffer for the read signal 9 (CGRD) and select signal 10 (CGCS) to the character generator 4;

FIG. 3 is a diagram showing a specific circuit example of the access circuit 3 shown in FIG. 1, and for the sake of explanation, parts common to those in FIG. 1 are designated by the same reference numerals.

When the chip select signal (CS) and write signal (WR) of control signal 6 are input from MPLJ 1, buffer 2
00 is enabled and the data on the data bus 5 is supplied to the input terminals of each register 202-204. When address signals AO and At are both “0” and data is written, a latch signal 207 is output and the font register 202
Data is stored in . When AO is “1” and A1 is “0”, the latch signal 208 is output and the byte number register 2
03, when AO is O" and At is 1", latch signal 2
09 is output and the code register.

Data on the data bus 5 is stored in 204. In this way, the MPU 1 sets data corresponding to each register.

Reading of pattern data 8 is executed by MPUI outputting a read signal (RD) when both AO and AI are 1''.At this time, the output of OR circuit 300 becomes LOW, enabling buffer 201, and ,OR
The output of the circuit 301 becomes LOW and the CGRD signal 9 becomes c.
ctcsi.

The data is output together with the character generator 4, and readout from the character generator 4 is executed. Also, at this time, the read counter 214 is
It is incremented by 1 every time GRD signal 9 is output. This output,
is manually inputted to the adder 213, and performs the processing of the address signal. The read counter 214 receives a reset signal (
RES) is cleared by the NOR circuit 302 and the NAND circuit 303 when writing to each register 202 to 204.

Multipliers 210 and 211 are both constructed of gate array circuits, and multiplier 210 calculates the product of font information and the number of bytes, and multiplier 211 calculates the product of the number of bytes and the character code. The adders 212 and 213 are composed of a 4-bit full adder 304 (LS83), and generate the address signal 7 for the character generator 4. When the font information is "0", the address signal 7 of the character generator 4 takes the value of (number of bytes) An address signal 7 is created by adding a bias value of (font information) x (number of bytes) x 256) to (character code).

As a result, the start address of the character pattern information corresponding to the font information is created and outputted to the character generator 4 as an address signal 7.

In this figure, buffers 200, 201, 205, .
215-217 are 8-bit tri-state buffers such as LS244, and registers 202-204
are each an 8-bit latch such as LS273. The counter 214 is a counter such as LS393, 305
is a decoder such as LSI39.

FIG. 4 is a diagram showing a specific circuit example of the multipliers 210 and 211 in FIG. 3.

400.401 is an 8-bit tri-state buffer such as LS244, and 304 is a 4-bit full adder such as LS83 as described in FIG. This circuit has 8 bits x(xO~X7)XY(YONY
This is a circuit that performs the calculation 7) to obtain and output the 16-bit product 20-215.

[Description of character generator reading program by MPU (Fig. 5)] Fig. 5 is a flowchart of the process of reading pattern data for one character from the character generator 4 of the MPUI stored in the ROM of the memory 2. .

First, in step S1, font information is written by setting the lower two bits (AO, At) of the address signal to 0'' along with the chip select signal (C3) and write signal (WR), and the font information is set in the font register 202. .

Next, in step S2, similarly to step S1, if AO≧1. A
When 1=O is set and the number of bytes of pattern data is written, the number of bytes of pattern data is written to the byte number register 203. Similarly in step S3, AO-0, Al-1
When a character code is written in , the code data is stored in the code register 204 . As a result, the read counter 214
is cleared to "0", and the adder 213 outputs a 20-bit address signal 7 (CGAOO to CGA19) indicating the start address of the character to be read.

In step S4, both the address signals AO and At are set to 1" and the chip select signal (CS) and read signal (RD) are set to 1".
(execution of input command), read signal 9 (CGRD) of character generator 4 and select signal 10
(CGCS) is output and pattern data 8 is read out from character generator 4. The read pattern data 8 is stored in, for example, a video RAM or a print buffer as necessary. In step S5, it is checked whether all byte data of the specified character code has been read out. If not, the process returns to step S4 and the pattern data 8 is read out again. The read counter 214 reads out the pattern data 8 once. Therefore, the address signal 7 is automatically incremented by 1 each time the pattern data 8 is read.

As described above, according to this embodiment, the pattern address of the character generator can be obtained and the pattern information can be read out regardless of the address space of the MPU and without reducing the processing speed.

[Effects of the Invention] As described above, according to the present invention, pattern data can be read out from a character generator at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an access circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing connections between the access circuit of this embodiment, an MPU, and a character generator, and FIG. 3 is a specific circuit of the access circuit. FIG. 4 is a diagram showing a specific circuit example of a multiplier, and FIG. 5 is an operational flowchart of MPtJ for reading pattern data for one character from a character generator. In the figure, 1...-MPU, 2... Memory, 3... Access circuit, 4... Character generator, 5...
Data bus, 6... Control signal, 7... Address signal, 8... Pattern data, 9... Read signal (CG
RD), 10...Chip select signal (CGCS),
200゜201.205,215-217...Buffer, 202...Font register, 203...Byte number register, 204...Code register, 206...
...Control signal generation circuit, 207-209...
Latch signal, 210.211--multiplier, 212,2
13... Adder, 214... Read counter.

Claims (2)

[Claims] (1) font information storage means for storing font information of a character from which pattern information is to be read; pattern number storage means for storing the number of pattern data of the character; code information storage means for storing code information of the character; The method further comprises means for creating an address signal for the pattern information based on the font information, the number of pattern data, and the code information, and means for incrementing the address signal each time the pattern information is read. Characteristic character generator access circuit. (2) The means for creating an address signal includes a first multiplication means for calculating the product of the number of pattern data and font information, a second multiplication means for calculating the product of the number of pattern data and code information, and a second multiplication means for calculating the product of the number of pattern data and code information; 1. An access circuit for a character generator as set forth in Patent No. 1, characterized in that the access circuit includes an addition means for adding two multiplication means output values.