JPS6350992A - Digital level display device - Google Patents

Abstract

PURPOSE:To rapidly perform a correct display even at the time of switching resolution during display operation by logarithmically converting an absolute value signal and a peak held signal respectively by separate decoders. CONSTITUTION:A digital signal inputted to a converting circuit is converted into the absolute value signal. This absolute value signal is logarithmically converted by the decorder 2a and further to a displaying signal suitable for a display. The absolute value signal is held by a peak holding circuit 4. This held value is logarithmically converted by the decorder 2b and further converted into the displaying signal. Then, the outputs of both the decoders 2a, 2b are synthesized in a synthesis circuit 5 and the instantaneous level and the peak level of the digital signal are displayed on a display means 8. Accordingly, during the display operation, even when the selection of a selection means 3 is switched, the held value immediately before the switching is not left nor displayed. In such a way, the correct display can be rapidly carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital level display device suitable for use in compact disc (CD) players, digital audio tape recorders (DAT), and the like.

[Summary of the invention]

In the present invention, the absolute value signal and its peak-held signal are each logarithmically transformed by separate decoders.

[Conventional technology]

PCM1il for CD players, DAT, etc. In a recording/reproducing device, an analog audio signal is digitized and recorded on a recording medium, and during reproduction, the digital signal is converted into an analog signal and output. FIG. 2 is a block diagram of a digital level display device used, for example, in monitoring the level of a digital signal in such equipment.

In the figure, reference numeral 1 denotes a conversion circuit, which converts an input digital signal into an absolute value signal representing its absolute value and outputs it.The absolute value signal is input to a decoder 2 consisting of a ROM, logic gates, etc., and is converted into a decibel signal. (dB) It is logarithmically converted for display, and also converted into a display signal suitable for display. The output of the decoder 2 is input to a peak hold circuit 4, and its peak value is detected and held. The synthesis circuit 5 synthesizes the signal corresponding to the instantaneous level (absolute value) output by the decoder 2 and the signal corresponding to the peak level (absolute value) output from the peak hold circuit 4. This synthesized display signal is supplied to the driver 7, and the driver 7
The display means 8, which is composed of a plurality of lamps, LEDs, etc., is driven in response to the display signal. As a result, the instantaneous level and the peak level are displayed by the display means 8.

When the selection means 3 is operated to switch the resolution of the decoder 2, the display on the display means 8 can be displayed in steps of 3 dB or 1 dB, for example.

[Problem that the invention seeks to solve]

In this way, the conventional device peak-holds the output of the decoder 2. For example, if the selection means 3 is operated to switch to 1 dB resolution during display operation at 3 dB resolution, the peak hold circuit 4 Because the previous peak value decoded with the previous resolution is held.

There was a drawback that the peak value at the new resolution was not displayed unless a value larger than the hold value by about 3 dB or more was input. In order to prevent this, a reset switch 6 is provided in the peak hold circuit 4, and when switching, turn on this reset switch 6 to temporarily reset (cancel) the hold state.
I needed to.

[Means for solving problems]

The present invention provides a digital level display device that includes a conversion circuit that converts an input digital signal into an absolute value signal representing its absolute value, a peak hold circuit that detects and holds the peak of the absolute value signal, and a peak hold circuit that detects and holds the peak of the absolute value signal. a first decoder that performs logarithmic conversion; a second decoder that logarithmically converts the signal held by the peak hold circuit;
The present invention is characterized by comprising display means for displaying the level of a digital signal corresponding to the outputs of the decoder and the second decoder, and selection means for switching the resolution of the first decoder and the second decoder.

[Effect]

An absolute value signal indicating the absolute value of the input digital signal is held at its peak by a peak hold circuit. The absolute value signal is logarithmically transformed by the first decoder, and the peak-held signal is logarithmically transformed by the second decoder, respectively.

〔Example〕

FIG. 1 is a block diagram of a digital level display device of the present invention, and parts corresponding to those in FIG. 2 are given the same reference numerals. In the present invention, the absolute value signal output from the conversion circuit 1 is input to the first decoder 2a, and is also input to the peak hold circuit 4. Then, the output of the peak hold circuit 4 is sent to the second decoder 2b.
The outputs of the decoder 2a and the decoder 2b are input to the combining circuit 5. The other configurations are the same as in FIG. 2.

The digital signal input to the conversion circuit 1 is thus converted into an absolute value signal. For example, if a digital signal is expressed as a 2's complement number of predetermined bits, its MSB is the sign (O when positive, 1 when negative).
It is said that Therefore, if the data consists of, for example, 16 bits, and the MSB is 0 (positive data), the remaining 15 bits of the signal are directly used as the absolute value signal. On the other hand, when the MSB is 1 (negative data), for example, the MSB
and the exclusive OR of each bit and the negation of each bit), and add 1 to this to obtain a 15-bit absolute value signal. In this way, negative data is converted into the same signal (absolute value signal) as positive data at the same level.

This absolute value signal is input as is to the decoder 2a, its instantaneous level is logarithmically converted to display in decibels, and further converted into a display signal suitable for display. Further, the absolute value signal is input to a peak hold circuit 4 consisting of, for example, a comparator and a register, and its peak value is detected and held.

The value held in peak hold circuit 4 is sent to decoder 2
b, is logarithmically converted, and further converted into a display signal. The outputs of decoder 2a and decoder 2b are combined by a combining circuit 5. The output of the synthesis circuit 5 is supplied to the driver 7, and the driver 7 drives the display means 8 in response to the display signal from the synthesis circuit 5. In this way, the instantaneous level and peak level of the digital signal are displayed on the display means 8.

The decoders 2a and 2b, which are made up of ROM, logic gates, etc., each have built-in decoders with different resolutions (for example, 1 dB and 3 dB), and by operating the selection means 3, one of the decoding patterns is selected. When the input changes by 1 dB or more or 3 dB or more in response to the selection, the output changes. As a result, the display on the display means 8 is displayed in 1 dB or 3 dB increments depending on the selection.

The peak hold circuit 4 is connected before the decoder 2b and holds the peak value of the absolute value signal regardless of the selection by the selection means 3. Therefore, during the display operation, the selection means 3
Even if the selection is changed, the hold value immediately before the change will not remain or be displayed.

Note that the reset switch 6 of the peak hold circuit 4 can be omitted.

〔effect〕

As described above, the present invention provides a digital level display device that includes a conversion circuit that converts an input digital signal into an absolute value signal representing its absolute value, a peak hold circuit that detects and holds the peak of the absolute value signal, and a peak hold circuit that detects and holds the peak of the absolute value signal. A first decoder that logarithmically transforms the value signal, a second decoder that logarithmically transforms the signal held by the peak hold circuit, and a digital signal level converter corresponding to the outputs of the first decoder and the second decoder. a display means for displaying;
Since the second decoder and the selection means for switching the resolution of the second decoder are provided, even if the resolution is switched during display operation, accurate display can be performed quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital level display device of the present invention, and FIG. 2 is a block diagram of a conventional digital level display device. 1... Conversion circuit 2.2a, 2b... Decoder 3... Selection means 4... Peak hold circuit 5... Synthesis circuit 6... Reset switch 7... Driver 8... Display more than means

Claims (1)

[Claims] A conversion circuit that converts an input digital signal into an absolute value signal representing its absolute value, a peak hold circuit that detects and holds the peak of the absolute value signal, and a first decoder that logarithmically converts the absolute value signal. a second decoder for logarithmically converting the signal held by the peak hold circuit; and a display means for displaying the level of the digital signal corresponding to the outputs of the first decoder and the second decoder. A digital level display device comprising a selection means for switching resolutions of the first decoder and the second decoder.