JPS63503336A - オペレーテイング・システム機能の負荷を軽減するためのｉ／０システム - Google Patents

オペレーテイング・システム機能の負荷を軽減するためのｉ／０システム

Info

Publication number
JPS63503336A
JPS63503336A JP62507035A JP50703587A JPS63503336A JP S63503336 A JPS63503336 A JP S63503336A JP 62507035 A JP62507035 A JP 62507035A JP 50703587 A JP50703587 A JP 50703587A JP S63503336 A JPS63503336 A JP S63503336A
Authority
JP
Japan
Prior art keywords
processing
memory
control
input
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62507035A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0519179B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
ピーコツク・リチヤード・ブラウニング
マーフイ・フイリツプ・アーサー
ミシマー・デイビス・ロス
Original Assignee
ユニシス・コーポレーシヨン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/926,568 external-priority patent/US5764922A/en
Application filed by ユニシス・コーポレーシヨン filed Critical ユニシス・コーポレーシヨン
Publication of JPS63503336A publication Critical patent/JPS63503336A/ja
Publication of JPH0519179B2 publication Critical patent/JPH0519179B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP62507035A 1986-11-04 1987-10-29 オペレーテイング・システム機能の負荷を軽減するためのｉ／０システム Granted JPS63503336A (ja)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US92673886A 1986-11-04 1986-11-04
US92656786A 1986-11-04 1986-11-04
US92658886A 1986-11-04 1986-11-04
US926,567 1986-11-04
US06/926,568 US5764922A (en) 1986-11-04 1986-11-04 I/O system for off-loading operating system functions
US926,738 1986-11-04
US926,588 1986-11-04
US926,568 1986-11-04

Publications (2)

Publication Number Publication Date
JPS63503336A true JPS63503336A (ja) 1988-12-02
JPH0519179B2 JPH0519179B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-03-16

Family

ID=27506008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62507035A Granted JPS63503336A (ja) 1986-11-04 1987-10-29 オペレーテイング・システム機能の負荷を軽減するためのｉ／０システム

Country Status (4)

Country Link
EP (1) EP0290533B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS63503336A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA1306311C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3788346T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Also Published As

Publication number Publication date
EP0290533B1 (en) 1993-12-01
JPH0519179B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1993-03-16
EP0290533A1 (en) 1988-11-17
CA1306311C (en) 1992-08-11
WO1988003682A1 (en) 1988-05-19
DE3788346T2 (de) 1994-06-23
DE3788346D1 (de) 1994-01-13

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