JPS63503016A - Apparatus and method for encoding and decoding attribute data into error check symbols of main data - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Background of the invention The present invention relates to the field of digital data transmission. More specifically, the invention provides attributes Encoding data into parity or error checking symbols for main data , i.e. the additional data symbol is encoded with the information of the attribute data to be conveyed. Data recording of digital data being transmitted with encoded error checking symbols. Attribute decoded error check symbol The present invention relates to recovering the attribute data from the main data of the transmission cylinder combined with the code.

(In video technology, video tape recording is synonymous with transmission. In the field of digital data transmission (including error check symbol or harrity symbol used on the receiver side of the link. Attempts to use and thereby improve the reliability of the transmission process are common.

These error check symbols or parity symbols are used when binary codes are used. is usually a digital pit, but can also be a binary code. Error check In the following, the parity symbol will simply be referred to as an error check symbol. these Symbols can occur in a variety of different ways. Typically, the occurrence of error check symbols is or translate the main data to be recorded into one or more error check symbols This includes the use of error correction codes that are media that Linear error correction code(s) This translation divides the polynomial represented by the main data by an error-checking polycyclic. This is achieved by calculating the difference and using the remainder as an error check symbol. child There are many types of error correction codes that are known to perform the translation process. Richie: Some things are not linear. For those skilled in the art, the difference between linear and nonlinear is It's understandable.

After the error check symbol is issued, the main data and error check symbol are combined. and transmitted to a receiver. Then, in combination with the error check symbol, The main data where there is no is still called the main data and is combined with the error check symbol. The main data thus obtained will be called transmission data. Combination with error check symbol The main data encoded using Wasari attribute data will be referred to as attribute encoded transmission data hereafter. Bu.

According to the prior art, in the receiver the transmitted data is decoded into so-called A syndrome occurs. Syndrome if there were no errors in the transmission process. The system shows this state by having a binary code that typically has all zero values. . If there is an error, the syndrome will indicate it. Furthermore, if the error is If it is within the error correction range indicated by the check mark, the position of the error corresponds to the syndrome. Therefore, it is shown. The range of error correction is the total number of error check symbols attached to the main data. The range is generated and corrected by the use of error checking symbols. It is expressed as a number of errors. By the way, there is no limit to the number of errors that can be detected, but all There is no guarantee that it will be corrected. This is because the number exceeds the error correction range. be. Depending on the number of error symbols and the number of check symbols that have occurred, the error check symbol is decoded together with the main data, and the error correction is less than a predetermined number of symbols. It also makes it possible to detect some errors with a large number of false symbols. general uses a relatively large number of check symbols for a given number of main data symbols. The use of the error detection and error correction process increases the reliability of the error detection and error correction process.

In some digital systems, a set of discrete, dedicated data symbols are transmitted. It is commonly used to identify certain attributes of the main data to be processed. below This individual and dedicated data is called "attribute data." This attribute data is typically An example of this is digital color television transmission. In signal transmission and processing systems, attribute data is Horizontal synchronization pair force 2 - subcarrier burst phase can be used. This phase relationship is , is not specified in color television signals. This is the horizontal sync pulse The number of times the predetermined occurrence has occurred, and the color, subcarrier, shall be calculated based on the detected value relative to the number of burst initiations. I'll go. In digital video applications, this phase relationship is Sometimes it is calculated.

In the prior art, such synchronization versus color sub for every TV scan line It is customary to encode the carrier burst phase separately into several data symbols. It is about. These attribute symbols then identify the video belonging to this same horizontal scanline. - Added to sample datawords. Then, for each horizontal line, multiple data words that define the video (and typically the synchronization signal) and their associated The associated attribute data is transmitted. When this transmitted data is received, the attribute Synchronous paired color subcarrier burst phase information identified by the signal is used. processing of the accompanying video data.

The difficulty with this method is the transmission of attribute data in addition to the main data. A portion of the transmission channel bandwidth must be devoted to transmitting attribute data. In the case of storage, it refers to magnetic media or similar physical space around the memory. This is necessary for sexual data. In-band and recording in the transmission channel Space in storage memory is typically reserved to accommodate the bandwidth of the transmission channel. It is desirable to save space in storage memory in every possible way. It is.

Therefore, without adding an attribute data symbol to the transmitted data, i.e., the main without transmitting attribute data symbols in addition to data and error check symbols. Attribute data as digital data that enables transmission and decoding of attribute data In order to simplify and facilitate the need for a technique to decode data, the present invention For purposes of identification of circuits and data referred to in connection with the operation of the embodiments, certain Special terminology will be used hereafter. The invention is suitable for transmitting and receiving data. Embodiments of the invention are described in detail in connection with the embodiments, and therefore embodiments of the invention are transmitted below. The term "side" and "receiver" are used. In the first embodiment, the "sending side" is the undecoded error, which is referred to below as the "first error check symbol". The main data is generated to transmit the check symbol, and in the following, "attribute error Error check symbols called "check symbols" are combined into one attribute data class. occurs corresponding to a selected one component of the two sets of error chips. The check symbol is referred to below as the "corrected error check symbol" and is applied to the actual transmission. It should be understood that it refers to a circuit that is organized into symbols. (By the way, attribute data The "error check symbol" corresponding to the data is not used for the data, but is simply used as an attribute. t-identification of the relevant component in the data class and further check References to the symbol shall be understood to mean the data identification symbol. . ) In the second embodiment, the "transmission side circuit" refers to the most significant bit position of the main data. Error checking bits by integrating selected components of attribute data classes at ・Form an input string leading to the generator, and generate an error check from the input string. It should be understood that it refers to the circuit that generates the check signal. these The error check symbol is also referred to as a "modified error check symbol."

In the first embodiment, the receiving side circuit is: the main data under the received conditions (hereinafter referred to as (referred to as "received main data"), and after that main data, the second main data error is detected. Generate a new error check symbol called difference check symbol; second main data error check symbol and a correction error check, hereinafter referred to as the "reception correction error check symbol". combined with the received block symbol, hereafter referred to as “partial syndrome”. corresponding to each component of said attribute data class; Generates a set of error check symbols called "second attribute error check symbols": By combining the partial syndrome described above and each of the second attribute error check symbols, the following After that, it generates a series of symbols or symbol forms called "syndromes"; A zero detection operation is performed for each syndrome, and the attribute data encoded at the sending side is In order to make an excellent identification of selected components of the class of data, It is understood that it refers to a circuit consisting entirely of zeros or ft1i & another place. I want to be understood.

In the second embodiment of the present invention, the receiving circuit refers to each component of the two-attribute data group, Integrate with the received main data one element each time; receive each component of the attribute data class Corresponding to each combination with the main data, it will be called the "third error check symbol" from now on. All error check symbols are generated; each group of third error check symbols and the received modified error check symbol, referred to as "error check symbol". and generate multiple syndromes; perform zero detection operation for each syndrome. , identify which syndrome is made up only of zeros, and then add the attribute data. ・Identifies which components of the class are encoded at the sender. , should be understood as referring to the circuit. Afterwards, the data will be sent and received The operation of transferring data between parties is simply called transmission, but the recording of data that accompanies subsequent re-creation is also called transmission. Included in transmission.

In this book, "word" should also be understood to mean a certain number of symbols. and its main data field integrated with the error check signal is however, its length is usually equal to one word. The term "symbol" ” for each individual primary data field or any error checking field. Refers to a component, and in the case of the binary number system embodiment of the present invention, refers to a binary bit. For example, Reed Nromon (Reed-8) o　I　omon　) When implementing the present invention using a code, the "symbol" It will be understood that it refers to the individual numbers used in the matching method. Used in carrying out the present invention Some number systems that are used are discussed in more detail below.

The following abbreviations have already been defined in this document and are used in the drawings and embodiments of the method and apparatus of the invention. Shorthand notation for referring to various symbolic fields used in the description.

d=attribute data component to be encoded into error check symbol for main data A selection component of a class of - ie "attribute data".

D = Main data to be transmitted low, or "main data".

pd = input Kafka field or input error check bit generation circuit When enough leading zeros and D are combined to form one word, Error check symbol generated by the signal side circuit - i.e. "first main data Error check symbol.

Fax = A alone or combined with enough trailing zeros to form one word Assign an error check symbol that represents the person who , this term refers to symbols that have a one-to-one correspondence with the components of an attribute data class. It should be understood as meaning, and should not be used for error detection or correction of attribute data. Symbols and symbols that can be understood can be used as substitutes, and can also be used for attribute checking. Whether an error correction code or some other type of code was used to generate the symbol. The attribute data class to which the code word corresponds, regardless of the It should also be understood as a code word that identifies a specific component in a one-to-one correspondence. It is. Some practical examples will be defined and mentioned as decomposition examples in later pages. In the example, the attribute check symbol indicates that the attribute data field is the Pd field. The key that is shorter than or equal to the length of can be the attribute data itself.

P=first error check coded with attribute error check symbol generated at sender The error check symbols are transmitted regardless of the method in which they are calculated. - i.e. "corrected error check symbol".

p/= version of the main data received by the receiver after transmission - i.e. Main data”. This version/is due to errors introduced in the transmission process. , may itself have errors.

P' = version of the correction error check received at the receiver - i.e. "received correction Error check symbol. This version is based on errors introduced in the transmission process. Therefore, it may have errors in itself.

Pd' = 1 word as an input field to the receiving side error check bit calculation circuit Reception using D' or D' itself with enough leading zeros to form a code. error check signal generated by the detector circuit - i.e. the "second main data error check signal" ku symbol”.

By taking P"=Pd', Pd encodes the fax on the sending side. Receiver-side correction error caused by encoding Pa in the same way as Difference check symbol - By the way, this will be referred to as "pre-syndrome" from now on.

Syndrome = result of logical operation between P' and P''.

PaJ...Pax...Pan = Supplied to the receiving side decoding circuit and attribute data Mathematics of the identification of Ax corresponds to the constituent elements of the class Aj...m... An error check symbol that makes it possible to perform an operation is an "attribute check symbol." . The term "attribute check symbol" refers to a one-to-one pairing with the components of an attribute data class. It should be understood as meaning a symbol in the same relationship as the error detection or attribute. They are not to be understood as symbols used to correct data. In a claim, The word [attribute error check symbol] may be used and also emit an attribute check symbol. regardless of whether an error correction code or some other type of code was used to generate the certain constructs within the attribute data class to which the code words correspond. It should be understood as a code word that identifies components in a one-to-one correspondence. . Some examples which will be defined and referred to as decomposition examples in the following pages. The attribute check symbol indicates that the attribute data field is longer than the length of the Pd field. As long as p is shorter or equal, it can be the attribute data itself.

Pax = Reception corresponding to the selected component of the attribute data class selected on the sending side. This term Fax is an error check bit on the receiving side. It should be understood as meaning a symbol that has a one-to-one correspondence with the component. , shall not be understood as symbols used for error detection or correction of attribute data. Cree The term "attribute check symbol" can be used as a substitute in the An error correction code or other type of code was used to generate the check symbol. In the attribute data class to which the code word corresponds, regardless of whether understood as a code word that identifies a specific component in a one-to-one correspondence It is something that should be done. Several examples will be defined and mentioned as decomposition examples in later pages. In such embodiments, the attribute check symbol indicates that the attribute data field is As long as it is shorter than or equal to the length of the field, it will be the attribute data itself.

Alpha = The first error in the attribute error check symbol on the sending side for the selection operation on the receiving side. Selective mathematical and/or logical operations or operations used to encode the difference check signal. Arithmetic order. The preferred alpha operator is the logically exclusive O-operation, which is preferred This is because the number system is a binary system.

Alpha; hereafter called alpha inverse or inverse operator , the inverse operation of alpha or the reverse order from alpha. alpha is defined If you are not limited to alpha with a reciprocal operator, then the nonlinear code or in the case of linear codes, alpha may be undefined or singular. It doesn't have to be.

Identity operator = able to determine whether two groups of symbols are the same or not. any mathematical or logical operator. Expressed as a binary code or binary n-tuple In the case of any code with symbols that can be That is, the X-0R operation is a simple method of performing identity operations. However However, this operator also performs bit-to-bit or symbol-to-symbol comparisons in comparators, etc. Also plays. Is the identity operator independent of the characteristics of the alpha operator? However, it is said that it is a simple operation in the preferred binary code system. For this reason, it seems that the X-0 calculation is better.

The teachings of the present invention describe how data or error checking symbols are displayed. It will be understood that it is equally applicable to other number systems. of the present invention In some other embodiments, other mathematical operations defined for the binary number system may be used. I am using it. As long as the necessary mathematical operations can be defined in an advantageous number system, Any number system may be used in practicing the invention.

Broadly speaking, the comprehensive method of the present invention includes a circuit for generating a modified error check symbol. attribute data or attribute data error check symbols in the input stream to the including generating an error check symbol whose presence is corrected. follow , the selected components of the attribute data class are “encoded” and subjected to the alpha operation into a corrected error check symbol that is transmitted using a child. encoded on the sending side The identity of selected components of an attribute data class is "decoded" at the receiver. It will be done. The process performed on the receiving side includes an inverse algorithm between P' and Pd'. Depending on the behavior of the alpha operator, if an inverse alpha operator is defined, This also includes those designed to reach fax'.

If the inverse alpha operator is not defined or unique, then This is a different embodiment. If the inverse alpha operator is not defined , the receiving side circuit is combined with each of Pd' f:PaJ...Pan and multiple P# It may also be possible to generate one. Each of P” is defined as p/ by the identity operator. is compared to determine the identity of Fax". Fax' has the same P" as P'. Class PaJ to be generated becomes one component of Pan. If Inverse Al If the F operator is not unique, some constituents of the group formed by PaJ...Pan An ambiguity arises that the component satisfies the condition P′ alpha “Pd” . (Here, if alpha is defined, only Fax' satisfies this condition. do. ) In environments where this ambiguity is allowed, the output can be converted to Pal. Ru. In environments where this ambiguity is not allowed, the receiving circuit must satisfy this condition. Do not perform the operation Pd'alpha Fax for all faxes that may This necessarily generates a plurality of P'', and all P'' thus generated are Use the identity operator to compare with P' and thus determine the true identity of the fax. Separate. Pax is P of the ambiguous subset of Paj...Pax group corresponds to the component that produces P'' which is identical to '.

In some embodiments, the receiving circuitry configures the attribute data class for each component. and emitted for each component of the receive correction error check symbol and attribute data class. Exclusive zero logical operation or equivalent operation is performed between the generated pre-syndrome and By performing calculations, a syndrome occurs. Everything is zero, first detected The resulting syndrome is based on the attribute data cluster selected for encoding at the originator. identifies the components of the system and generates a corrected error check symbol.

Any error correction code may be used in implementing the present invention. But long , the inverse alpha operator is used in limited cases where a linear error correction code is used. defined only for the alpha operator in the The algebraic system in which the positive code is defined is extracted. If the nonlinear error correction code is used, or the linear error correction code is is defined for each of the classes of alpha operators that are defined for each one. When used with a fax, the receiving circuit is a true fax machine without any ambiguity. A trial and error method must be used to identify the

Any reference to linear error correction codes in this document will be understood by those skilled in the art However, the receiver circuit has to perform a trial and error matching step to decode the true Pax. It can also be implemented using a nonlinear error correction code, apart from the It will be understood that it means something.

At least two known practices referred to herein as decomposition method and direct method In embodiments, the invention can be practiced. In a broader sense, the following methods defines general aspects of preferred decomposition methods that may be carried out. In this book Other decomposition methods and apparatus for carrying out these methods described below are preferred embodiments of the present invention. This is a good example, followed by species in a wide range of genera. Preferred method of the invention A general way to implement any of the two error correction codes includes the following steps: However, use this to calculate the first error check symbol for the main data. Error correction is hereafter referred to as BCC1; components to be used in attribute data classes. Select any error correction code, hereafter referred to as ECC2. Using this, the attribute error check symbol is calculated from the selected attribute data. , said ECC2 may be different or the same as ECC1; any mathematical and/or perform logical operations between two sets of error checking symbols, or The result of the mathematical operation, that is, combining Pd and Pa f using the alpha operator , the attribute error check symbol is encoded into the first error check symbol, and is thereby transmitted. The main data and the corrected error check symbol to generate the corrected error check symbol (in the real-life example of a binary code, alpha is most preferably an exclusive OR Logical operation, which is the preferred code and preferred alpha);E i P' which calculates the second main data error check symbol Pd' using CC1; An inverse alpha operator is used between Pd' and an inverse alpha operator. The operator derives the Fax defined inside it: and the derived Fax into the corresponding construct of the attribute data class.

If the inverse alpha operator is not defined, it is only defined. If not, a trial and error method for decoding is used at the receiving end. these In the example, Pd2 is generated using ECC1 and using the alpha operator P′ and P′ of each class of Paj...Pan or Pan...Pan. and Pa satisfying the conditions expressed by Pd' and Pd'. This way Each such combination generates a presyndrome P”i. Each of the clusters uses an identity operator to determine the identity of the PaX. is compared with P'.

Fax is a class PaJ...Pan that is generated as P'' which is equal to P'. Corresponds to the relevant component.

From the above explanation of the decomposition method, if a few selected human lines are subjected to the process defined above. If it is possible to perform all mathematical operations with peace of mind, then is suitable. If the several human lineage can be mapped to corresponding binary values 0 and 1 If so, all the above requirements are satisfied. For example, the present invention uses two symbols (logical one and Main data and error check data expressed in a binary value system with only logic 0 and It can be applied to clock symbols, and each symbol can be applied to each binary nib of four binary bits. Readon Romanco with 16 symbols defined that can be mapped to Main data and error check are performed using the Reed-8o1omon code. The present invention can also be applied to the case where a block symbol is expressed.

The teachings of the present invention, in a preferred class of decomposition embodiments, consist of a plurality of attribute data. Attribute error check generated from one selected component (data) in the class A method for encoding the check symbol into the first error check symbol corresponding to the main data. Including methods and equipment. The corrected error check symbol is subsequently These may be transmitted together with the applicable main data symbols. Structure of attribute data components The symbol representing one selected component of the class consisting of the selected attribute data is also Attribute error check symbols generated from data component elements can also be used directly or individually. It is not transmitted separately.

Narrowly speaking, binary codes and exclusive OB-logical operations are used as alpha operators. Details of the preferred digestion method can be found in the individual error check notes for the inoculation field. It involves calculating the numbers and combining the results using exclusive zero logic operations. Head In the law, the encoding work on the sending side consists of main data D and attribute data A. individually and the resulting error check symbols are subjected to exclusive zero logic operations. are combined to generate a corrected error check symbol P. In other words, this decomposition method In this case, the error check symbol Pd is used as its own input field on the calling side. one with an input field D concatenated with enough leading zeros to form one word. Using this encoder will generate K. Error check symbol Pa is other encoder, and the other encoder receives one word as its input. input field Af concatenated with sufficient trailing zeros to form a code: said encoder It has at the input end of the The present invention is based on a limited group of attribute data components. It has the greatest effect on different classes. A cluster consisting of attribute data components In an embodiment where the lath is sufficiently small, the error check symbol Pa is used as a reference table. , or instead of calculating the fax using an error correction code, A non-computational circuit that allows rapid translation between error check symbols and faxes. It may also be provided that the

After error check symbols Pa and Pd are generated, these two fields The codes are combined by an exclusive-OR logic operation between each other. This is the attribute data error check symbol Pa of the selected component of the class This is the process of encoding Pd. Following the encoding process, the main data D and modification An error check symbol P is transmitted. In some embodiments, integrating with P A data field consisting of a It can also be used as an input field for a separate error checking system to create good.

This separate error checking system integrates the input field with P in subsequent bit positions. A separate error check symbol is generated for field D. These separate error checks The box symbol indicates any error correction component whose selection itself is not critical to the invention. may be generated along with the code. These separate error checking symbols are used along with the main data. After transmission, it is used by a separate error correction and detection circuit to correct Correct errors that occur within the performance range. Although it has occurred outside the correctable range, Any errors that can be detected are signaled and cause retransmission.

Whether or not the above error correction process is performed before the receiving circuit starts functioning. Regardless, the receiving circuit performs the same function in all disassembly method embodiments.

Its function is to decode the incoming data and encode it into the main data error check symbol. The objective is to determine the identity of selected attribute data. This is shortened (f In a preferred embodiment using error detection code (oreshortened), Add enough leading zeros to the leading bits of D' to form one word to be input into the encoder. This is achieved by integrating the

The encoder then generates Pd in the same way that Pd was generated at the transmitter. d' is generated. The value of Pd’ is then input to the partial syndrome generator as a single-manpower and the partial syndrome generator performs an exclusive OR logic between P' and Pd'. Partial syndrome is generated by performing operations.

A separate circuit then supplies each of the possible values for Pa - i.e. the syndrome The generator is supplied with one Pa for each component of the attribute data class. preferred In some embodiments, the PaO values are provided in a look-up table.

In other embodiments, the values could be calculated by the encoder.

The syndrome generator then combines each possible value of Pa with a partial syndrome. The syndrome is generated by performing an exclusive OR logical operation between the two. Exclusive Due to the nature of the logical OR logic operation and the nature of the generation of various amounts of input data, only zero A syndrome composed of Identifying specific attribute data selected for. Main data D' and its accompanying Therefore, the user's desired attribute data is the display, signal processing, etc. Or it works by following other methods.

In an alternative embodiment to the decomposition method, an inverse alpha operator is defined. , and assume that Pd, Pa, and P are all 1-bit binary data fields. As can be seen from the truth table of the exclusive zero function, it is unique. (P’X -0RPd') and Pad --- Exclusive OR between each component of the Pan class Instead of performing the operation, apply the inverse alpha operator between P' and Pd' The fax may be derived in one operation.

Another method of transmitting attribute data without actually transmitting the attribute data is There is a direct method in this book. In this method, the sending encoder has a code word formed by a D integrated into a human as a field; The A is placed in the leading bit position and defines the most significant bit position of the input code word D. occupy

(This is called a foreshortened error detection code example. . ) In another embodiment, one may input other input words into the encoder. For example, at the least significant bit position. Then the encoder is selected The g difference check symbol Pt- is generated from the single-manual word of D that integrates the people who have been selected. line In the shape error correction code, P is mathematically combined with the error check symbol Pa. is equal to the error check symbol Pd. In the most comprehensive embodiment, the encoding program Processes can be addition, subtraction, multiplication, division, or any combination of these. Okay, but I'll use the alpha operator, which is used for these mathematical operations. You may do so. Furthermore, logical operations such as AND, OR4 or exclusive OR It is also possible to use a combination of mathematical operations and logical operations. minutes As in the solution example, the direct method example uses a linear error correction code or a nonlinear error correction code. Any correction code can be used. Add linear error correction code to alpha operator. The direct method using the code is that the alpha operator is a defined inverse Limited to alpha operators with alpha operators, the receiver circuit can directly , the inverse alpha operator can be used to decode the fax biometrics. .

Nonlinear error correction code or linear error correction code and alpha are defined. Directly using the alpha operator, which is not limited to the alpha group where In a method example, a complex trial-and-error method is used to solve the biological ambiguity of fax. It is necessary to remove it. In the preferred embodiment, the exclusive OR logical operation Used for encoding and decoding. After that, P is transmitted.

On the receiving side, in embodiments where the inverse alpha operator is not defined, Then, each possible A value obtained by the class of the attribute data component is bit position (or the selected A was concatenated at the originating side) (integrated into the same bit position as ).

The field for this person and B is then the input code word for the other encoders. becomes the code. This encoder integrates each of the possible input words D' Calculate the error check symbol D" for each possible value of A. There exists a set value P". The value of P" is fed to the input of the syndrome generator and the The raw material is the identity comparison between all P'' and P' generated in this way for each P''. By doing this, a syndrome is generated for each P#. Preferred two-way price implementation In the example, the identity test is an exclusive OR logical operation between each P'' and P'. , these are receiver versions of modified error checking symbols. Syndro, all made up of zero The system identifies the particular value of A selected for encoding at the transmitter.

The device of the invention for realizing the disassembly method is serial in its architecture. may also be parallel, or a combination of these may be used. In other words, both the sending and receiving sides It may be purely in series or in parallel, or it may be a hybrid of these. Furthermore, the sender It can be in series and the receiving side in parallel, or vice versa. Both decomposition method and direct method are pure series and pure parallel, which will be explained in detail later in the detailed explanation. can be described in detail. That is, either the transmitting and receiving sides are in series or both sides are connected. An example is described below where . For simplicity, these examples will not be summarized here - as those skilled in the art will be familiar with the various decomposition methods and This is because all of the transformational examples of the direct method are understandable.

Devices for direct methods can also be used in series or parallel or hybrid architectures. It could be realized as a. Similar to the disassembly method, the transmitter and receiver are connected in series or may be either parallel or a combination of parallel and series. Furthermore, The transmitting side can be in series and the receiving side in parallel, or vice versa. Figure 1A shows an implementation of the present invention in which the alpha operator is an exclusive OR logic function. 2 is a conceptual flowchart of the disassembly method performed.

FIG. 1B shows how the alpha operator is inverted at the receiving end of the embodiment of FIG. 1A. The f operator is defined and is solitary (no other identical one exists). 2 is a conceptual flowchart of an embodiment in which

FIG. 1C shows how the alpha operator is inverted at the receiving end of the embodiment of FIG. 1A. Conceptual flow of an example in which the FF operator is defined or made non-isolated It is a diagram.

FIG. 2A shows a direct implementation of the present invention in which the alpha operator is an exclusive zero logic function. 1 is a conceptual flowchart of the method.

Figure 2B shows how the alpha operator is inverted at the receiving end of the embodiment of Figure 2A. Conceptual flow of an example in which the f operator is not defined or solitary This is a diagram.

Figure 2C shows the inverse alpha operator at the receiving end of the embodiment of Figure 2. Conceptual flow of an example in which the FF operator is defined or made non-isolated It is a diagram.

Figure 5A shows the disassembly method with serial data evaluation architecture at the receiving end. FIG.

FIG. 3B shows how the alpha operator is inverted at the receiving end of the embodiment of FIG. 3A. Conceptual flow of an example in which the f operator is not defined or solitary This is a diagram.

FIG. 5C shows how the alpha operator is inverted at the receiving end of the embodiment of FIG. 3A. Conceptual flow of examples in which the f operator is defined or is changed to be solitary It is a diagram.

FIG. 4A implements the decomposition method of the present invention with alpha as an exclusive OR logic function. Diagram illustrating a parallel data evaluation architecture machine for.

Figure 4B shows how the alpha operator is inverted at the receiving end of the embodiment of Figure 4A. Conceptual flow of an example in which the f operator is not defined or solitary This is a diagram.

Figure 4C shows how the alpha operator is inverted at the receiving end of the embodiment of Figure 4A. Conceptual flow of an example in which the f operator is defined and is solitary It is a diagram.

Figure 5A includes an exclusive OR logic operation on alpha - Figure 5B shows the implementation of Figure 5A. An inverse alpha operator is defined for the alpha operator on the receiving side of the example. , and is a conceptual flowchart of an embodiment modified to be solitary.

The 6th person diagram assumes that alpha is a general alpha operator that includes an exclusive OR logic operation, A book that makes the inverse alpha operator undefined or non-isolated. Diagram showing a parallel data evaluation architecture machine for implementing the direct method of the invention .

Figure 6B shows how the alpha operator is inverted on the receiver side of the embodiment of Figure 6A. Conceptual flow diagram of an example in which the rufa operator is defined and changed to be solitary It is.

Figure 7A shows that the inverse alpha operator is defined and Implementing the decomposition method of the present invention using the alpha operator including the exclusive OR logical operation 1 is a flow diagram illustrating a general method for doing so.

FIG. 7B shows the alpha of the embodiment of FIG. 7A when the alpha operator is not defined. 2 is a conceptual flowchart of a modified embodiment of the invention.

FIG. 8A shows a general apparatus for carrying out the method of the embodiment of FIG. 7A.

FIG. 8B depicts a general apparatus for carrying out the method of the embodiment of FIG. 7B.

Detailed description of the invention Looking at the first person diagram, we can see that the present invention is implemented using the alpha operator as an exclusive OR logic function. The disassembly method is shown in a flowchart. This is an example of trial and error. This decomposition The method performs an error check on selected components of one class of components of attribute data. The check symbol is encoded into an error check symbol for the so-called main data, and the correction is performed using A correct error check symbol is generated and transmitted together with the main data. receiving side The method evaluates the incoming data and selects attribute data for encoding at the sender. identifies a particular component within a set of components of the data and outputs its data.

The first step in the decomposition method of the present invention, error check symbols for main data Calculation of Pd and error check symbol Pa (also called attribute check symbol) By calculating, this is the attribute data for one selected component of the class. It is carried out against The Pa check symbol actually detects errors in the attribute data. It is not used for correcting. Actually, how many of these symbols are there? In some embodiments, it may be the attribute data itself, or they may be attribute data. data into a code word that identifies the attribute data that it accompanies in a one-to-one correspondence. It was a formalized thing.

In a preferred embodiment, Pd is the use of main data D, as shown in 201C. Calculated by integrating leading zeros into bit positions that are not present. person skilled in the art Then understand that the leading zero is not necessary to define the magnitude of D. cormorant. Therefore, this step can be omitted. A similar partial idea is that the book The book describes all methods for integrating leading zeros and such steps. The same can be said about the circuit for realizing the top-up.

In this document, any steps defining subsequent zero integration, and any implementation In the example, all circuits provided to realize such steps are omitted. Yes, but trailing zeros are required to define the magnitude of the digital number. Please understand that.

In a preferred embodiment, a sufficient number of leading zeros are added to the main data so that The leading zero, the main data D, and the error check symbol P generated from the main data. d are integrated and equal to the number of symbols constituting one word. This integration is shown at 22. It's been done. Pd converts the main data D with its integrated leading zero into a conventional engine. It is calculated by inputting it to the coder 24. This encoder is A difference correction code is also implemented. Using a linear error correction code reduces the operating speed. The alpha operator is defined as the inverse alpha operator. For the same reason, it is advantageous to limit the number of operators to those that can be used. Furthermore, the main advantage is , for a defined inverse alpha operator, the true identity of a fax is the reception For the state of Pd' and P' on the side, simply use the inverse alpha operator. It is possible to detect it immediately by simply applying it between these two amounts. If this inn If the birth alpha operator is not defined or if it is not isolated. fax, the receiving circuit uses a trial-and-error process to delete the fax until the true fax is found. The process must be completed.

This takes a very large amount of time. However, the present invention The alpha operator is an alpha operator whose alpha is defined and It may be implemented using a linear error correction code where the operators are not limited. , or the inverse alpha is undefined or isolated. It can also be implemented by a non-linear error correction code. defined As an example of an i alpha operator that does not have an isolated inverse alpha operator, There is an AND logical operator. Calculated for 1-bit Pd and Pa fields Here is an example of the AND alpha operator.

Alpha operator = AND Pd Pa P Here, the alpha operator converts the Pd and Pa 1-bit fields to the 1-bit field in the right column. This is an AND logical operation that converts the field into the P field. The inverse alpha operator is This is a logical function between P and Pd, and this function gives Pa in the right column as shown below. Ru.

The inverse alpha operator is not unique Pd P Pa In the first state of Pd and P, Pa has two different values, which of these also satisfies the conditions of Pd and P0, which is ambiguous for the inverse alpha operator In some cases, it is called not unique. This ambiguity is resolved in the receiving circuit. The only way to eliminate ambiguous subsets is through trial and error decoding. All of Pd' and Pa in Compare each generated P" with P' and determine which Pa becomes P#, which is the same as P'. This will determine the identity of the fax. In this example, this method is ambiguous. does not result in the removal of Ambiguity must be tolerated as it is. In some applications, this is accepted; in other cases this is not allowed. The problem of ambiguity is Pd, P The larger the fields of a and P, the less serious it is. Furthermore, general Generally speaking, the number of components of the attribute data class is large in the Pd field. This is much smaller than the total number of combinations created by error check pits. . Therefore, attributes that exist in ambiguous subsets with unused combinations It is possible to separate the constituent elements of a data class. Therefore, what is the ambiguity? It can be effectively removed even for the alpha operator, and any algorithm of the present invention Use with the rufa operator, any system, and any error correction code be able to. With this in mind, the various changes mentioned below Further embodiments will be better understood.

The encoder 24 has a plurality of exclusive OR gates based on a unique generator polynomial. Conventional parity generation configured by combining to be able to perform division The division operation is unique to the generation of CRC check pits.

The error check symbol generated by the encoder 24 is then determined by this division. This is the coefficient of each term of the resulting residual polynomial. Such techniques are used in the commercial world It's well known and I won't even explain it.

The present invention does not limit numerical representation to the binary system.

The logical and/or mathematical operations of the alpha operator are similar to other operations described within this document. Defined by the exclusive OR logic operation used in the examples, Any number system that can produce a linear map in the binary number system may be used.

Therefore, attribute data person and main data D1 necessary mathematical and/or logical operations Any code can be used to display it as long as it can be defined. said Reed Solomonko An example of such an adaptable code is a linear code.

A binary code has only two symbols, these are 0 and 1, and The de Solomon code can be used even with a number obtained by multiplying it to the same power as long as it is a prime number. It is possible. One such code has 16 defined symbols. be. Each of these symbols is directly divided into four binary bits by a mathematical relationship. mapped to nibbles. The number represented by this binary value can then be conveniently used The two terms bit and symbol are used interchangeably here, and both can be used interchangeably. Code 1 Alphabet # means an element that can be integrated into a code word.

Selected structure of attribute data element class: error check bit for element is It may be provided in any different manner based on the method of FIG. For example, in series There is one bus 27 supplying each of the components of the attribute data class in the stream. The selected component Ax, which may be present, is then strimmed by suitable equipment. Convert the output to Fax bit or change it to make bus 27 into multiple buses. Each of them carries one component of class M...Ax...An . Fax using a suitable device such as a multiplexer to select the bus transport Ax Ax for encoding may be supplied. These two 7-Kitechi The device that selects one of these is bit-serial, bit-parallel architecture, may be an architecture that is a hybrid of these two. such a combination Devices based on functional designs for are well known to those skilled in the art.

The above is true for all the examples described in this book. Ru. That is, multiple units of zones such as the constituent elements of an attribute data class are created by trial and error. A number of components of the attribute data class must be manipulated in embodiments using may be provided by staggered serial streams or may be provided by multiple data paths in parallel. The columns may be fed simultaneously. Any of the examples described in this document Regardless of the point in time when processing data, it can be parallel, word serial, word parallel, or group parallel. Loop series, word parallel, or a hybrid architecture It may also be something that you have. In other words, either parallel or series architecture Even though many components of the attribute data class are handled by the Functional units of any of the described embodiments, e.g. encoders, concatenators, ALUs , bit stripper, logic gate or Fi logic function operator, multiplexer , output circuits, identity detectors, etc. can be bits, bytes, words, or groups. Has a series or parallel architecture organized by loops Which architecture to choose is a matter of design choice based on speed, cost, etc. It is. Details of the various architectures for the functional units will be self-explanatory to those skilled in the art. It is about Ming. The details of their functions and the flow of operation in various embodiments are explained below. Describe it. i.e. some of the different method permutations, different conditions for the α operator and Some of the overall architecture for processing elements of a large amount of data is stated below. possible for each functional unit in each embodiment We do not define the quality of each circuit.

It is possible that a vast number of permutations are possible, and such a circuit is beyond the scope of the person skilled in the art. Something that can be easily designed if you have some knowledge of the target area and the order in which it functions. This is because.

Appropriate error checking bits corresponding to the selected constituent elements of the attribute data class. The steps for providing . child As an example of execution of step 28, error check signal Pa) is encoder 2. 4 or performed by encoder 24. It may also be calculated using an encoder that executes other error correction codes.

In such embodiments, trailing zeros may be used for selected attributes starting at the least significant bit end. combined with the sex data component. Furthermore, step 28 includes the Pd file of the attribute data 26. encoded into a codeword Pa with a length shorter than or equal to the length of the field It may be. In some embodiments, the attribute data 26 is a Pd field. If the field length is less than or equal to the length of the Pd, step 28 It may be a process of supplying the attribute data itself to be encoded along with the symbol; This method is not preferred. Generated input code The word is shown at 26. The output code string has an attribute error check symbol is the attribute check pin) Pa. In other embodiments, error checking It is possible that Pa is supplied by a reference table, and in this table corresponds to the selected wII component of the class whose input address is the attribute data element. There is. For each such 111 component in the attribute data class, In the lookup table, if each component of the attribute data class has its corresponding error check The check bits are encoded by an encoder as shown at 24 in Figure 1. The corresponding error check bits would be stored, as would be the case. other fruits The example has one input boat for the class name component of the attribute data element. A multiplexer is used. Which input is the output port depending on the selected signal Controls which attributes are bound to certain selected constituent elements of the attribute data class. The multiplexer is controlled to supply error check bits corresponding to the It will be done.

Main data with error check bits from selected components of attribute data class The error check bit correction process for the data is performed using the α operator indicated by 30. It is clearly shown. In the preferred embodiment, a binary number system is used and the α operator is an exclusive 01'l logical operation, but in other embodiments, any α operator May be selected. Error check bit for main data Pd and attribute data cluster The error check bits for the selected components of the space Pa are both the same predetermined number. A data field consisting of bits. The number of bits is selected by the user. This will depend on the reliability requirements and other characteristics of the system in which the invention is used. The α operator indicated by 30 in Fig. 1 calculates each bit of Pd and its corresponding bit-by-bit exclusive OR operation between the bits in Pa or the α operator other mathematical and/or logical operations or their order selected for For simplicity, the α operator is shown as in the preferred embodiment. In the same way, exclusive OR@arithmetic operation is performed. However, α is an exclusive OR operation. Other examples in which the inverse α operation is defined are also described, Furthermore, if the inverse α operator is not defined or is not Other embodiments are also described with reference to the drawings.

In the preferred embodiment, the output of the bit-by-bit exclusive OR operation at 30 is This is a field for the correction error check bit P. This field is the least significant bit The correction error check bit Pt is integrated with the main data bit D located at the position (correction error check bit Pt). The correct error check bit can be recovered as the original P-field up to -1 at the receiver. It doesn't matter where they are placed). Main data D and correction error check The combined field consisting of bit P is transmitted over transmission link 32 in FIG. It is transmitted and encoded as indicated by /i. Attribute data A is transmitted does not need to be encoded or encoded, since its identity is in the error check bit P. This is because it is encoded.

On the receiving side, the selection of the method of the present invention depends on whether the inverse α is defined or Or it depends on whether it is undefined or isolated.

1st A.

The first step in all possible embodiments of 1B1 and 1C is the leading zero step. By integrating the trings into the most significant bit positions of the received data D', This is represented by an exclusive OR logic operation at 34. Those skilled in the art can guide you. It is self-evident that zero is not important for determining the value of a digital number. Moshiko If the step of is used, the output of the exclusive OR operation at 34 is shown at 36. bit format. Bit format in 36 as well as bit format in 22 The format is one word long in the embodiment using the shortened error correction code. Ru. The received main data in bit format 36 and leading zeros are is applied to encoder 38 as a string. This encoder 38ij on the sending side The error correction code executed by encoder 24 must be executed at , outputs an error check bit Pd'.

In the embodiment shown in FIG. 1A, the exclusive OR logical operation is not used for the α operator. A trial and error method is used to determine the identity of the fax. In this example The names of the constituent elements of Pd' and class Pat...Pan are indicated by 40. are combined in an exclusive OR logical operation to produce multiple P' fields. . The components of the Pat...Pan class are serial and parallel inputs to the bus 44. To illustrate the point already made about the architecture, the Pat...Pan click The components of the laser are supplied in series on bus 44 for trial and error evaluation. Alternatively, multiple It may also represent a parallel bus. Exclusive OR function unit 40 has components Pat...Pan1 Regardless of which architecture is selected and supplied, The unit 40 may be a series or parallel architecture or a hybrid architecture. Needles may be installed as a cutia. For example, if the incoming data is a serial bitstream If Pa1. is assembled in a shift register that enters in series and exits in parallel. All parallel outputs are connected to the corresponding bits of the Pd′ field and Pa simultaneously into multiple exclusive OR gates that combine one bit of the field. be accepted. Similarly, if the output stream is coming in serially, The cut 40 is composed of a shift register that enters in series and outputs in series. You may. Class Pa1. ...As the Pan bits arrive, they shifted along the shift register or with the corresponding bit of the Pd′ field. be coupled at the serial output of the shift register in a single exclusive 01-L gate. There is also. Similar architecture has multiple components of class Pat...Pan. It may also be applied to more units 40 arriving at the same bus. The generality of the above is It applies equally to all functional units in all embodiments.

The plurality of P" fields generated by unit 40 are P' field in the tar unit 48. eye for bus 58 The output of the dentity test is multiple syndromes. The operator in 49 is , it is possible to distinguish when two code words become the same. Representing any of the identity operators that symbolize any circuit There is. In the binary embodiment, this identity operator is an exclusive OR gate. , which means that the exclusive OR of two identical codewords is always zero. This is because it is. The syndrome is then demonstrated by step 50. are checked to determine which ones are zero. Zerothin supports fax Drome represents the circuit represented by step 52 by data bus 51. The correct attribute data Ax is output.

In Figure 1B, an inverse α operator 39 is defined and an isolated real Examples are shown. All functions preceding function 43 have already been associated with Figure 1A. Same as stated. Therefore, I will not describe it here. In this example Then, the identity of Pax is compared with Pax k as expressed in 43. Therefore, it can be directly determined by performing an inverse α operation between Pd' and P'. can. From the fax, the correct corresponding attribute data is sent to the data path 41 and step It may be outputted as represented by 52'.

Figure 1C shows that the inverse α operator is undefined and non-isolated, Another example is shown in which a trial and error method has to be performed. In this example All steps involve unit 40 providing multiple partial syndromes to data path 47. Using the α operator in place of the exclusive OR operation to give P, the class Pat... Each of Pan.

The same as described above in FIG. 1 except that the I11 component is combined with the field Pd'. It is the same as . These P' data fields are each identified by an identification operator 49. It is combined with the P' field. The result of this operation is which P“ corresponds to Pax. Determine. If the identification operator 49 is an exclusive OR operation, the identification or identity test Output circuit 50 becomes a zero detector, which is the output of the exclusive OR operation in data path 53. fax through the data path 51 to the output circuit 52 which outputs the corrected attribute data. Output. Details of such an example where any general α operator is used can be found in This will be discussed below in connection with FIGS. 7 and 8.

With reference to Figure 1A, it should be noted that the α operator is an exclusive-OR logic operation and the trial and error recovery A more detailed description of the decomposition method, such as the encoding method used, is given next. this In the trial and error decoding example, the components of the class Pat...Pan are as follows: They may be provided simultaneously or in a serial manner, as will be shown in more detail below. this Represented by operation #''lt differential check bit supply step 42 and transmitted A preferred circuit for configuring the side error check bit supply step 28 and and may be configured by any of the devices described above. In a preferred embodiment Therefore, the error check bit supply steps 28 and 42 are performed by It is structured by either. Compute error check bits from input string indexes the error check bits for a given attribute data component or is the hardware error check bit pattern of various attribute data components. By selecting the appropriate input from a multiplexer whose inputs are The preferred embodiment uses these techniques without calculating Pa bits, since the time consumption is very high. use Step 30 uses a different encoding process than exclusive OR. In embodiments where the encoding process is the inverse of the encoding sequence, the attribute data Step 4: Supplying all error check pins for each component of the lath 2 is unnecessary and may be omitted.

If an exclusive OR logical operation is used or the inverse α is undefined or singular General Methods Used in Received Images for Trial and Error Examples #- Error check for each of the n possible components of the class of i′ attribute data components. (picture) t syndrome calculation device. attribute data component Each set of error check bits for one particular member of the class of When supplied, the error check for the syndrome FiPd' and the attribute data component is It is calculated by performing an exclusive OR logic operation or an α operation with the check bit. calculated. One such pre-syndrome is the class of attribute data ts components. is calculated for each component of Next, presyndrome has multiple The X-0R gate is suitable for identification or identity performance, as it generates the syndrome A one-to-one comparison is made to the P' field by the operator. A certain sinde that is all 0 Assuming there is no error during transmission, the ROHM is encoded by the transmitting side. identify the specific attribute data components selected for the process. Attribute data component class one or more providing error checking bits for individual components of the The step of is indicated by busbar 44 in FIG. 1A.

Each syndrome calculated in FIG. 1A is determined by the identity operator 49. 50 in FIG. 1A, which is an emissive OR operation, and r is Pd'. P′ which is equal to exclusive ORed Pa and equal to exclusive ORed P′ Yes.

As is clear from the occurrence of P on the transmission side, the modified error check pitch) P It is equal to the quantity Pc exclusive ORed with Fifi Pa. On the receiving side, it is rejected as P/. The quantity Pd' subjected to exclusive OR operation and the quantity Pd' subjected to exclusive OR operation is the quantity (Pa=F and exclusive is equal to exclusive ORed Pd') and exclusive ORed P'.

Therefore, if there is no error in the transmission of P, P' matches P on a bit-to-bit basis, and P ' and exclusive 0) are all 0. This situation is caused by the error check bit. The error check bit Pa supplied by the bit supply circuit 42 performs an error check on the transmitting side. Match with the error/check bit Fax supplied by the check bit supply circuit 28 It only occurs when you do. Therefore, in the serial embodiment, the transmission side selects for encoding the Error check pin for a specific component of the selected attribute data class) Fa When x occurs in the pre-syndrome calculator represented by 40 in Figure 1A, 50, if the identity operator 49 is an exclusive ORI logical operation, all It becomes 0. Encoder supplied by error check bit supply step 42 For attribute data classes whose check bits were not selected for encoding on the transmission side. When corresponding to one component, all syndromes at 50 are not 0.

After the syndrome calculation in Figure 1A, the syndrome is calculated in block 50 (Figure 1). This is a Fia detector). Sent to Tep. If syndrome 48 is supplied in serialized state, then 0 The detection step is when the error check bit Fax reaches the syndrome calculation step. It generates a signal that only indicates an all-zero syndrome at a specific time when

The last step in the decomposition method is to create the attribute data class corresponding to the all-zero syndrome. The goal is to output the correct components of . In one device, this Specific error check pins (Pa) supplied to the Roam calculation circuit and their corresponding The output of the 0 detection circuit is maintained while maintaining the tracking state of the correspondence between the attribute data and the person. This may be done by monitoring the force. The output of the 0 detection circuit is all 0. When indicating that the syndrome has been calculated, if the syndrome is all 0, The resultant corresponding Ax is indexed and output by unit 52. Transmission link The superchannel step indicated by the dotted line in the link is related to the description of other embodiments. will be further explained.

Figure 2 shows the direct method of the present invention in which the α operator is an exclusive 08% logical operation. A conceptual flowchart is shown.

Although this algorithm is described in conjunction with the direct method, the steps shown in Figure 2A Steps also work against the decomposition method.

The direct method differs from the decomposition method in the following points. In other words, on the receiving side, the decoding process performs an error check for each component of the attribute data class when combined with D' bass tong. The decomposition method requires a qubit calculation, whereas the decomposition method requires an error due to the attribute data. Check bits may be indexed.

The direct method on the transmission side is the selected component of the class of attribute data et1fc element. In an example of a shortened linear error detection code, the main data is made open. starts by joining to the unused most significant bit position in the The bit can be placed in the least significant bit position as long as the same thing is done at the receiving end. good). The resulting bit string is shown at 54 in FIG. 2A.

String 54 is used as an input string for encoder 56.

Encoder 56 may be any encoder that generates a linear error detection code. good In a preferred embodiment, the I-da 56ij inputs directly from the bit string 54. Calculate error check bit P. This operation is an error check for main data D. (Picture) Separate calculations of Pd and selected classes of attribute data tll components. This is equivalent to the embodiment in which separate calculations for the components are performed. unintentionally Error correction for attribute data (Pax) is indicated by Fiα operator 76. The encoder 56 performs a bit-by-bit exclusive OR operation. Error correction for data is encoded as Pd. obvious to a person skilled in the art As shown above, the α operator 76 has three forms defined as described above regarding the decomposition method. It may be any of the α operators, and the changes on the receiving side are 2B and 20. A detailed description will be given in connection with the description of the figures. At this time, the direct method determines which form of the α operator is Depending on the chosen method of disassembly, a modified embodiment similar to that described above may be used. Ru.

In other embodiments, encoder 56ij may be two separate encoders, one One encoder calculates Fax and the other encoder calculates Pd. two The output from the encoder is combined with the two data outputs of these two encoders f c A mathematical logic unit of any form with two data inputs or can be combined using logical operations. Then, the mathematical logic unit is P Perform addition, subtraction, multiplication, or division between d and Fax bits or Pd Exclusive OR operation, AND operation, and OR operation are performed between and Pa. mathematical or # Each of these different forms of logical operations requires a modified error correction pitch. ) give different bit patterns to P. d, Ax and D to P on the receiving side A decoding operation is performed to calculate “beep”. This decoding operation also There is no difference between D and 07, and the bit strings P and P'' are bit-to-bit. can be any sequence of mathematical and logical operations as long as they are equal on the basis of . The preferred embodiment uses exclusive OR logic operations. if it has one or more Since it is constructed with other OR gates, it is easy to use and can express Pd or Paxtl. For this, we do not change the number of bits of P compared to the number of bits required for Encoding and decoding operations in some of the other possible embodiments are particularly relevant to mathematical operations. This is because the number of bits for the corresponding bit changes.

The embodiment of FIG. 2A is a trial and error embodiment. This has been evaluated multiple times. one evaluation for each component of the attribute data class. Necessary means that it is necessary until the correct attribute data is found. do. This data evaluation process is performed for each Pa in the class Pat...Pan. We first calculate multiple P'' syndromes with Pd'X-0RPa'''C for It consists of things. Then, each pre-syndrome is A match with P/ identifies Ax.

The preferred embodiment shown in FIG. 2A is such that the exclusive OR operation is one or more is simply constructed with a logical OR gate and it represents Pd or Fax. Binary number to keep the number of bits of P unchanged compared to the number of bits needed We use an exclusive OR logic operation for the alpha operator of the system.

The bit string 64 may also have an error of km introduced during the transmission process. may not have been introduced. If super channel is used In particular, if the number of transmission errors is incorrect in the error pressure code used in the super channel. Unless the difference detection and correction range is exceeded, there will probably be no error. If the transmission If there are errors in string 64 as a result, the invention will not work properly.

The first step in calculating the collar number pre-syndrome is to connect the bit string 64. In order to match, each component of the attribute data class M...An is supplied.

The attribute data supply step 66 supplies each component of the class of attribute data components. This function is performed by supplying the element to the mother 1s6B. As mentioned above, the attribute data The data class components may be supplied in serial or parallel format, and the operator The coupling device denoted by 70 handles data serially or in parallel. It's okay. The attribute data on the bus 68 is opened by the received main data D'. is provided to be connected to the unused most significant bit position. this is is done by performing an exclusive OR operation as shown at 70, but any other result This can be done in a combined operation. The function of operator 70 is attribute data A and D'.

The purpose is to combine the P' bit strings. The resulting output string is shown at 72. be done.

Each pre-syndrome is the result of trial and error when α is an exclusive OR logical operation. In the embodiment, it is calculated as follows. configured in encoder 56 The same α operator and error correction code as n, and also the one expressed by operator 74 The encoder 74 that configures the component of the class of attribute data At...An and the combined string D′ for each input string such as P′. The receiving element is used as a ring to calculate multiple error check patterns P''. used in

After the modified membrane difference Sakaki Masapi) P is generated, they are the main data at the least significant end. Can be tied to a string.

Then, the main data D and the changed error correction pitch P are 60 and 62 in FIG. 2A. Transmitted and /''! or recorded as indicated by n. Certain embodiments are described below. has a separate error correction pin to ensure the integrity of this transfer. these good The so-called super channel will be described later.

At the receiving end, the received raw data D′ and the received modified error correction bits P ' forms a bit string denoted by 64. Bit string 64 is a transmission process. There may be some errors in the results of the process. Attribute data supply step 66 is received. Connection to the unused most significant bit position owned by main data D' supply each component of the class of attribute data components (vector 68). This leads to an exclusive OR logic step shown at 70 as one input string of D' and P' pits) for IJ tongue and Bit positions for D' and P' combined string 64 as other input strings 70 associated with attribute data A combined with a string of 0s that occupies This is done by performing an exclusive OR operation.

The attribute data supply step supplies all error correction bits for attribute data components. The attribute data supply step 56 supplies the attribute data component itself to the The above description for the configuration of error correction bit supplying steps 28 and 42 is the same, except that It can be constructed from any of the following circuits. For example, if look If the uptable is used to configure the attribute data supply step 66 For example, the contents of the look-up table may contain attribute data instead of the corresponding error check bit. On the data component n itself becomes a bit string. If the multiplexer is circuit 6 6 if used for each component of the Fim data class. each input has one input for the attribute data component of that class. It is converted into a single bit pattern and a node. The equipment for configuring the direct method The architecture for the location can be either series or parallel. The processing for performing calculations on the communication side and the circuitry for structuring the processing are sophisticated. It differs from the serial architecture in that it exhibits simultaneity. serial architecture Calculations for each attribute data component are performed serially for the . In parallel architectures, one for each attribute data component. In a parallel path where there are paths, one syndrome simultaneously is calculated for each component of the In serial architecture, If only one path is used, then this single path is the used to calculate the syndrome for the first component, then it is used again to compute the syndrome for the second component of the gender data class. used.

In the method of the present invention, the syndrome of the number of furrows is calculated simultaneously or one at a time. Representing the method steps to calculate each syndrome whether or not . Each syndrome is calculated as follows. In a preferred embodiment, Encoder 74, similar to encoder 56, receives the combined string as an input string. Error correction bit pattern using one of the components of the class of the attribute data and is used at the receiving end to calculate the pitch P/.

In other embodiments, the encoder 74 is configured such that A is Ax used on the transmitting side. and the selected value used to generate P# equal to P when D=D' May be any circuitry necessary to perform mathematical and/or logical operations. stomach. Encoder 74 need not be identical in structure to encoder 56 and The same sequence of operations performed by reader 56 may not be performed.

The only condition is that p=p'' for D=d' and A=Ax as mentioned above. .

In a preferred embodiment, an exclusive OR is used for encoding and decoding and Coder 56 is identical to encoder 74. In this example, P”error correction The string of bits is such that the D' string passes through encoder 74 alone, i.e. If there is no attribute data to be combined with the attribute, then the error check bit of the result Errors resulting from passing one component of a data class through encoder 74 alone. The error correction string that would occur if encoded with the differential pressure bit Pa equal. The encoding process performed by encoder 74 is performed by encoder 56. It must be the same as the encoding process performed. That is, if the exclusive OR operation Some other mathematical operations different from Pa error correction bits are performed in encoder 56. If used to encode Pd error correction bits, then the same mathematical and/or logical processing must be used by encoder 74. child The exclusive OR logic operation of is indicated by 76 at the transmitter as it is the preferred embodiment. 78 on the receiving side.

If there are no errors during transmission, D' will be equal to D bit-for-bit, such that , then Pd2 is bit-for-bit equal to Pd at the transmitter and P'' is becomes equal to P.

The syndrome calculations, indicated by block 80 in FIG. The error correction bit P′ and the error correction bit P” generated by the encoder 74 are It is an exclusive OR logical operation between. If there was no error during transmission, P/ is P and PViP'. Therefore, P' is not equal to P"? The syndrome consisting of the result of the exclusive OR logical operation between P' and P" is all 0. It becomes a string. However, this means that the P” error correction bit is coded at the receiving end. The encoded attribute data A is encoded into an error correction signal P by an encoder 56. This is true only when the same attribute data A is used.

The purpose of the receiving circuits in Figures 2A and 1B is to create a string of all zeros. Syntax for each component of the attribute data class until the drome is found. is to calculate the drome. Attribute data that results in a syndrome of all 0s on the receiving side The data is the same attribute data encoded at the sender. Therefore, the attribute data is sent Even if not, appropriate attribute data can be output by the receiving device. all Detect the time when the syndrome of 0 occurs and assign it to the attribute component that caused it. These final processing steps, all of which correlate the syndromes of D, are shown in Figure 1. Configure in steps 82 and 84 of FIG. 2 which are identical to steps 50 and 52. be done.

Correct operation of the attribute data recovery method of the present invention is based on whether D' and P' are correctly recovered. It is based on the assumption that D and P are equal. If the error is either D or FiP If it occurs during any transmission, the all-zero syndrome will occur in the appropriate attribute data class. It does not even occur when a component is selected for decoding at the receiver. Therefore, the book The invention is a system in which the special case impossibility of passing attribute data is not important. Most effective in stems. Generally, color television digital transmission and Or in systems such as digital signal processing systems, from one scanning line to the next. There is a large amount of redundancy of data into the scan lines. In such a system, The present invention works extremely well because of this redundancy and further improves reliability. There is no need to take steps.

However, in systems where transmission errors are relevant, , another embodiment of the present invention eliminates the difficulty caused by such errors. It can be used to゛Basically, such an embodiment line of the present invention transmits and receives Does it have its own error correction circuit that works independently of the encoder on the side? The received data must undergo transmission or recording processing before being used by the receiving circuit. It includes a transmission or recording circuit that detects and corrects errors that occur during the transmission. This way The properties of this embodiment of the ``super channel'' are conceptually illustrated by the dotted lines in Figure 1. There is. The term "superchannel" refers to channels with separate and independent error correction means. will be used below to refer to transmission and/or recording circuitry. like this A superchannel embodiment stores the data to be transmitted in the PI indicated at 88. Use encoder 86 to encode each set of check bits represented. do. The input data to the encoder 86 is the main data D and the changed error correction. This is a string emitted from bit P. Encoder 86 can be any linear error correction code. Structure the code.

This code is the same as that constructed by encoders 24 and 38 in FIG. They may or may not be the same. Super channel error correction bit P9 is transmitted and/or recorded together with the main data D and the modified error correction signal P. Ru. On the receiving side of the superchannel circuit, the error correction PI is denoted by 90. It is received as follows and takes the form p*'yt. Super channel circuit decoder 9 2 has as its input string P*' error correction bit, received main data D' and and the received modified error correction bit P'. Then, P*′ error correction bit An error within the error detection capability of the P*' error correction bit is detected and Errors within the correct ability are corrected. The output from decoder 92 is the stream shown in FIG. 35. The error during transmission processing is within the correctable range of error correction bit P*' As long as there is, error string 35 will fall without error.

Figure 2A is the same in the same manner and has the same function as the superchannel circuit described in Figure 1A. The super channel circuit that performs all the steps is indicated by a dotted line. Super channel in Figure 2A The method used in the circuit is also the same as that used in Figure 1A. be.

Figure 2B shows a case where the inverse α is not defined, i.e., not specified or singular. An example of one trial and error format for the general α implementation is shown. day Only the data evaluation or decoding function is shown in Figure 2B, which is shown in Figure 2A. All other steps are the same. Figure 2B data The data evaluation process uses each of the constituent elements of Pd2 and class At...An. Contains a trial and error decoding operation to calculate the P” field. Drome P "The first step in the calculation process is the attribute data class kt...A Attribute data for each component of n or specific states of Pd' and P' and each member of the fuzzy subset of the class.

The attribute data class component thus supplied is the received data string 6 4 (not shown) and is coupled by a functional unit or unit 70 of FIG. 2A. It will be done. This process includes an attribute data supply step 66, a bus line 68 and the resulting stream. 72. Attribute data supply step can be serial or parallel or any arbitrary arc between these two limits mentioned above. It can be a architecture. An even bigger change is lookup table, multiplayer each bit or bit of a component of a class of attribute data. is a symbol pattern and an attribute data such as a parallel bus bar that is made into a node. Exists for the source of the data component. If the multiplexer is for circuit 66 one input for each component of the attribute data class. each input contains one bit parameter of the attribute data component of that class. Turn and node wear.

The plurality of bit patterns 72 are arranged such that a plurality of glycine syndromes P"<< occur. is input to encoder 74. Encoder 74 is the same as encoder 56 in the transmitter Construct the α operator. Therefore, each pre-syndrome P is expressed as α operator. This results in one of the components of the class Pat acting on the Pd' field.

The pre-syndrome between Fax and Pd' will be equal to P'. Therefore, the next step By testing all pre-syndromes to distinguish them from P' fields, Chiru. This feature has one pre-syndrome and P′ field is represented by a discriminative operator unit 75 which generates an undrom. Next, Drome indicates that P' is equal to P'', thereby identifying Fax and Ax. tested to determine the difference. Fax identification is the corresponding Ax field is output to a functional unit 84 which outputs a code.

Figure 2C shows the inverse α operation where the α operator is chosen and defined or singular. The receiver circuitry may differ from that shown in FIG. 2A for embodiments with It shows what is happening. For the inverse α, which is finite and singular, The encoding or data evaluation operation is simply by applying an inverse α operation between Pd' and 27. , the identity of PaX is given directly, and it is therefore difficult to directly identify Ax. This results in one calculation without repeating rows and errors. The inverse α operation is defined and differs by % In such embodiments, encoder 65 encodes the bit string via data path 67. The D' field is received by the encoder 56 on the transmission side (not shown). Error check bit string Pd' using the same error correction code as used. 2 occurs. This Pd' bit string is then input to the inverse α operator 69. It will be done. It also receives the P' bit string from bit string 64.

The inverse α operator 69 uses Fax to output the corresponding attribute data Ax. outputs the fax bit string sent via data path 71 to power circuit 84. Ru.

Embodiments of the invention may be implemented in a series or parallel architecture, or in combination with these two architectures. Complete configuration of data processing and data evaluation by introducing technology is possible. To determine the identification of Fax and Ax, class M...Kalpa or The process of repeating trials and errors using the components of Pat...Pan is This is data evaluation processing. As defined in any of the embodiments presented herein. of these embodiments at the sender or receiver than performing any of the functions provided. take an individual bit or symbol in any of the functional units of any Processing that deals with data is referred to as data handling or processing. Embodiments of the invention are serial or a parallel architecture or any combination of these two limitations. Data handling and data evaluation can be structured in any of the following architectures: can. The degree of parallelism from a single bit to a group of multi-bit words depends on the architecture. The degree of parallelism can be selected for different textures within the data transmission system. can be made different depending on the position. The preferable amount of parallelization also depends on the complexity of the circuit. It depends on many factors such as complexity, data processing time, cost, etc. different or the same architecture for data handling and data evaluation in any embodiment. You can also combine them. For example, distribution of data by multiple parallel paths and Serial architecture data handling units in each data path provide Ax identification. Performing data evaluation to determine the difference is only one of many possible permutations. Only. Parallel data handling architecture and serial data evaluation architecture A combination with is also possible. A parallel data evaluation architecture combines this multiple procedures for evaluating each data path, if included in Data is needed. Each of these can be used in series or parallel architectures. You can choose either one. Of course, data evaluation is based on a trial-and-error type of practical example. only necessary. However, the implementation requirements that do not use trial and error evaluation are Similarly, functional units of intention are defined by specific functions that must be performed to deceive. serial or parallel architectures for handling the data required. It may be either cha. Series architecture trials and error separation tests For the embodiment, testing for each attribute data component is performed serially. In an example of trial and error forms in parallel architectures, syndrome The system uses parallel communication with one path for each attribute data component. simultaneously for each component of the attribute data class.

In a serial architecture, a serial path is the first component of an attribute data class. is used to calculate the syndrome for the attribute data class, and then When used to recalculate the syndrome for the components of 2, only One passage can be used.

Figure 3A shows how to decompose Figure 1A such that the α operator is an exclusive OR logical operation. A serial data evaluation architecture for one embodiment of an apparatus for configuring is shown. It is. The transmit side or transmit side circuitry is shown in the upper half of the figure. coupler 94 is a zero step from the user to the main data stream arriving at the combiner input on line 96. Add tring. Combiner 94 combines unused bit positions to create one word. You can add enough leading zeros to the main data string to satisfy It can be of any arbitrary design. The design in Figure 3A constitutes the method in Figure 1A. This is only one of many aspects used to structure this method. The specific configuration of the circuitry used is not important to the invention. Those skilled in the art will understand that FIG. We acknowledge the many modifications that can be made to provide alternative embodiments that perform the same function as the circuit. There are many things that can happen. When the various steps of the disassembly method are configured by the user Figure 3A. It is only necessary that the function constituted by the circuit of One important thing. Some but not all of these possible alternative embodiments None are described herein.

The number of main data bits is the number of input bits for each input to the system's encoder) Since it is known for the coupler 94, simply arriving at line 96 The main data bits are counted and the most significant main data bit reaches the combiner 94. Later, the bit positions (or time slots) on main data input line 98 are filled with zeros. However, a circuit that outputs the signal to line 98 may also be used. into encoder 24 The combined bit string as input is shown at 100.

The structure of encoder 24 is well known to those skilled in the art and is suitable for organizing the method of FIG. 1A. overall to the specific error correction code selected by the user for use on Dependent. Accepts input data in either serial or parallel format Structures for encoders that can be used are known. In the embodiment of Figure 3A , encoder 24 accepts the main data on line 98 in serial format; Translate the main data into the corresponding main data error check pin) Pd. Then this are output in serial format on line 102.

These main data error check bits are the attribute data and edges selected by the user. must be encoded with error check bits corresponding to Fax. Ax is selected by the user as an attribute of the main data, which indicates that it is associated with the main data must be encoded for transmission along with the data. Ax is attribute data containing Ax. The data value AI-An is selected from two values.

The error check bit Fax for the selected attribute data Ax is the error check bit Fax. is supplied by a cut supply circuit 28. This error check bit supply circuit 28 It can take many forms. In a preferred embodiment, lookup table 1 04 is the error check pin for each component of the class of attribute data) Used to store Pa. These bits Pa are used to calculate the Pd bits. using the same or different error correction code from that used for This is the result of the calculation. Typically, these error check pins) Pa are read-only. stored in memory. To access a specific set of error check bits above: , addresses are provided to the lookup table on bus 106. This address is , error check bits for one specific component of the class of attribute data are recorded. corresponds to the stored position. When this address is received, lookup table 10 4 is the corresponding error check bit F for the selected attribute data of bus bar 108; Output ax. The address on bus 106 may be provided in any one of a number of ways. can be paid. In the embodiment shown in FIG. 0 has an output coupled to a busbar 106 and a plurality of inputs. Each input is Address of the error check bit for a specific one of the components of the attribute data class is combined into a hardware-enabled bit pattern for the User-defined controls The selection signal at bus 110 from logic 112 is applied to output bus 106 at any particular time. Controls the selection by multiplexer 110 of a particular one of its inputs coupled to Ru.

In another embodiment, the error check bit supply port @28 is simply a multiplexer. 110. In this alternative embodiment, the attribute data Each input that corresponds to one component of the attribute data class Specific error check bits corresponding to the components) hardware. At this time, the selection signal 110 is the attribute data class error check. selects of the block bit patterns are coupled to bus 106. Ru.

Bus bar 106 is then coupled to alpha operator circuit 114 . The selected α operator is It may be any α operator, and the receiving circuitry will respond to the selected α operator. good In a preferred embodiment, the α operator with is an exclusive-OR circuit.

In another embodiment, the error check bit supply circuit 28 is a lookup table. 104, such as encoder 24. In this example , the multiplexer 110 inputs the actual bit pattern of the attribute data class component. has an input connected to the The selection signal 110 is then activated by bus 106. Select one attribute data component for attachment to the coder's input. Then, The encoder generates the corresponding error check bit for the selected attribute data component. Fax is calculated and these error check bits are input to the exclusive OR circuit 114. and is applied to the bus bar 108.

Regardless of the particular configuration of error check bit circuit 28, α operator 114 Error check pin for selected components of data class) with Fax Error check for main data Pd is encoded. This encoding is Performs a bit-to-bit exclusive OR logical operation between the This is done in a preferred embodiment. The result of this logical operation is the bus 116. becomes the changed error check bit P.

In another embodiment, other devices for performing the α operator function replace circuit 114. and used. In such embodiments, circuit 114 can be configured to Each of the main data error check bits using the attribute data error check bits a mathematical expression that is programmed or controlled to perform the same operation on a set of Chill with logic unit or other logic.

These modified error check bits are combined with the main data string D for transmission. It must be. This is the function of combiner 118. This circuit 118 is The output bit string at bus 102 is matched at the trailing or least significant bit position. The corresponding error check bit Pd consists of a combined SL-IJ ring of D followed by a corresponding error check bit Pd. Ru. If combiner 118 is used, in the most significant unused bit position The combined string of main data D, preceded by a string of 0s, is connected to bus 120. input into the device. For a series architecture, combiner 118 connects bus 120 The modified error check is the same as for the actual number of bits of the string you enter in Combiner 94 and They are of the same design. Combiner 118 connects its output bus 122 to the signal at bus 116. It works to output the bit string P first. Changed error check bit When the numbers P are output to bus 122, they are counted. Count error check When a certain number of check bits is reached, the combiner switches state. This status The switch connects the input bus 116 to the input bus 122 such that the output bus 116 is connected to the output bus 122. line 120 is connected to output bus 122; The string that immediately follows the output of the modified error check bit string P is Output on line 120.

Only the main data D and the changed error check pins P are transmitted over the transmission link 30. sent. An optional bit separator 124 determines the stream to be transmitted on bus 126. to separate the zeros from the bit string at bus 122 to output the ring. to work. This bit separator 124 separates the bits of the input string at bus 122 from A number of bits equal to the number of bits in the D and P fields are counted and passed through the bit separator. A function that interrupts the transmission through the bit separator from bus 122 to bus 126 after passing through the bit separator. It can be of any design. As recognized by those skilled in the art, bus bar 12 6 to demarcate or otherwise signal the beginning and end of the string to be transmitted. Some header or start bit and stop bit information is required to It's okay. Additionally, the start and stop bits or delimiting characters are also each may be provided to signal the start and end of the main data string. child Whether these delimiting characters or bits are used depends on the user's application. , their use is not critical to the invention. Furthermore, the bit separator 124 The use is not critical to the invention.

The main data D by link 30 and the modified error check pin) are preceded by P. Transmission of zeros causes no interruption of system operation. However, it must be transmitted Separating the leading zeros from the bit data means that the transmission of these bits is unnecessary across the band. This is preferable because it contributes to

On the receiving side, the received main data D′ and the received changed error check Bit P' is input to combiner 128 at mother@130. Combiner 128 is also a busbar. Receives string 00 at 150 and opens with shortened main data D' It works by reinserting 0s in front of unused bits 1 that are set to 1. this is While this may be preferable for certain structures of encoders, certain Not necessary for the embodiment. Adding leading zeros is done by encoder 24 and Encoders such as encoder 38 are consistent with the word length of the system in which they are used. Generally designed in the prior art to accept input strings of equal fixed length. required in embodiments with a certain structure of encoder to be measured. . If the input codeword is shorter than or equal to this fixed length, the unused bit positions are must be tied to a logic zero to prevent unknown voltages on floating inputs. Must be. Such a floating input is a calculated error check bit makes it unreliable. If bit separator 124 is used on the transmission side, If not, the combiner can be omitted.

The output bit string from combiner 128 is shown at 134. Street with separating the 0-D' string from the P' string and placing it on a different busbar. A bit separator 140 outputs each string. 0-D'stri The input signal is input to encoder 38. Encoder 3 is encoder 2 on the transmission side It is equivalent to constructing the same error correction code as in 4 and calculating Pd' from D'. performs the same function. If there is no error when transmitting and/or recording main data D Alternatively, if a superchannel is used for transmission link 32, D' becomes D is equal to Pd' and Pd' is equal to Pd.

EXCLUSIVE OR AS THE α OPERATORIn the embodiment of FIG. 3A, operator 135 is This is an exclusive OR circuit that generates the partial syndrome P'x -0RPd' in 2. .

In the preferred embodiment, the partial syndrome output by exclusive OR circuit 135 The system is an error check bitstream corresponding to the attribute data class component AI-An. It must undergo an exclusive OR operation with each of the rings Pa1-Pan.

Bit strings P', Pd' and Pal...Pan are exclusively manipulated The order is not important to the invention, and in some embodiments the order (P'x-OR Pd')x-ORPa1.-Pan may be switched to other permutations.

To achieve the exclusive OR operation in the order shown in FIG. 1A, exclusive OR circuit 1 The partial syndrome at the output bus 142 from 35 Coupled to 0 input. The exclusive OR circuit 144 outputs the error check bit string P It has another input bus 147 that supports the a1-Pan strip. error check This stream of check bit strings is supplied by the error check bit supply circuit 42. will be supplied. As in the case of the error check bit transmitting circuit 28 on the transmitting side, the receiving The error check bit 42 on the transmission side can be used in any one of a number of different ways. It may be configured. In a preferred embodiment, the error check bit ROM 146 is Error check bit string P corresponding to each component of the attribute data class a1 - Used to store Pan. Address for ROM 146 is provided at bus 150 from the output of multiplexer 148. Multiplexer 1 48 specifies that each input identifies a component of the attribute data class to a specific address. It has multiple inputs that can be converted into software. Selection at bus line 152 The signal is sequentially passed through negative multiplexer 148 for coupling to its output bus 150. Let them choose. This result is the address of error check bit supply ROM 146. This results in a stream of address strings on bus 150 for the respond port.

ROM 146 (and 104) as recognized by those skilled in the art. Must have other control signals so that it can reach each address string Correctly access the corresponding data. Design for such circuits is within the skill of those skilled in the art. It will be obvious for.

The selection signal at bus 152 can be generated in any one of a number of different ways. It's okay. The actual manner in which it is generated is not important to the invention. multi The selection of sequentially coupling each of its inputs to its output by a plexer 148 One way to generate the select signal is by using a count input driven by clock 156. The counter 154 is to use a counter 154 having the following values. The counter 154 has clock 1 56, each output outputs a stream of binary clock pulses from bus 1520. The activation of each of the plurality of outputs consisting of one line is converted into sequential activation.

When the respective output line of counter 154 is activated, the multiplexer selects the corresponding one of its inputs for coupling to the output bus 150 of . clock The 1560 frequency is determined by the 2M 146 accessing the corresponding error check bit. 15 for a period of time sufficient to enable them to be output to the bus 147. 2 so that each address is output to the output bus 150 according to the selection signal at step 2. Must be set.

As will be recognized by those skilled in the art, the error check pin (Pa1-Pan) There are many other aspects. One such aspect is that the master can be configured without using ROM 146. The inputs of the multiplexer 148 are made into hardware, and each input has an attribute data structure. The node corresponding to the error check bit of one particular class of components. The bus bar 150 is to be connected to the airized bit nozzle (turn). , which is then connected directly to the input of an exclusive-OR or other decoupling circuit 144.

This method is faster than using the error check bit supply ROM 146. , is a preferred embodiment of the error check bit supply circuit 42.

Another way to configure the circuit 42 is to configure the encoder 24 and the circuit 42 without using the ROM 146. and 38. At this time, multiplexer 1 48 inputs to the bit patterns of the individual components of the attribute data class themselves. Becomes hardware. At this time, the selection signal 152c is that of the attribute data class. such that each individual component is input to this encoder via busbar 150. do. The encoder assigns an attribute to each attribute data class component that reaches its input. The corresponding error check bit is calculated and the error check bit is added to the bus 147. Output the string Pa1-Pan.

Error check bit string Pa1-Pan stream is supplied to bus 146 Regardless of how it is implemented, an exclusive OR or other combination circuit 144 is always functions in the same manner. The purpose of exclusive OR circuit 144 is to determine which of the attribute data classes whether the component is encoded into a modified error check bit P at the sender. to generate the final syndrome 8l-8n used to determine Ru.

Exclusive OR circuit 144 outputs a stream of syndromes on bus 149. Shin Each of the dromes 8l-8n has an error check bit string Pa1-Pa Bit-by-bit exclusive OR between one of n and the partial syndrome at bus 142 Calculated by performing arithmetic operations. As is clear to those skilled in the art, busbar 1 The number of bits in the partial syndrome at 42 is a bit-by-bit exclusive OR operation. Because the calculation was used to generate the partial syndrome and the exclusive OR logical operation Since there is no carry in the calculation, the bits of bit strings Pd' and P' equal to the number of points. Furthermore, that of the error check bit string Pal-Pan The number of each bit is the number of partial syndrome error check bits of the bus 142. is also equal to Each syndrome is then a bit of a partial syndrome. The number of bits must correspond to the number of bits. At bus 149, which is also 0, Error check pin only for syndromes in the syndrome stream) Fax The corresponding syndrome. The reason for this is (P'x-ORPd')x- Assuming that ORPax has no error during transmission, P'x-OR( This is because it is equal to Pd'x-ORPax). If there is an error, P' ,=P and P'x-OR, P=o.

The fax sends selected constituent elements of the attribute data class encoded by the sending circuit. Since it is equal to the prime Ax, the identity of Ax will be given.

In the stream of syndromes at bus 149, all zero syndromes are detected. is coupled to a zero detector 50 which causes the signal at bus 151 to change state when . This 0 detection circuit 50 is simply connected to the output of the serial input parallel output shift register. It can be a connected N0R (or NAND) gate. This shift register is Viratra serial format of each syndrome until all bits are reached When all bits arrive, the syndrome is input to the input of the NOR gate. Outputs all bits of the system simultaneously in parallel format. If the NOR gate If the inputs were all 0's, the NOR gate output would change state.

Output circuit 155 then outputs the selected attribute when a change of state on bus 151 occurs. Outputs the gender data component Ax.

The output circuit 1550 function may be implemented in any of a number of different designs apparent to those skilled in the art. It may be done by one of the following.

Output circuit 155 has as an input a selection circuit at bus 152, thereby The components of the gender data class are input to their error channels which are fed to the exclusive OR circuit 144. It keeps track of such sequences that have check bits. Know this information By doing so, the output circuit can identify the attribute data class to which each syndrome corresponds. The sequence of syndrome 81-Sn that reaches bus line 149 with the components of It becomes possible to know. The output circuit 155 has a ROM corresponding to this output circuit. Difference check bits and attribute data component bit patterns that differ from themselves A looka similar in design to the error check bit supply circuit 42 except that it includes can be a top table. The output of the bus 151 in the 0 detection circuit is all The output circuit 155 is activated only by the selection signal corresponding to the syndrome that was 0. A selection signal at bus 152 to restore the attribute data component from its ROM. can be used to gate the output circuit 155. Output circuit 155 A similar change in design can be made as described above in connection with the error check bit supply circuit 42. It can be done.

In Figure 3B, the α operator is any general α operator and is undefined. Small implementations are non-specific, such as when a decomposition method with serial data evaluation is used. An example is shown. In this example, the Pd' string at busbar 136 is It is given to the child circuit 157, which is another input, and class Pa1... at the bus bar 147. - Receive a stream of error check bits Pa of Pan. α operator is discriminative operation Outputs a series of P'' fields at bus 139 that are coupled to child 141. This identification The operator also receives as input via bus 138 the P' bit string, and and whether the two bit strings are the same by comparing between each 21 decide whether If they are the same, the decoded fax identity information The data is sent to the output circuit 154 via the bus 143 to output the corresponding attribute data. Make Ax output.

FIG. 3C shows an example of a decomposition method in which the inverse α is defined and singular, and Changes to the receiver circuitry from that shown in FIG. 3A are shown. this In the example, the Pd' at busbar 136 and the y field at busbar 138 are inverse α is given to operator 159. The output of the inverse α operator circuit 159 is Fa at the mother M154. It becomes x. This string is applied to an output circuit 155, which outputs the corresponding decode the string into gender data Ax.

Figure 4A shows a parallel data evaluation architecture for the α operator as an exclusive OR logic operation. An example of the method that has come to constitute the decomposition method of the present invention using the architecture is as follows. It is shown. The embodiment of FIG. 4A is a preferred apparatus for implementing the preferred method of the present invention. . The circuitry on the transmitting side may be the same as in the embodiment shown in Figure 3A. a Alternatively, it may perform the same functions as the device in Figure 3A, but perform them in parallel. Do it in such a manner. Any number system and any error correction code may be used. and any α operator may be selected. The circuit on the receiving side of this example is As in the example of Figure 3A, the inverse α operator is defined or singular. must be selected according to whether

Similar notes are given to the receiver parallel syndrome generator circuit of FIG. That is, the first In converting the discrimination test circuit of the embodiment shown in FIG. 3A to the parallel format of the embodiment shown in FIG. , the circuitry preceding and following the identification test circuitry for the embodiment shown in FIG. 3A. or may perform the same function as the embodiment of FIG. 3A. may be configured, but in a parallel manner. Furthermore, the encoder of circuit 163 generates Pd using the same error correction code used to generate Pd at the transmitter. ' and processes Pd' with y so that it becomes Fax. Fax is output circuit 1 66 to the bus 164 and its corresponding attribute data in any known manner. Fax is converted.

For a trial and error example using an exclusive OR logical operation for the α operator, The decoder circuit 163 has a partial syndrome on the bus 164 consisting of P'5-ORPd'. generates a system.

This partial syndrome generated on bus 164 is generated by a plurality of x-OR circuits 168, 169, 170, 171, etc., each of class Pa1...Pan Can be combined with both components at the same time. Each component of the above class is paired with one input of a corresponding exclusive-OR (X-OR) operator circuit.

The outputs of the x-0 circuits 168-171 are all 0 due to a certain syndrome. This is a syndrome that correctively identifies the attribute data encoded on the transmitting side.

In more detail, the trial and For the error and error example, a single partial syndrome is shown at busbar 164 in FIG. 4A. It is output and coupled to the inputs of a plurality of exclusive OR circuits 16B-171. attribute data Exclusive OR circuits 168-171 for each component of the class There is one exclusive OR circuit. corresponding to the individual components of the attribute data class. Error check bits are supplied to individual buses 175, 15, 177 and 179. , each bus bar is coupled to a respective input of an exclusive OR circuit 16B-171. Ru. In other words, each exclusive OR circuit 168-171 is a partial syndrome receive a message. Each exclusive OR circuit 168-171 generates a single syndrome. and each syndrome corresponds to one component of the attribute data class. Ru. to the selected component Ax of the attribute data class encoded by the sender. Only the corresponding syndrome Sx becomes all 0.

Each syndrome in the parallel format is determined by the zero detection circuits 159-162. This signal is supplied to the input of a zero detection circuit.

Each zero detect circuit has an output line shown as lines 168-171, respectively. which changes state when the syndrome at the input consists of all 0 bits. Support signals that change. These 2-in 1/18-171 outputs are multi-line selection busbars. 175 and coupled to the select port of multiplexer 178. This circle The multiplexer serves the purpose of output circuit 1540 in Figure 3A.

Multiplexer 178 allows each input to have one particular configuration of attribute data classes. It has multiple inputs that can be assigned to an element. Each input is an attribute The bit patterns representing the corresponding components of the data class are It will be done. The selection signal on line 175 is the input corresponding to the syndrome that was all zeros. Such that only the force is selected for output at output bus 180.

Figure 4B is an example of a decomposition method in which inverse α is not determined or is not singular. FIG. 4A shows changes in the receiver circuit from that shown in FIG. In this example ・The receiving side partial syndrome generation circuit 163 generates Pd on the transmitting side. Pd' is generated using the same error correction code that was used. , Pd and P ' are output to bus lines 180 and 182, respectively, at this time. Pd' is class Each component Pa1...Pan and a plurality of α operator circuits 184, 186 ... are combined simultaneously. This result is obtained by multiple identification circuits 188, 190, . . . are compared simultaneously with P'. The output of these identification circuits is 2s Pa1 . . . Correctly identify which one of the Pans is a Fax. This data is F It is sent via bus 192 to an output circuit 194 that outputs attribute data Ax corresponding to ax. Ru.

Figure 4C shows an example of the decomposition method in which the inverse α operator is defined and is singular. Modifications to the receiver circuit shown in FIG. 4A are shown. In this example In this case, the receiving side partial syndrome generation circuit 163 is the same as that used on the transmitting side. Pd' is generated from the received main data D' using an error correction code. Bus line 180 and The Pd' field and y field in 182 and 182 respectively calculate the Fax. It is applied to the inverse α operator 195 and outputs it to the bus line 195. The output circuit 166 is Receives a fax and outputs the corresponding Ax field.

Figure 5A shows whether α is not defined, including the case where it is an exclusive OR logical operation. or non-singular α for the device configuring the direct method of the present invention. The evaluation architecture is shown. In the direct method, coupler 200 connects bus 2 02 serial bitstream main data D, Dt-@1lli2r)4 The bitstream is combined with selected attribute data that differs from the bitstream. selected genus The data bitstream can take many different forms as described above in connection with Figure 3. It may be provided in any one of the following manners, and the manner in which it is provided is not relevant to the present invention. is not important. In Figure 5, each input of the multiplexer is input that is hardwired into a bit pattern of one of the components of the data class A multiplexer method is selected that has . User-defined control logic 206 of the attribute data class so as to define a certain attribute of the main data D that arrives at that time. Allow selection of desired components. The output of the combiner 200 is based on the main data D. The selected attributes are bound to unused bit positions that are designated as ovens. This is the string 208 that was created.

Encoder 56 receives the serial pit stream 208 and converts it to the user's selections. Translated into error check bits P modified according to the error correction code. Preferred implementation Although in the example the logical operation exclusive 0 is used for the α operator.

Any other α operator may be used as well. Figure 5 is marked by the Greek letter α. represents the α operation used for encoding. As will be clear to those skilled in the art, In the preferred embodiment, coder 56 simply connects string 208 to its corresponding Revised error check) PK@translated by that person) IJ song 0 Works about 8.

That is, the encoder 56 performs an error check bit on the attribute data Ax and the main data D. Rather than computing the cuts individually, combine them using an exclusive OR logic operation. However However, in other embodiments, this method of generating modified error check bits may be methods can be used. Additionally, other mathematics such as addition or logical AND operations If a target or logical operation is used, the encoder 56 has two prior art The format of the encoder is set to the selected attribute data component and the king data. Generate separate check bits Px and Pd respectively (using the α operator followed by a circuit for combining the strings of ), i.e. from separate encoders The two error check pit output strings of add the two strings and subtract the strings, multiply the two strings, and divide the two strings. Or control to perform logical AND or logical OR operation between them. can be given to the data input of a mathematical logic unit.

The output from the encoder 56 or mathematical logic unit is a modified error checker. It is a string of P. p) P is then connected to one input of coupler 210. given to power. The other input of the combiner is configured to receive bit string 20B. 0 circuit 208 coupled to the input of encoder 56 is a modified error check pin) P is coupled to string 208 and string 212 is output to bus 214.

The bus 214 is connected to the input of a bit separator 216. Performs the same function as bit separator 124 of FIG. 5 except that it is not an option. , that is, the main data P and the modified error check bits Po must be transmitted. These bits must be set so that the selected attribute data Ax is not transmitted. It must be separated from bit string 212. Transmit attribute data Ax What we do is recover the selected attribute data at the receiving end without actually transmitting it. This is contrary to the present invention. Bit separator 216 is similar to that described above for bit separator 24. The actual design can have any of the following designs, and the actual design is suitable for the present invention! Essential isn't it. As should be obvious to the layperson, constructing a bit separator like this There are many different embodiments. The output of bit separator 216 at bus 218 is is applied to the input of the transmission link 32 and supplies the bit string 220 to said input. .

In connection with the embodiments described above, the transmission link 32 may include self-error checking capabilities. Good, - the human codeword is the bit string 220, the output of which is shown in FIG. The corrected receiving side bit stream 222 is then presented to the receiving side. transmission Apparatus for performing this error detection and correction in link 52 will be readily available to those skilled in the art. The received main data D' and the received modified error check bit P' are Shifted into recirculation shift register 224. The purpose of this shift register 224 stores the received bit string 222 and determines the inverse α operation. Components of classes of attribute data in non-FX specific trial and error embodiments For sequential combination of bit strings 222 with o-tn 70 with each n The bit string 222 is shifted to be output repeatedly to the input of the combiner 226. to First, an example of trial and error will be explained.

The receiving circuit receives the attribute data class D combined with D in the trial and error embodiment. Structure #: For each element (or at least the conditions of Pd' and P' For all components of the ambiguity subset of the attribute data class that satisfy ) Since the error check bit P" must be calculated, P" must be calculated. The attribute data class for unused pit and pit locations as input strings to the circuit. Combined with the ``seventy'' components to form multiple bit strings consisting of n D There is a need to. That circuit is encoder 74.

To achieve this multi-combining function, combiner 226 has another input, an attribute data cluster. bitstream consisting of bitstrings for each component of the be provided.

When each attribute data bit string reaches combiner 226, the shift register is Register 224 connects one of bit strings 230, 251, etc. to bus 252. When the bit string of the attribute data class arrives to form Shift to output string 224 in a spaced relationship.

The received P' and D' bit strings 222 correspond to each of the attribute data classes. Shift register 224 must be used once for a component. must be recirculating. Therefore, a copy of bit string 222 is shifted from bus 234 to output to combiner 226. A copy of ring 222 is also returned to the input of shift register 224 via bus 236. Shifted so that (by gate 238 at bus 256), shift register The bits shifted out from the input data D into a single string of input data D. P” error check bits for the corresponding string 222 are calculated. is returned to the shift register for the entire time. The state of this gate 238 is An active low that is a logic 0 when the cut string 222 is reaching the transmission link 52. It is controlled by a control signal designated as the signal "new D/".

The attribute data supply circuit 66 of FIG. 2 can be configured in many different ways. One of these possible embodiments is shown in FIG. 5A. Attribute data supply times The actual manner in which path 66 is configured is that the selected configuration Connects the bit strings that define each of the components of the attribute data class of the stream. The extent to which it can be fed to combiner 226 is not critical to the invention.

The particular configuration selected for the fifth person embodiment includes multiplexer 240. , which has multiple inputs, each input representing one component of the attribute data class. Corresponds to the basics. That is, each input has its corresponding constituent element of the attribute data class. It is hardwareized to a plain bit pattern. The selection signal at bus 248 is Controls which of the inputs of multiplexer 240 are coupled to output bus 228 .

If bus 228 is a serial format bus, multiplexer 240 must include a parallel-in-serial-output shift register as its output stage. . The selection signal on line 248 is applied to a group of output signal lines from counter 242. Supplied as two active signals. The count input of this counter 242 is a clock 246 is connected to the clock signal on line 244 provided by 246. Coun When the counter 242 counts clock pulses, the number of counts can vary at any particular time. of the plurality of outputs connected to bus 24B supporting the select line that is active between Each one of the outputs of counter 242, representing a particular one, is activated sequentially. As the power of the multiplexer 2400Å increases, a new one of the output bus 2 28 and thereby the corresponding component of the attribute data class of bus 228 bit pattern.

The selection signal at bus 24B is also coupled to shift register 224 as a control signal. A copy of bit string 222 is sent to combiner 226 for this shift register. Indicates when the output should be shifted to . obvious to those skilled in the art The timing and control circuitry ensures that the shift register 224 is in position at the appropriate time. using the selection signal at bus 248 to shift the It is necessary to In some embodiments, delay means 250 at bus 228 The arrival of bit string 222 and the bit representing one component of the attribute data class. used to create the proper timing relationship between the arrival of the obtain.

As will be apparent to those skilled in the art, for each component of the attribute data class 251, etc.) The particular equipment shown in FIG. 5 at the side is not important to the invention. combined Any straight line that can be used to form strings 250, 2!11, etc. Column format architecture can be used for the purpose of implementing the invention .

The combined strings 230, 251, etc. are fed to the input of the bit separator 252. It will be done. This bit separator 2520 separates the received error check bit p/ and output them to the bus 254. Bit separator 252 also a combination consisting of the received main data D combined with each component of the data class The bit strings are separated and the bit strings are sent to the stream on bus 256. output to the system. The bit strings separated in this way are 258, 259 etc.

Each of the bit strings 258, 259, etc. is applied to the encoder 740 input. It will be done. The purpose of encoder 74 is to encode bit strings 258, 259, etc. and generating P//m difference check bits for each. encoder 74 constructs the same error correction code constructed by the encoder 56 on the transmitting side. , can be designed as the same thing. In a preferred embodiment, the encoder 74 is the same as the encoder 56 and performs an error check on the received data D. Error check pitch for bit Pd' and corresponding component of attribute data class ) Pa1.

The same α operator is constructed between Pa2 and the like. mathematical and/or logical operations This α operator, or diatance, is expressed using α. Figure 5A shows that α is arbitrary. Two cases: general α or α is exclusive OR + logical operation Intended to illustrate circuits. This α operator is a mathematical and/or logical operation. Error check pin for calculated or received data D) Pd is attribute data Error check pitch for the constituent elements of the lath) Encoded together with Pa1゜Pa2 etc. In another embodiment, encoder 74 represents a sequence of operations that The same mathematical or logical operations for P” is equal to P whether used as used by 6 It may be of any other structure that generates a bit P" such as P".

The output of the encoder 74 is the bit string P1, P2... at the bus bar 260. This is a stream of Pn. Each bitstream of this stream has an attribute Error check for one component of the data class Error check pit for data D') One P# error corresponding to encoding to Pd Represents a difference check bit string.

Bus 260 is coupled to one input of syndrome generation circuit 262 . Syndro Another input of the program generator 262 is coupled to the bus 254 and outputs the received change signal. A bit string of error check bits P' is received. Syndrome occurrence times In a preferred implementation, path 262 serves to determine whether P" and P' are the same. In the example, this identity check circuit 262 is an exclusive OR circuit, but other implementations By way of example, any structure in which the amount between P" and P' can be determined embodies the invention. be satisfied with the execution.

The only one of the syndromes at busbar 264 will be all zeros. This syndrome The system is encoded at the sender and corresponds to the selected component Ax of the attribute data class. This corresponds to P" where Fax is encoded.

The syndrome focus stream at bus 264 is the same as zero detection circuit 50 in FIG. 3A. is coupled to the input of a zero detection circuit 266 having the same design. Its exit on line 268 A power signal, ie, a 0 signal, is coupled to output circuit 84. This output circuit 84 is all 0. a specific component of the attribute data class corresponding to the syndrome at bus 264 It works to output. To achieve this function, the output circuit B4 is connected to the delay circuit 2 70 to the select signal at bus 248. The purpose of the delay circuit 270 is as follows. explained below. The heart of the output circuit 84 is the configuration of each attribute data class. A multiplexer 272 having respective inputs corresponding to the elements.

Each input is hardwired into the bit pattern of the corresponding component of the attribute data class. software. Multiplexer 272 outputs the gated select signal on bus 274. signal, which is delayed in time and N by the 0 signal on line 268. (2) Selection signal at bus 248 gated by gate 276; line 26 The 0 signal at 8 remains in the logic 0 state for non-zero syndromes, tb, and When each syndrome in the line 264 reaches the multiplexer 27 The selection signal on bus 248 is prevented from reaching the selection input of bus 248. Attribute data The specific syndrome corresponding to the selected component AX of the When processed by output circuit 266, the logic state of the 0 signal on line 268 is Changes to principle 1. As a result, the gate 276 is present on the bus line 24B at that time. The select signal is gated to the select input of multiplexer 272. The delay circuit 270 Apply the cut strings 250, 232, etc. to the encoder 74 and check the P'' error. delay the selection signal for a sufficient time to allow it to be converted to a qubit string The delay circuit 270 works to detect that the syndrome corresponding to Ax is 0. 2 at the same time when it reaches circuit 266 and changes the state of the 00 signal on line 268. The gated select signal at in 274 outputs the attribute data for output to output bus 280. If sufficient delay is provided to select the appropriately selected component Ax of the class must be

As will be apparent to those skilled in the art, output circuit 84 may take any of a number of different forms. The particular configuration shown in FIG. 5A is suitable for the present invention. It's not very important. The selected configuration is generated by exclusive OR circuit 262. The appropriate selection of the attribute data class corresponding to the all-zero syndrome It is only necessary that the component be able to be output.

In FIG. 5B, the α operator configured by the encoder 56 is defined and singular. An embodiment of the invention is shown having an inverse α operator. Figure 5B is replaced by Figure 5A. As is clear, the inverse α is specified, which shows only the difference of the receiver circuit from that shown. In all such embodiments, which are both unique and unique, the receiver circuit can be fairly simple. Ru. In the embodiment shown in FIG. 5B, the incoming bitstream from the transmission link The ring is provided to bit separator 281 via bus 282. This bit separation 281 serves to separate the P' and D' bits and connects them to buses 285 and 285, respectively. and 284 separately. Encoder 285 encodes the D bit at bus 284. An error check signal (Pd') is generated on the bus line 286 in response to the error check signal Pd'. en Coder 285 is configured by encoder 56 on the transmitting side (not shown). Construct the same error correction code as . Next, the error check bit string Pd and P are generated in the Pax error check bit string on bus 288. to reverse the alpha operator encoding operation performed by encoder 56 (not shown). n is given to the inverse α operator circuit 287. This data corresponds to the attribute data Ax. Output to the output circuit 289. Figure 6A shows a book that uses an α operator for which inverse α is not specified or is not singular. A parallel data evaluation architecture implementing the direct method of the invention is shown. No. The six-person diagram embodiment can be used to determine whether α can be any general or unrestricted α operator. In two cases, the opposite represents a situation such that is an exclusive OR logical α operator. α is either unspecified or not ore-specific. On the transmission side, A to P check bit Parallel 7 format data for X6 or Fax encoding speeds up operation If this is not desired, the embodiment of the serial architecture shown in FIG. This is a very small change. That is, the main data D is processed in parallel format. The selected component Ax of the attribute data class is the selected component Ax of the attribute data class. is opened by the main data D that shortens the line supporting the component Ax This can be easily done by connecting to an unused bit position on the encoder 560 input. Simply input in parallel format for concatenation. The encoder 56 is its input) Receive IJ processing in parallel format, use any error correction code and any α calculation Output the changed check bit P in parallel format using the child do. The bit separator 216 (not shown) is a simple It is by design. Since these changes are extremely small on the transmitter side, they are detailed in Figure 6A. Not shown in detail.

The sender provides a parallel format string 290 to the transmission link 52 for transmission. do. Similarly, in the case of other embodiments, the main data D and Contains only the modified error check pin) P. The transmission link can also be used in other embodiments. It may likewise have its own error correction circuit.

On the receiving side, the received main data D' and the received changed error check bits P are processed in parallel. A plurality of latches 292, 295 etc. in column format, i.e. D The input bus 289 from the transmission link supporting ' and p'7 e/l/d is Each of the two copies of the main data D and the changed error check pitch P/ A plurality of latches 292, 2? : Connected to 5th input (parallel or series) format).

Each latch is one word long and has a modified error checking bit file. The n main data fields D combined with the field P' contain all bits of the n latches. do not occupy the same position. The unused bit positions of each two bits can be used by multiple hardware has n inputs connected to each of the bit patterns that are t represents each component of the attribute data class A1...An. . These hardware bit patterns connected to the latches of the 7-bit It exists on a plurality of busbars represented by lines 294. Of course, if the latch 292, 29 5 etc. If a serial format is desired, the attribute data class configuration Each n of elements is shifted into a corresponding latch by circuitry obvious to those skilled in the art. A suitable data handling architecture should be buses 289 and 294 in parallel and parallel formats.

After loading, latch 292 loads the D' and P' bits and the A1 attribute data component. 293 stores the combination of D' and P' bits and the attribute data cluster. Stores the combination with the SQA2 component.

The outputs of the latches 292, 295, etc. are separated.

D' and attribute data bit A, such as encoder 295 or encoder 296. n, which is dedicated to that particular latch. Therefore , latch 292 connects the A1 bit and D' bit to the input of encoder 295. has. This encoder has been modified to generate an error check (P). P1 error check using the same α operator and error correction code as n used on the sending side. Calculate the book bits.

In other configurations, encoder 295 (and all other encoders such as 296, etc.) coder), as long as one condition exists, one or more than seven operations are performed on the sending side. Functions used by one or more encoders can be expanded into sequences. any mathematical and/or logical operation, whether or not the same May be used.

In this case, the encoding performance selected for encoding by the receiving encoder is No matter what the calculation is, P for D − D’ and A = A x ′ must be generated.

70 Its encoder uses identity detection such as the same operator circuit 300, 502, etc. If the output string coupled to the circuit via the busbar is equal to work to determine. In a preferred embodiment, this identity detection circuit is an exclusive OR This is a circuit that calculates the attribute data cluster by performing the operation P"X-0RP". calculate the syndrome for that particular component of the system. In other embodiments, the same The unity detection circuit may be any circuit that detects when P'' is equal to P.

With respect to latch 292, latch 293 has D′ coupled to the input of encoder 296. output and A2 bit output. Encoder 296 has P2 error check bit. Calculate the cost. The output of encoder 296 is the output of two-bit 292 or latch 295. Equality-detecting exclusive OR circuit with inputs coupled to P' bit from either 302. All latches from the receiving side have identical copies of these P' bits. It does not matter from which source the P' bits come from to store the image.

The exclusive-OR circuit generates syndrome S2 on its output bus 304. Each The exclusive OR circuits 500, 302, etc. can be used in either parallel or series format. generate the syndrome bits and output them to one of the buses 505 and 504. do. Each of these syndrome supporting output buses such as buses 503 and 304 This is connected to the input of the zero detection circuit. In the example of the 0 detection circuit enlarged in Fig. 6A, (by the Hiro NOR gate). The syndrome bit of the output bus 304 is connected to the input of NOR gate 506, which inputs each bit of syndrome S2. It serves the purpose of determining whether the set is a logical zero. Other 0NOR gates 30 8 serves the same purpose for 0 detection of S1 syndrome.

Each latch, such as latches 292 and 293, has seventy types of attribute data classes. corresponds to this component. The same circuits also have the same characteristics as circuits 500 and 502. That is, the same can be said of the identification detection circuit. One more NOR gate is the attribute data class. It corresponds to the component of the program.

The outputs from the NOR gates of gates 506 and 508 serve as output circuits. The select input bus 510 is coupled to the select input of multiplexer 512. . This multiplexer has the attribute data corresponding to the syndrome that had all O bits. Outputs the components of the data class. The input of the multiplexer 312 is Hatch a specific bit pattern of one selected attribute data class component. hardware. The bit pattern of selection bus 512 is determined by which of these input ports. Determine whether t is connected to the output bus 314.

FIG. 6B shows an example of a direct method in which the inverse α operator is defined.

In this example, the input bitstream at bus 289 from the superchannel Rings D' and P' output the bits P' at bus 295 and D' at bus 293. is applied to cut separator 291. The encoder 297 receives the D bit and is on the transmitting side. An error correction signal (Pd) is generated using the same error correction code used. One Then, the Pd' and P' bits are sent to the inverse α operator circuit 299 that generates the Fax bit. given. Pax bit is an output that outputs attribute data corresponding to Fax bit. The signal is applied to circuit 301.

In Figure 7A, the inverse α operator is defined and the present invention is calculated using a more α operator that is singular and n. A 70-chart of a general method for performing the analysis is shown. Figure 8A is 7A shows a general apparatus for carrying out the method of FIG. 7A.

In Figure 7A, the first step is to calculate Pd using an arbitrary error correction code. This is represented by step 520 below. It is referred to as ECC◆1. This is determined by encoder 322 in FIG. 8A. be achieved. Step 524 is to send a fax to the selected attribute data Ax. The purpose is to generate error correction bits. This corresponds to circuits 326 and 528 of FIG. 8A. done by. The error correction code constructed by translator 328 is The different error correction codes or ECCs configured by the reader 522 are It's okay. Typically, 528 is a look for one small error in attribute data. Uptable or multiplexer.

Step 550 is an encoding process in which Fax is encoded into Pd using an arbitrary α operator. It's Tep. This action is ALU! i52 or other logic; is executed to perform a desired sequence of mathematical and/or logical operations. is reversed on the receiving side using only P' and D' so that t calculates the fax. The number of mathematical and/or logical operations is not important as long as it is important. In other words, the α operator is compatible with any α operator, but if the inverse operator is If the coded attribute is not unique or unique, then the trial and error method is required at the receiving end to provide identification or identity of the gender data. General like this A typical method is shown in Figure 7B. If the inverse α operator is defined and singular Then, since the receiving circuit can directly give fax from Pd' and P', The identity of Ax can be determined without trial and error iterations.

Step 354 transmits the D and P bit strings via transmission link 52. represents a step and, as in the case of the above-mentioned embodiments of this extension, has its own error compensation. It may also be a superchannel with positive and detection capabilities.

Step 3'56 is to calculate Pd from the received data D using ECC1. and This is accomplished in a known manner by circuits 358 and 540 in FIG. 8A. achieved. Encoder 540 has the same error correction as ECC◆1 used on the transmission side. The code must be constructed and finally the mathematical calculations made in step 550. The alpha sequence of operations and/or logical operations is inverted or reversed in step 542. The α operator is performed between Pd and 1 to give Fax'e. This is calculated This is done using jt7ICPd' and the received error check pin p/. A LU544, Rurui or some other logic to give Fax bit string This inverse α operation sequence is performed.

In embodiments where the inverse α is defined n and singular, the final step is 346 As shown in step 542, the mathematically given Ax corresponding to 37'cPax is Output. This is accomplished by back translator 348 in FIG. 8A.

This translator uses ECC2, typically a lookup table or MU It is X.

Figure 7B is a generalization of Figure 7A in which the inverse α operator is not defined or singular. Indicates a change in method. Figure 8B is a general hardware configuration for the method of Figure 7B. After step 356 indicating the attribute data classification, a data evaluation step 557 Error check bit P21 for the components of the This is done to encode n and Pd, respectively. This encodes Fax to Pd is done using the same α operator as n used on the sender side to derive P . In FIG. 8B, this is done by ALU 550, and this is one input. An encoder or looker that has a Pd field as from the attribute data check bit supply circuit 552 such as a top table to other inputs. It has Pa1...Pan fields that arrive sequentially. Class Pa1... ・When each component of Pan reaches the AI and U inputs, the ALU 550 Two data files are set to output presyndrome IN, Pz...Pnf. to perform alpha operator sequences of mathematical and/or logical operations between fields. controlled by. One such syndrome is that each component of an attribute data class (or at least an ambiguous subset of all configurations of the attribute data class) element) is output. Therefore, step 557 in FIG. P1...Px...Pn. Here Px is the selected attribute data class. Corresponds to the Fax error check bit for the configured component. Next, step 53 9 is against P Test each of the Pl...Px...Pn pre-syndromes for identity. It is done as it should be done. In FIG. 8B, this is done by the identifiability test circuit 354. It is done.

If only Px is the identity determination, go to this data extraction step 341. In the group, the components of the attribute data class corresponding to the line partial syndrome Px are Output. In FIG. 8B, step 541 converts Fax to the corresponding Ax A lookup table or some decoder that embodies the ECC2 so that It is configured by a back translator 356, which is one of the following.

Although the present invention has been described above in connection with preferred embodiments and modified embodiments, it will be apparent to those skilled in the art. Obviously, many modifications are possible without departing from the spirit and scope of the invention.

All such modifications are intended to be included within the scope of the claims.

Engraving (no changes to the content) Engraving (no changes to the content) Engraving (no changes to the content) FIGURE2A Engraving (no changes to the content) FIGURE 2G Engraving (no changes to the content) Engraving (no changes to the content) A× FIGLJRE, 58 A× FIGURE 3C Engraving (no changes to the content) transmission (or superchannel) FIGURE4A Engraving (no changes to the content) A% FIGURE 40 Engraving (no changes to the content) Engraving (no changes to the content) FIGURE 58 Engraving (no changes to the content) FIGURE6A Engraving (no changes to the content) A-me FIGUREG Snake Engraving (no changes to the content) FIGURE 7A Engraving (no changes to the content) FIGURE 8A Engraving (no changes to the content) From bit separator 338 x FIGLJRE 8B Procedural amendment (voluntary) name of invention 2. Articles related to the design Main data HA　For encoding attribute data into M check symbol and 1M encoding Apparatus and method 3, person making corrections Relationship to the case: Patent applicant Name: Ampex Corporation/International Search Report

Claims (23)

[Claims] (1) Encode the attribute data in the error check symbol of the main data and encode it after transmission. Decode specific attribute data encoded from main data and error check symbols. However, the above attribute data is specified by the class of the attribute data component. For devices such as combined to receive the above main data and attribute data components, and to the above main data. generating a first main data error check symbol for the first main data error check symbol; Modified error check by encoding the check symbol along with the above attribute data components a first means for generating a symbol; and a first means for generating the main data and the above from the first means. Combined to receive modified error checking symbol, attribute data component Generates and receives a set of attribute check symbols for each component of the class. error check symbol, the second main data error check symbol, and attribute data structure. Decode the above attribute check symbols corresponding to the individual components of the above classes of components. and detecting the identity of the attribute data making the above modified error check symbol. means and The above-mentioned device is characterized by comprising: (2) For the apparatus recited in claim 1, the first means includes error correction. Translate the above main data into the above first main data error check symbol according to the code The above class of attribute data components according to the first translation means and some code for a second one that translates one selected component of a translation means, and is coupled to said first and second translation means and said modified The above first main data error check symbol and the above attributes to create an error check symbol The device described above is characterized in that it performs a symbol-to-symbol logical operation with a check symbol. (3) In the device according to claim 1, the first main data error check the second means is generated according to an error correction code; To translate the above main data into a second main data error check symbol according to the code and the third translation means to generate a partial syndrome. the second main data error check symbol generated by the means and the first means; Perform symbol-to-symbol logic operations with the above modified error check symbol received from of each of the above classes of attribute data components, including partial syndrome generation means. A check symbol provider for supplying the above set of attribute check symbols corresponding to the component. the check symbol supply means and the partial syndrome generation means; detect the identity of the attribute data combined with the above to make the modified error check symbol one symbol corresponding to each of the above classes of attribute data components. Clustering of the above partial syndrome and attribute data components to generate a drome. A symbol pair between each set of the above attribute check symbols corresponding to one component of the The device as described above, further comprising syndrome generating means for performing symbolic logic operations. (4) In the device according to claim 3, the syndrome generating means combined and identifying the above selected components of the above classes of attribute data components. further comprising identification detection means for testing said syndrome to determine. The above-mentioned device is characterized in that: (5) In the device according to claim 4, the device is coupled to the identification detection means. , an attribute data structure corresponding to the syndrome identified by the above identification detection means. An apparatus as described above, characterized in that it outputs selected components of said class of elements. (6) In the device according to claim 5, the identification detection means may detect 0 times. A system that identifies selected components of the above class of attribute data components. The drome is all 0, and further includes a plurality of 0 detection logic means, each of which Individuals are encouraged to suffer from one of the above syndromes and develop that particular syndrome. each output means generates a control signal indicating whether or not all the signals are zero. one which is all zeros coupled to each said control signal from said zero detection logic means of said The above characterized in that the attribute data component corresponding to the syndrome is outputted. Device. (7) In the device according to claim 3, the check symbol supplying means is A set of attribute checks corresponding to each of the above classes of attribute data components. The above syndrome generating means can be applied to multiple output buses by simultaneously supplying the including alternative OR logic means, each of which is connected to each of said output buses and said partial synchronizer. and the syndrome is combined with the cluster of attribute data components. The above partial to produce a corresponding syndrome of one component of the The above attributes correspond to one component of the syndrome and attribute data component classes. It is characterized by performing a symbol-to-symbol exclusive OR logical operation with the gender check symbol. The above device. (8) Error check record of main data to generate a changed error check symbol. encode attribute data in the signal and, after transmission, specify the specific attribute data encoded in this way. The data is decoded from the main data and the changed error check symbol, and the above attribute data is to the device as determined by the class of the selected attribute data component. of the above attribute data class to generate a modified error check symbol. To encode one selected component into the error check symbol of the above main data a first encoding means of; combined to receive the above main data and the above modified error check symbol; These are decoded and the attribute data encoded in the above modified error check symbol is obtained. first decoding means for providing an identification of a selected component of said class of components; , The above-mentioned device is characterized by comprising: (9) In the device according to claim 8, the above attribute data class The selected component is encoded by the encoding means according to the encoding algorithm. , and the first decoding means is providing each of the above components of the above class of attribute data components and providing the attribute data Each component of the class is first combined with the main data received above to create a data file. an attribute data supply means for forming a field; One pre-syndrome for each component of the above class of attribute data components. Each field main data is generated according to the above encoding algorithm. a second translating the data into at least one pre-syndrome group of check marks; encoding means; each of the above pre-syndromes and the above received modified error check symbol. Which of the above pre-syndromes has been modified as received above? A symbol-to-symbol identification check is performed to check whether the Syndrome generation means for conducting a check, The above-mentioned device is characterized by comprising: (10) In the device according to claim 9, the first encoding means may be Encoding the attribute data component according to the difference correction code, and the attribute data supplying means is a set of multiple busbars each supporting one component of the above attribute data class Supplying all components of the above classes of attribute data components to different buses simultaneously The second encoding means includes a plurality of error check symbol calculation circuits, Each of the above received masters is combined with an attribute data component on one of the buses. each of the above error channels is coupled to receive a field of data consisting of data; The check symbol calculation circuit processes the data according to the error correction code of the first encoding means. One of the above pre-syndromes by translating that received field of data. The syndrome generating means includes a plurality of exclusive OR logic means. , each of which receives the above received modified error check symbol at its first input. and between them receive the above pre-syndrome at the second input. A symbolic-to-symbolic exclusive OR logic operation is performed to determine whether each syndrome is simultaneous occurrence of at least one syndrome corresponding to one of the The above device characterized by: (11) In the device according to claim 8, the first encoding means: Selected components of the above classes of attribute data components according to the error correction code The above modified error check can be performed by encoding the above into the main data error check symbol. The main data error of the selected component of the attribute data class Encoding into a check symbol is a sequence of at least one logical or mathematical operation. Therefore, the above sequence has a defined and unique inverse sequence, and the above sequence has a defined and unique inverse sequence. The first decoding means generates a first main data error check symbol from the main data. the above code according to the code used in the first encoding means to produce a A second means data error check symbol from the means data received from the first encoding means. and the identification of selected components of the above attribute data class. The above second means data error check symbol and the above modified error check to give and a means for giving a reverse sequence between the mark and the mark symbol. The above device. (12) Encode the attribute data into the main data error check symbol and encode the attribute data with the above attribute code. Specified attribute data encoded in this way can be uploaded after transmission without transmitting data. Decoded from the recorder data and error check symbol, and the above attribute data is the selected attribute. In the device as defined by the class of sexual data components, Generates a first main data error check symbol for the above main data, and generates an attribute data attribute error check corresponding to one selected component of the above class of data component. The error check symbol is modified by encoding the first main data error check symbol together with the check symbol. A first means for generating a check symbol, the above-mentioned changed error check symbol, and the above-mentioned main data. Attribute error charts corresponding to each of the above classes of data and attribute data components. and the first main data error check symbol by the first means. The above selected from the above classes of attribute data components encoded in check symbols. a second means for confirming the identity of the component; The first means is coupled to the second means, and the first means and the second means are connected to each other. a data transmission means for transmitting the main data and the changed error check symbol; This data transmission means transmits the above main data and the above changed error check record. These individual error checks can be performed by generating separate error check symbols for each symbol. a means for transmitting a symbol, said data transmitting means being said main cheetah; and the above main data and data generated during transmission after receiving the above changed error check symbol. Detects and corrects errors in the changed error check symbol above, and corrects the main data and a changed error check symbol is given to the second means. The above device as a sign. (13) one selected component of the field of the first Cheetah component to the second encoded into error check symbols of the data and the actual transmission of the selected components above. After transmitting the error check symbol and the second data, the first data structure is in an apparatus for recovering said selected component of said field of component; Then, the above second data and the first data are combined to generate a modified error check symbol. the selected component of the field of the data component; means for transmitting the second data and the modified error check symbol; A data transmission means and an error check symbol for the second data are individually generated. The changed error check symbol and the second data are transmitted from the data transmission means to recover the above error check symbol and the above changed data for the above second data. the first error check symbol by performing a predetermined logical operation between the The first step of calculating the identity of the selected component of the field of the data component. 2 means and The above-mentioned device is characterized by comprising: (14) The device according to claim 13, which is coupled to the second means. and identifies which components of the fields of the first data component are to be calculated. means for outputting said selected component of the field of the first data component; The above device further comprising: (15) Main data and known attributes along with error check symbols related to this main data. The information regarding the attribute data defined by the set of gender data is stored in the implementation of this attribute data. In the method of transmitting without actual transmission, The first generated from the above main data to generate a modified error check symbol. Encode the main data error check symbol along with information that identifies the above attribute data. transmitting the main data and the modified error check symbol; Receive the above main data and the above changed error check symbol, and receive the main data and the received modified error check symbols regarding the attribute data. generating a syndrome containing information; The above method consists of: (16) Identification of selected attribute data being encoded as well as main data and related information. In a method of transmitting error check symbols, combining the selected attribute data and the main data; From the combined string of attribute data and main data according to the error correction code generating a modified error correction symbol; transmitting the main data and the changed error check symbol; combining the selected attribute data and the transmitted main data; An input screen consisting of the above transmitted main data combined with the above selected attribute data. Add the above error correction code to generate the above modified error check symbol in the string. The above modified error check symbol will cause pre-syndrome according to the code. The above pre-syndrome identifies the selected attribute data component that will be generated. predetermined between the system symbol and the modified error check symbol transmitted above. Generating a syndrome by performing logical operations The above method consisting of: (17) selected attribute data defined by the data class of the known component; main data by encoding the data into error checking symbols generated by the main data. In a method of transmitting data representing one selected attribute of the data, First main data error check for the above main data according to the error check code Calculating the symbol, generating a modified error check symbol, is specified and attribute data structure according to a predetermined logical operation having a unique inverse logical operation. The above first main data with the attribute error check symbol associated with the selected component of the component. encoding the data error check symbol, the above main data and the above modified error; transmitting a check symbol; By reversing the above predetermined logic operation and the above modified error check check symbol and the second main data error check symbol generated from the received main data. Perform inverse logical operation using the above error correction code between the two input fields that make up the By performing the calculation, the attribute data encoded in the above changed error check symbol is calculating the components of the data; How to become more. (18) Encoding attribute data into error check symbols generated for main data represents one selected component of a class of known attribute components by In a method for transmitting data, Calculate the first error check symbol for the above main data according to the linear error correction code. Calculating the above selected attribute component classes according to the linear error correction code generating a second error check symbol from the component; Predetermine between the above error check symbols to generate a modified error check symbol. The above first error check symbol can be checked by performing a specified logical operation. encoding an error check symbol; transmitting and receiving the main data and the modified error check symbol; so as to give data representing the above selected components of the above known attribute components. The above by reversing the sequence of logical operations done in the encoding step above. of the above attribute class using the received main data and the modified error check symbol. calculating a syndrome for at least one component; How to become more. (19) In the method according to claim 18, the encoding step The logic operation described above is a binary addition of the first and second error check symbols, and the logic operation described above is a binary addition of the first and second error check symbols. The above calculation step of reversing the operation is the above linear error correction code of the above encoding step. Generation of the third error check symbol from the received main data according to the code and the third error check symbol between the error check symbol of 3 and the modified error check symbol received above. A method as described above, characterized in that it is a binary subtraction performed. (20) In the method according to claim 18, the encoding step The logical operation is an exclusive OR logical operation between the first and second error check symbols. Yes, the above calculation step is received according to the above error correction code of the above encoding step. generating a third error check symbol from the received main data; generate a set of fourth error checking symbols for each component of the rath, and Exclusive OR between the changed error check symbol and the third error check symbol Performing logical operations to generate partial syndromes, the above partial syndromes and each set of the fourth error check symbols. including the occurrence of at least one syndrome, and each syndrome The above method is characterized in that the symbol corresponds to one set of the fourth error check symbols. Law. (21) Encode the attribute data with error check bits of the main data and Transmits the above main data and the encoded error check bits above without transmitting the data. The above attribute data is extracted from the main data transmitted and the encoded error check bits. and the above attribute data is determined by the class of the attribute cheetah component. In this method, First main data error check on the above main data according to the linear error correction code Generate bit, modified error check to generate bit Exclusive OR logic between data error check bit 1 and attribute error check bit The above attribute data components according to the above linear error correction code by performing the with attribute error check bits given by one selected component of the class of changing the first main data error check bit; transmitting the changed error check bits and the main data; receiving the main data and the modified error check bit; The second main data error is detected from the received main data according to the linear error correction code above. generating a difference check bit; The above second main data error check bit and the above received modified error check. Partial simulation is performed by performing a bit-by-bit exclusive OR logic operation between the bits and generating an undrom, A set of attribute error checks for each component of a class of attribute data components bits and the set of each of the attribute error check bits and the partial system. By performing a bit-by-bit exclusive OR logical operation between syndrome of the above selected configuration elements of the above attribute data class. Identify the syndrome of the above multiple syndromes that are known values corresponding to the prime thing, outputting attribute data corresponding to the identified syndrome; How to become more. (22) By encoding the error check symbols generated for the main data. information about an attribute data component selected from a class of attribute data components In the method of transmitting The above selected attribute cheater structure at the most significant bit position according to the linear error correction code. Calculate the modified error check symbol for the above main data combined with the component transmitting and receiving the main data and the modified error check symbol; thing, The above error correction code of the attribute data component at the maximum error bit position according to the above error correction code. each bitstream from the above received main data combined with one component of the A plurality of sets of second error chips are generated from a plurality of bit strings such that a ring is constructed. calculating a check symbol for each of said set of said second error check symbols and said performing an exclusive OR logical operation with the received modified error check symbol; Therefore, multiple syndromes may occur, How to become more. (23) Encode the attribute data into the error check symbol of the main data and encode it after transmission. The specific attribute data encoded in this way is extracted from the main data and error check symbol. decrypts the above attribute data as defined by the class of the selected attribute data component. The device that is configured to receive the above main data and attribute data components. and emit a first main data error check symbol for the main data. the first main data error checker so as to produce a fresh and modified error check symbol; a first means for encoding a mark symbol in the attribute data component; The result is to receive the above main data and the above modified error check symbol from the means of and generates a second main data error check symbol from the received main cheetah, and The above-mentioned changed error check symbol and the above-mentioned second main data error check record. Confirm the identity of the attribute cheetah by decoding the code and making the above modified error check symbol a second means for causing the The above-mentioned device is characterized by comprising: