JPS635016Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a depth sounding device that counts and displays the distance to the seabed in water depth measurement using sound waves.

Conventionally, this type of sounding device that displays counts has selected the counting unit by artificially changing the clock cycle of the counting circuit. For example, in the case of 4 digits, the clock of the counting circuit was artificially switched between when the counting unit was 0.1 m and when it was 1 m.
If the clock of the counting circuit is fixed in this way, if the counting circuit overflows, measurement becomes impossible. That is, when the display unit was selected to be 0.1 m, there was a drawback that if the display digit was 4 digits, it would be impossible to measure when the water depth was 1000 m or more.

An object of the present invention is to provide a device that loads "1" into the most significant digit of the counting circuit and automatically switches the clock cycle of the counting circuit to perform counting when the counting circuit overflows.

Examples of the present invention will be described below.

In FIG. 1, 1A, 1B, 1C, and 1D indicate numeric displays, which constitute a four-digit display. 2A, 2B, and 2C indicate the counting unit with a decimal point display. Displays 1A, 1B, 1C, and 1D display the stored numerical values of latch circuits 3A, 3BB, 3C, and 3D, respectively. Latch circuit 3A, 3B, 3C, 3
D stores each count value of the counting circuits 4A, 4B, 4C, and 4D. Counting circuit 4A, 4B, 4
C and 4D each consist of a decimal counting circuit, where counting circuit 4D receives the carry pulse of counting circuit 4C, counting circuit 4C receives the carry pulse of counting circuit 4B, and counting circuit 4B receives the carry pulse of counting circuit 4A. Count each. Then, the counting circuit 4A counts the clock pulses from the gate circuit 5.

Counting circuits 4A, 4B, 4C, 4D are transducer 7
The time from when the ultrasonic pulse is emitted until the reflected wave from the detected object returns to the receiver 9 is counted.

The transmitter 6 periodically generates a start pulse (FIG. 2a) and at the same time generates an excitation pulse (FIG. 2b) to excite the transmitter 7. The reflected wave from the detected object is captured by the receiver 9 (Fig. 2c) and guided to the receiver 8, where only the seabed reflection is extracted and becomes a stop pulse (Fig. 2d).

The start pulse a is the counting circuit 4A, 4B, 4
At the same time as resetting C, 4D and the frequency dividing circuit 10, the flip-flop 11 is set, and when the stop pulse d is applied to the flip-flop 11 from the receiver 8, it is reset and the gate wave (Fig. 2e)
generate. By counting the duration of this gate wave e, the distance to the detected object can be counted. The period of the clock pulse of this gate wave e becomes longer each time the counting circuit 4D overflows, and the counting unit is automatically switched to automatically display the distance and the counting unit. This will be explained below.

The output of the frequency divider circuit 10 is decoded by the decoder 12, and the output thereof is gate circuit 13A, 13B, 1
Control 3C. The clock pulse from the clock pulse source 14 is frequency-divided by a frequency dividing circuit 15 to 1/10, and further frequency-divided by a frequency dividing circuit 16 to 1/10. Further, the clock pulses from the clock pulse source 14 are sent to the gate circuit 13A, the output pulses from the frequency divider circuit 15 are sent to the gate circuit 13B, and the output pulses from the frequency divider circuit 16 are sent to the gate circuit 13C. Any one of these gate circuits 13A, 13B, and 13C is turned on, and the clock pulse that has passed through this gate circuit is applied to the counting circuit 4A through the OR circuit 17 and the gate circuit 5.

When the counting circuit 4D overflows, its output drives the monostable circuit 18;
An output is generated (FIG. 2f). This output forcibly loads the counting circuit 4D to "1" and is also applied to the frequency dividing circuit 10.

When the start pulse a is first applied to the frequency divider circuit 10, the frequency divider circuit 10 becomes zero and the decoder 12
The output turns on the gate circuit 13A and turns off the gate circuits 13B and 13C. Counting circuit 4D
Each time the overflow occurs, one clock pulse is applied to the frequency divider circuit 10, and the frequency divider circuit 10 increments the counter. At the first overflow, the output of the decoder 12 is sent to the gate circuit 13B.
is turned on, gate circuits 13A and 13C are turned off, and when the second overflow occurs, the output of the decoder 12 turns on gate circuit 13C and turns off gate circuits 13A and 13B.

Normally, the speed of sound in seawater is 1500 m/sec.
In the case of a depth sounder, if the water depth is D and the time from transmission to reception of seafloor reflected waves is T, then T
=2D/1500=D/750. In other words, 1m of water depth is 750
Hz, a depth of 0.1m corresponds to one cycle of 7.5kHz, and 0.01m corresponds to one cycle of 75kHz. Therefore, if the counting unit is m, a 750Hz clock pulse is used, and if the counting unit is 10cm, a 7.5kHz clock pulse is used.
If it is cm, just count 75kHz clock pulses. For example, if the frequency of the clock pulse source 14 is
If it is 75kHz, 75kHz from gate circuit 13A
clock pulses are supplied to the counting circuit 4A, and the counting circuits 4A, 4B, 4C, and 4D count up to 99.99 m. If the stop pulse d is not applied here, the counting circuit 4D will overflow. When the first overflow occurs, the counting circuit 4D is loaded to "1" and at the same time the gate circuit 13A is loaded.
is turned OFF, and a 7.5kHz clock pulse is supplied from gate circuit 13B to 4A for a count of 100.0m.
Count from to 999.9m. Furthermore, if the stop pulse d is not applied, the counting circuit 4D causes a second overflow. Therefore, the counting circuit 4D is loaded to "1" and at the same time the gate circuit 13B
is turned OFF, and a 750Hz clock pulse is supplied from the gate circuit 13C to the counting circuit 4A, which counts from 1000m to 9999m.

As mentioned above, when the start pulse a is generated from the transmitter 6, the flip-flop 11 is set, and the gate circuit 13A is turned on and the clock pulse source 1 is turned on.
4 clock pulses are supplied to the counting circuit 4A through the gate circuit 13A, the OR circuit 17, and the gate circuit 5 to perform counting. Until the stop pulse d from the receiver 8 is applied, if the counting circuit overflows as described above, "1" is loaded into the most significant digit of the counting circuit and the counting clock is automatically switched. When counting is performed and a stop pulse d is applied from the receiver 8, the flip-flop 11 is set, the gate circuit 5 is turned off, and no clock pulse is supplied to the counting circuit 4A, and the counting circuits 4A, 4B, 4C, and 4D stop counting. . At this time, the count values of the counting circuits 4A, 4B, 4C, and 4D are set to the latch circuits 3A, 3B, 3C, and 3D by the stop pulse d, respectively.
The count values are displayed on the displays 1A, 1B, 1C, and 1D. At the same time, when a stop pulse d is applied, the output of the decoder 12 is latched by the latch circuits 19A, 19B, and 19C, and displayed on the displays 2A, 2B, and 2C. One of the indicators 2A, 2B, and 2C lights up. That is, as described above, the decoder 12 selects the clock pulses to be supplied to the counting circuit 4A.
This is to display the output of Therefore, indicator 2
A, 2B, 2C are indicators 1A, 1B, 1C, 1D
The counting unit of the numerical value displayed will be displayed.

As explained above, the present invention switches the period of the clock pulse supplied to the counting circuit to a clock pulse with a longer period than the clock pulse before the overflow every time the count value of the counting circuit overflows. ” and count with long period clock pulses,
This has the effect of automatically storing and displaying the count value when the clock pulse disappears and the count unit based on the number of overflows.

[Brief explanation of the drawing]

FIG. 1 shows a circuit section of an embodiment of the present invention as a block diagram, and FIG. 2 shows timing waveforms of each section in FIG. 1... Number display, 2... Decimal point display, 3...
... Latch circuit, 4 ... Counting circuit, 5 ... Gate circuit, 6 ... Transmitter, 7 ... Transmitter, 8 ... Receiver, 9 ... Receiver, 10 ... Frequency dividing circuit, 11 ……
Flip-flop, 12... Decoder, 13...
Gate circuit, 14...Clock pulse source, 15...
...Frequency dividing circuit, 16... Frequency dividing circuit, 17... OR circuit, 18... Monostable circuit, 19... Latch circuit.

Claims (1)

[Scope of utility model registration request] In a sounding device that emits sound waves toward the ocean floor, receives reflected signals from the ocean floor, and counts and displays the depth to the ocean floor, each time the count value of the counting circuit overflows, the most significant digit of the counting circuit is At the same time as loading "1", the period of the clock pulse of the counting circuit is switched to a clock pulse with a period one digit longer than the clock pulse before overflow, and counting is performed. A sounding device characterized by memorizing and displaying counting units.